JP5862420B2 - Clock driver circuit - Google Patents

Description

  The present invention relates to a clock driver circuit.

  A semiconductor integrated circuit generally includes a clock driver circuit that supplies a clock signal to a circuit block in order to synchronize internal operations.

  Patent Document 1 discloses a clock driver including a differential signal generation unit that generates a differential signal composed of a signal having the same logic as the clock signal and a signal having the opposite logic to the clock signal, and a wiring pair that transmits the differential signal. A circuit is described.

JP-A-9-191243

  In recent years, the influence of power supply noise on circuit operation has increased due to the increase in operation speed of semiconductor integrated circuits. As a countermeasure, the decoupling capacitance provided in the circuit is increased. Increasing the decoupling capacitance increases the circuit area. However, the technique described in Patent Document 1 does not mention at all about increasing the decoupling capacitance while suppressing an increase in circuit area as a noise countermeasure.

  The present invention has been made to solve such a problem, and an object of the present invention is to provide a clock driver circuit capable of increasing the decoupling capacitance while suppressing an increase in circuit area.

  A clock driver circuit according to the present invention includes first and second wirings formed in parallel, a first signal input circuit for driving the first wiring by a driving signal having the same theory as the input clock signal, and an input clock. A second signal input circuit that drives the second wiring based on the signal; and an output circuit that synthesizes the signals obtained via the first and second wirings and outputs an output clock signal; When the control signal indicating the active state of the input clock signal indicates that the input clock signal indicates the active state, the second signal input circuit drives the second wiring with a drive signal having the same theory as the input clock signal. When the input clock signal indicates an inactive state, the signal drives the second wiring by the input clock signal and the inverted logic drive signal.

  According to the present invention, it is possible to provide a clock driver circuit that further increases the decoupling capacitance while suppressing an increase in circuit area.

FIG. 3 is a diagram illustrating a clock driver circuit according to the present embodiment according to the first embodiment; FIG. 2 is a diagram illustrating the clock driver circuit according to the first embodiment in more detail. 1 is a diagram illustrating a main buffer circuit according to a first embodiment; FIG. 3 is a diagram illustrating a clock driver circuit according to a second embodiment;

Embodiment 1
Embodiments of the present invention will be described below with reference to the drawings. The clock driver circuit according to the present embodiment forms a decoupling capacitor when an input clock signal is inactive.

  FIG. 1 is a diagram illustrating a clock driver circuit according to the present embodiment. The clock driver circuit 1 includes a signal input circuit 2 as a first signal input circuit, a signal input circuit 3 as a second signal input circuit, a wiring 4 as a first wiring, and a second wiring as a second wiring. A wiring 5 and an output circuit 6 are provided, and a control signal S is input from the outside.

  The signal input circuit 2 drives the wiring 4 with a drive signal having the same theory as the input clock signal. The signal input circuit 3 drives the wiring 5 based on the input clock signal. When the control signal S indicating the active state of the input clock signal indicates the active state, the signal input circuit 3 drives the wiring 5 with a drive signal having the same theory as the input clock signal. When the control signal S indicates an inactive state, the signal input circuit 3 drives the wiring 5 by the input clock signal and the inverted logic drive signal.

  Here, the input clock signal N1 being active indicates a state in which the logic level of the input clock signal N1 is periodically switched. On the other hand, that the input clock signal N1 is inactive indicates a state where the logic level of the input clock signal N1 is fixed to High or Low.

  The wiring 4 and the wiring 5 are formed substantially in parallel on the semiconductor integrated circuit. The wiring 4 is connected between the signal input circuit 2 and the output circuit 6. The wiring 5 is connected between the signal input circuit 3 and the output circuit 6.

The output circuit 6 combines signals obtained via the wiring 4 and the wiring 5 and outputs an output clock signal.

  Thereby, when the input clock signal is in an inactive state, the wirings 4 and 5 provided in parallel have different potentials, so that a decoupling capacitor is formed.

  In general, the clock driver circuit has been designed so as to reduce the wiring capacity in order to improve the signal speed. Therefore, the inter-wiring capacitance formed when the clock signal is inactive has a small value as a decoupling capacitance.

  In the clock driver circuit 1 according to the present embodiment, when the clock signal is activated, the wirings 4 and 5 are driven by the same logic drive signal, so even if the inter-wiring capacitance is increased, the signal speed is affected. Absent. Therefore, the inter-wiring capacitance between the wirings 4 and 5 can be increased, and the decoupling capacitance is further increased, so that a clock driver circuit with more excellent noise resistance can be obtained.

  FIG. 2 is a diagram showing the clock driver circuit 1 according to the present embodiment in more detail. In FIG. 2, for convenience of explanation, the wirings 4 and 5 are collectively described as a wiring part 7.

  The signal input circuit 2 includes a buffer circuit 21 and a buffer circuit 22. The signal input circuit 3 includes an inverter circuit 31, a buffer circuit 32, a selector circuit 33, and a buffer circuit 34. The buffer circuit 22 and the buffer circuit 34 form a main buffer circuit 40.

  The wiring unit 8 includes a wiring 4 and a wiring 5. The wires 4 and 5 are formed by dividing one wire by a slit.

  The output circuit 6 includes a buffer circuit 61, an inverter circuit 62, a buffer circuit 63, and a selector circuit 64.

  An input clock signal N1 is input from the input terminal 10, and the input clock signal N1 is input to the signal input circuit 2 and the signal input circuit 3.

  The buffer circuit 21 of the signal input circuit 2 outputs a drive signal N2 having the same logic as that of the input clock signal N1, and the buffer circuit 22 receives a drive signal N3 having the same logic as that of the drive signal N2, that is, the same logic as that of the input clock signal N1. Output.

  The inverter circuit 31 of the signal input circuit 3 outputs an input clock signal N1 and an inverted logic drive signal N4. The buffer circuit 32 outputs a drive signal N5 having the same logic as the input clock signal N1.

  The selector circuit 33 selects one of the drive signals N4 and N5 by selecting one of the inverter circuit 31 and the buffer circuit 32 according to the control signal S input from the control terminal 13. The drive signal N6 is connected to the buffer circuit 34. The buffer circuit 34 outputs a drive signal N7 having the same logic as the drive signal N6.

  Here, the control signal S is a signal indicating the active state of the input clock signal N1. The control signal S is at a high level (for example, a power supply voltage) when the input clock signal N1 is in an active state, and is at a low level (for example, a ground voltage) when the input clock signal N1 is in an inactive state.

  The selector circuit 33 selects the buffer circuit 32 when the input clock signal N1 is in an active state, that is, when the control signal S is at a high level (for example, a power supply voltage). Therefore, the drive signal N6 is a signal having the same logic as that of the input clock signal N1.

  The selector circuit 33 selects the inverter circuit 31 when the input clock signal N1 is inactive, that is, when the control signal S is at a low level (for example, ground voltage). Therefore, the drive signal N6 is a signal having a logic opposite to that of the input clock signal N1.

  The buffer circuit 61 outputs an output clock signal N8 having the same logic as that of the drive signal N3 obtained via the wiring 4. The inverter circuit 62 outputs a drive signal N9 having a logic opposite to that of the drive signal N7 obtained via the wiring 5. The buffer circuit 63 outputs a drive signal N10 having the same logic as the drive signal drive signal N7 obtained via the wiring 5.

  The selector circuit 64 selects one of the inverter circuit 62 and the buffer circuit 63 according to the control signal S input from the control terminal 13, so that the input clock signal N <b> 1 among the drive signals N <b> 9 and N <b> 10 is selected. Those having the same logic are selected and output as an output clock signal N8. The output terminal 12 outputs an output clock signal N8.

  That is, the selector circuit 64 selects the buffer circuit 63 when the input clock signal N1 is in an active state, that is, when the control signal S is at a high level (for example, a power supply voltage), and when the input clock signal N1 is in an inactive state. That is, when the control signal S is at a low level (for example, ground voltage), the inverter circuit 62 is selected.

  When the input clock signal N1 becomes inactive at a high level (for example, power supply voltage), the drive signal N3 output via the signal input circuit 2 is at a high level (for example, power supply voltage), and the wiring 4 is high. Drive at level (for example, power supply voltage). At this time, in the signal input circuit 3, the selector circuit 33 selects the inverter circuit 31 according to the control signal S, so that the drive signal N7 output from the signal input circuit 3 has a low level (opposite logic of the input clock signal N1). The wiring 5 is driven at a low level (for example, ground voltage).

  In the output circuit 6, the drive signal N3 obtained through the wiring 4 is at a high level (for example, power supply voltage), the drive signal N7 obtained through the wiring 5 is at a low level (for example, ground voltage), and the selector circuit 64 of the output circuit 6 The inverter circuit 62 is selected.

  Thereby, when the input clock signal N1 is inactive, a capacitance is formed by the wiring portion 7. Further, the output of the selector circuit 64 of the output circuit 6 is at a high level (for example, power supply voltage), and the output of the buffer circuit 61 and the output of the selector circuit 64 have the same potential. There is no problem even if they are short-circuited.

  The buffer circuit 22 and the buffer circuit 34 of the signal input circuit 2 when the capacitor is formed will be described in more detail. FIG. 3 is a diagram illustrating an example of the main buffer circuit 40. As shown in FIG. 3, the buffer circuit 22 includes a PMOS transistor 221, an NMOS transistor 222, a PMOS transistor 223, and an NMOS transistor 224.

  The PMOS transistor 221 and the NMOS transistor 222 form an inverter 225 connected to the power supply VDD and the ground GND. The PMOS transistor 223 and the NMOS transistor 224 form an inverter 226 connected to the power supply VDD and the ground GND. The inverter circuit 225 and the inverter circuit 226 are connected in series.

  The buffer circuit 34 includes a PMOS transistor 341, an NMOS transistor 342, a PMOS transistor 343, and an NMOS transistor 344.

  The PMOS transistor 341 and the NMOS transistor 342 form an inverter 345 connected to the power supply VDD and the ground GND. The PMOS transistor 343 and the NMOS transistor 344 form an inverter 346 connected to the power supply VDD and the ground GND. An inverter circuit 345 and an inverter circuit 346 are connected in series.

  Here, a case where the input clock signal N1 is inactive will be described. For example, when the input clock signal N1 is at a high level (for example, a power supply voltage), that is, inactivated by the power supply voltage, the PMOS transistor 223 constituting the inverter circuit 226 at the subsequent stage of the buffer circuit 22 has a gate input N41 at a low level ( For example, the ground voltage), that is, the ground voltage is turned ON, and the drive signal N3 of the signal input circuit 2 is set to a high level (for example, a power supply voltage).

  Similarly, when the input clock signal N1 becomes inactive at a high level (for example, power supply voltage), the NMOS transistor 344 constituting the inverter circuit 346 at the subsequent stage of the buffer circuit 34 has a gate input N42 at a high level (for example, power supply). Voltage) is turned ON, and the drive signal N7 of the signal input circuit 3 is set to a low level (for example, ground voltage).

  Here, since the buffer circuits 22 and 34 require a high driving force, they are designed with a low resistance. Therefore, when the PMOS transistor 223 is ON, the wiring 4 is connected to the power supply VDD with a low resistance. Similarly, when the NMOS transistor 344 is ON, the wiring 5 is connected to the ground GND with a low resistance.

  Furthermore, since the wiring part 7 generally needs to be operated at a high frequency, a wiring layer having a larger wiring film thickness is used to reduce the resistance. Therefore, the wiring 4 and the wiring 5 are connected to either the power supply VDD or the ground GND, respectively. Therefore, when the input clock signal N1 is in an inactive state, the wiring portion 7 has a low-resistance, large-capacity decoupling capacitance (power decoupling capacitance) between the power supply VDD and the ground GND. It is formed.

  The clock driver circuit 1 according to the present embodiment can realize a larger power supply decoupling capacitance when the input clock signal N1 is in an inactive state. Thus, for example, when a part of the chip such as a multi-core is selectively operated, the power decoupling capacitance of the clock driver circuit 1 is increased, so that noise generated in other operation units can be reduced. By reducing the noise, the operation unit can be operated at higher speed, and the performance of the entire semiconductor integrated circuit can be improved. Further, since the clock driver circuit 1 increases the decoupling capacity by increasing the inter-wiring capacity, the circuit area can be increased even if the decoupling capacity is increased as compared with the case where a new decoupling capacity is provided. Increase can be suppressed.

Embodiment 2
FIG. 4 is a diagram illustrating the clock driver circuit 10 according to the present embodiment. The present embodiment is different from the clock driver circuit 1 in that a wiring is further added to the wiring unit 7. The wiring unit 7 includes a wiring 4a, a wiring 5, and a wiring 4b. The wirings 4a, 5 and 4b are formed in parallel, and the wiring 4b is formed on the side opposite to the wiring 4a with respect to the wiring 5. One end and the other end of the wiring 4b are connected to one end and the other end of the wiring 4a, respectively, and bypass the one end and the other end of the wiring 4a.

  Thereby, when the input clock signal N1 is in an inactive state, an interwiring capacitor 7a is formed between the wiring 4a and the wiring 5, and an interwiring capacitor 7b is formed between the wiring 5 and the wiring 4b. Thus, a larger decoupling capacitance can be formed as compared with the first embodiment.

  Note that the present invention is not limited to the above-described embodiment, and can be changed as appropriate without departing from the spirit of the present invention.

DESCRIPTION OF SYMBOLS 1 Clock driver circuit 2, 3 Signal input circuit 4, 4a, 4b, 5 Wiring 6 Output circuit 7 Wiring part 7a, 7b Between wiring capacity 10 Clock driver circuit 11 Input terminal 12 Output terminal 13 Control terminal S Control signal N1, N8 input Clock signal N2 to N7, N9, N10 Drive signal 21, 22 Buffer circuit 31 Inverter circuit 32, 34 Buffer circuit 33 Selector circuit 40 Main buffer circuit 61, 63 Buffer circuit 62 Inverter circuit 64 Selector circuit 221, 223 PMOS transistor 222, 224 NMOS transistor 225, 226 Inverter circuit 341, 343 PMOS transistor 342, 344 NMOS transistor 345, 346 Inverter circuit

Claims (6)

First and second wirings formed in parallel;
A first signal input circuit for driving the first wiring by a driving signal having the same theory as the input clock signal;
A second signal input circuit for driving the second wiring based on an input clock signal;
An output circuit that synthesizes signals obtained through the first and second wirings and outputs an output clock signal; and
The second signal input circuit includes:
When the control signal indicating the active state of the input clock signal indicates the active state of the input clock signal, the second wiring is driven by a drive signal having the same theory as the input clock signal;
A clock driver circuit that drives the second wiring by the input clock signal and an inverted logic drive signal when the control signal indicates the inactive state of the input clock signal. The output circuit is
The control signal combines the drive signal obtained via the first wiring and the drive signal obtained via the second wiring when the input clock signal indicates an active state, and the input Output the output clock signal of the same theory as the clock signal,
The control signal is combined with the drive signal obtained through the first wiring and the inversion theory signal of the drive signal obtained through the second wiring when the input clock signal indicates an inactive state. The clock driver circuit according to claim 1, wherein an output clock signal having the same theory as the input clock signal is output. The first wiring is connected to one of a power supply and GND when the control signal indicates an inactive state of the input clock signal,
The clock driver circuit according to claim 1, wherein the second wiring is connected to the other of the power source and the GND. The second signal input circuit includes:
A first buffer for driving the second wiring by a drive signal having the same logic as the input clock signal;
A second buffer for driving the second wiring by the input clock signal and an inverted logic drive signal;
4. The clock according to claim 1, further comprising: a selection unit that selects one of the first buffer and the second buffer and connects the second buffer to the second wiring. 5. Driver circuit. The output circuit is
A third buffer that outputs a signal of the same theory as the drive signal obtained via the first wiring;
A fourth buffer that outputs a signal of the same theory as the drive signal obtained via the second wiring;
A fifth buffer for outputting a drive signal obtained through the second wiring and a signal of inversion theory;
An output selection circuit for selecting any one of the fourth and fifth buffers and connecting to the output of the third buffer;
An output terminal connected to the output of the output selection circuit and the output of the third buffer;
The output selection circuit selects the fourth buffer when the control signal indicates that the input clock signal indicates an active state, and when the control signal indicates that the input clock signal indicates an inactive state, 5. The clock driver circuit according to claim 1, wherein five buffers are selected.   It is parallel to the first and second wirings and is formed on the side opposite to the first wiring with respect to the second wiring, and one end and the other end of the first wiring are connected to each other. The clock driver circuit according to claim 1, further comprising a third wiring to be bypassed.

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