JPH08181669A - Clock disturbance suppression device - Google Patents

Abstract

PURPOSE: To obtain a clock disturbance suppression device in which disturbance is reduced without use of a disturbance countermeasure component such as an EMI filter or a shield case. CONSTITUTION: A clock generating circuit 11 generates a clock A to be fed to an IC 1 and provides an output of it. A pattern 13 for a clock A connects the clock generating circuit 11 and an input pin of the IC1. An inverting circuit 12 is used to invert the clock A and a clock B is outputted. A pattern 14 of the clock B is wired adjacently to the pattern 13 of the clock A. Through the constitution above, harmonic components at rise and fall of the clock are reduced by wiring the inverted clock pattern adjacently to the clock pattern in the clock disturbance suppression device.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital signal processing device having a clock.

[0002]

2. Description of the Related Art In recent years, digitalization of electric equipment has progressed. The clock used in the digital signal processing circuit is becoming faster, and it is necessary to take measures against the clock interference.

A conventional clock interference suppression device will be described below. FIG. 4 shows the configuration of a conventional clock interference suppression device.

In FIG. 4, reference numeral 41 denotes a clock generation circuit which generates and outputs a clock. Reference numeral 42 is a wiring path (hereinafter referred to as a pattern) which is a pattern between the clock generation circuit 41 and the IC 1 which uses the clock. As described above, conventionally, only the clock to be used is generated and the pattern is only for that clock. The interference suppressing means in the conventional example is to insert a resistor 44 or an EMI filter 43 into the clock pattern to blunt the waveform or to filter the harmonic components to reduce the interference components, or to shield the circuit block with a shield case to the outside. Was reducing the radiation of.

[0005]

However, the above-mentioned structure has a problem that relatively expensive parts such as an EMI filter and a shield case are required.

An object of the present invention is to provide a clock interference suppression device that solves the above conventional problems.

[0007]

In order to achieve this object, a clock disturbance suppressing device of the present invention generates a clock, a means for inverting the output of the clock generating means, and a clock for generating the clock. A wireway from the means,
It is characterized in that it has a wiring path adjacent to the wiring path from the inverting means.

[0008]

With this configuration, the harmonic components at the rising and falling edges of the clock can be reduced by the inverted harmonic components of the clock.

[0009]

【Example】

(Embodiment 1) First, a clock interference suppressing device in a first embodiment of the present invention will be described with reference to the drawings. FIG.
FIG. 1 is a block diagram of a clock interference suppression device in a first embodiment of the present invention.

In FIG. 1, reference numeral 11 is a clock generation circuit, which generates and outputs a clock A to be supplied to IC1. 1
Reference numeral 3 is a pattern of clock A and clock generation circuit 11 and I
It is a wiring path to the input pin of C1. Reference numeral 12 is an inverting circuit, which outputs a clock B which is the inverted clock A. 14
Is a pattern of the clock B, and is wired adjacent to the pattern of the clock A.

(Embodiment 2) Next, a clock interference suppressing device in a second embodiment of the present invention will be described with reference to the drawings. FIG. 2 is a block diagram of a clock interference suppression device according to a second embodiment of the present invention.

In FIG. 2, reference numeral 21 is a clock generation circuit which generates and outputs a clock A to be supplied to IC1, IC2 and IC3. Reference numeral 23 denotes a pattern of the clock A, which is a wiring path between the clock generation circuit and the input pins of IC1 and IC2.
Also, the IC 3 is pattern-connected from the clock A pattern via a jumper. Reference numeral 22 denotes an inverting circuit, which outputs a clock B which is the inverted clock A. Reference numeral 24 denotes a clock B pattern which is adjacent to the clock A pattern and is wired. The clock A pattern to the IC2 is made adjacent by passing between the jumpers. The clock A pattern to the IC1 is made adjacent by using a through hole of a multilayer printed board.

(Third Embodiment) Next, a clock interference suppressing device in a third embodiment of the present invention will be described with reference to the drawings. FIG. 3 is a block diagram of a clock interference suppression device in a third embodiment of the present invention.

In FIG. 3, reference numeral 31 is a clock generation circuit which generates and outputs a clock A to be supplied to ICn from IC1, IC2 and IC3. Reference numeral 33 is a pattern of the clock A and is a wiring path between the clock generation circuit and the input pins of IC1, IC2, IC3 to ICn. An inverting circuit 32 outputs a clock B which is the inverted clock A. A clock B pattern 34 is adjacent to the clock A pattern and is wired.

With these configurations, the clock interference suppressing device of the present invention can reduce the harmonic components at the rising and falling edges of the clock by wiring the inverted clock pattern adjacent to the clock pattern.

[0016]

As described above, the clock interference suppressing apparatus of the present invention reduces the harmonic components at the rising and falling edges of the clock, thereby making it possible to prevent interference components such as EMI filters and shield cases that have been conventionally required. It is possible to realize a clock interference suppression device that reduces interference without using a clock.

[Brief description of drawings]

FIG. 1 is a block diagram of a clock interference suppression device according to a first embodiment of the present invention.

FIG. 2 is a block diagram of a clock interference suppression device according to a second embodiment of the present invention.

FIG. 3 is a block diagram of a clock interference suppression device according to a third embodiment of the present invention.

FIG. 4 is a block diagram of a conventional clock interference suppression device.

[Explanation of symbols]

 11, 21, 31 Clock generation circuit 12, 22, 32 Inversion circuit 13, 23, 33 Clock A pattern 14, 24, 34 Clock B pattern

Claims (1)

[Claims] 1. A means for generating a clock, a means for inverting the output of the means for generating the clock, a wire path from the means for generating the clock, and a wire path from the means for inverting are adjacent. A clock interference suppression device having a wiring path.