JP4301404B2 - Output buffer circuit - Google Patents

Description

  The present invention relates to an output buffer circuit capable of realizing a low slew rate with a small size.

  For example, a low slew rate of 20 nsec or more is required in the I2C bus standard as a two-wire serial interface, and a low slew rate may be required in noise countermeasures other than the IC2 bus standard. Therefore, as an output buffer circuit that meets such a low slew rate requirement, a configuration shown in FIG. 4 has been proposed (see, for example, Patent Document 1). This output buffer circuit delays a signal input to the input terminal IN by capacitive elements C11 and C12 via inverters INV11 and INV12 as prebuffers, and drives the output PMOS transistor P11 and the output NMOS transistor N11 with the delayed signal. Then, the signal waveform obtained at the output terminal OUT is blunted.

Further, a configuration configured as shown in FIG. 5 has been proposed. This is because a PMOS transistor P13 is connected in series as a high impedance element to the output PMOS transistor P12 driven by the inverter INV13, and an NMOS transistor N13 is connected in series as a high impedance element to the output NMOS transistor N12 driven by the inverter INV14. A low slew rate is realized by making the stage high impedance.
JP-A-6-152374

  However, since the output buffer circuit shown in FIG. 4 requires a considerably large capacitance value for the capacitive elements C11 and C12, if this is realized on-chip, a large size is required and the chip area increases. There is a problem. In addition, when the capacitors C11 and C12 are externally configured, there is a problem that the convenience is lacking.

  On the other hand, in the output buffer circuit shown in FIG. 5, the driving current is restricted by the high impedance transistors P13 and N13, and the necessary driving force cannot be exhibited depending on the external load to be connected to the output terminal OUT. There's a problem.

  An object of the present invention is to provide an output buffer circuit capable of realizing a low slew rate without increasing the area and without reducing the output drive capability.

  An output buffer circuit according to a first aspect of the present invention includes a first transistor and a second transistor of a first conductivity type whose drain is commonly connected to an output terminal and whose source is commonly connected to a low-potential power source, and the source is the above-mentioned The second transistor opposite to the first conductivity type is connected to the gate of the first transistor, the drain is connected to the gate of the second transistor, and the gate is connected to the output terminal directly or via a resistor. A third transistor of the conductivity type; a fourth transistor of the first conductivity type having a drain connected to the gate of the second transistor, a source connected to the low-potential power supply, and a gate connected to the input terminal; And an inverter connected between the input terminal and the gate of the first transistor.

  According to a second aspect of the present invention, the output buffer circuit according to the first aspect further includes a capacitive element connected between the output terminal of the inverter and a low potential power source.

  According to a third aspect of the invention, in the output buffer circuit according to the first or second aspect, the first transistor has a smaller current capacity than the second transistor.

  An output buffer circuit according to a fourth aspect of the present invention is the output buffer circuit according to any one of the first to third aspects, wherein the first conductivity type and the second conductivity type of each transistor are replaced with each other, In addition, the low potential power source of the sources of the first, second and fourth transistors is replaced with a high potential power source. Here, the first conductivity type transistor in claims 1 to 4 is, for example, an NMOS transistor, and the second conductivity type transistor is a PMOS transistor. 5. The output buffer circuit according to claim 1, wherein the transistor is replaced with a bipolar transistor, the drain is a collector, the source is an emitter, and the gate is a base. Good. In this case, the first conductivity type transistor is an NPN transistor, and the second conductivity type transistor is a PNP transistor.

  According to a fifth aspect of the present invention, there is provided a first circuit comprising the output buffer circuit according to any one of the first to third aspects, and a second circuit comprising the output buffer circuit according to the fourth aspect. In addition, the input terminals of the first circuit and the second circuit are commonly connected, and the output terminals are commonly connected.

  According to the present invention, the load is driven by one transistor at the start of the transition of the input voltage, and the load is driven by two additional transistors after the transition, so that the load is high at the start of the transition. It is driven by impedance and is driven at low impedance after the transition, and the output drive capability does not decrease. In addition, since it is driven with a high impedance at the start of the transition as described above, it is possible to eliminate the capacitive element used in the output buffer circuit having the conventional configuration shown in FIG. No, the area can be reduced. From the above, a low slew rate can be realized without increasing the chip area and without reducing the output drive capability.

  In the present invention, the load is driven by one transistor at the start of the transition of the input voltage, and is driven by two additional transistors after the transition. Further, the gate voltage waveform of the transistor driven at the start of transition is blunted by the capacitive element. As described above, a low slew rate is realized without increasing the area of the capacitive element and without reducing the output drive capability. This will be described in detail below.

  1 is a circuit diagram showing a configuration of an output buffer circuit according to a first embodiment of the present invention. P1 and P2 are output PMOS transistors, and N1 and N2 are output NMOS transistors. The area (current capacity) has a relationship of P1 <P2 and N1 <N2. N3 is an NMOS transistor that controls the transistor P2 by the voltage at the output terminal OUT, P3 is a PMOS transistor that controls the transistor N2 by the voltage at the output terminal OUT, P4 is a PMOS transistor that inverts the signal at the input terminal IN, and N4 is the input terminal IN. NMOS transistors, INV1 and INV2 are inverters as prebuffers, and C1 to C4 are capacitive elements.

  When the voltage at the input terminal IN changes from “L” (low level) to “H” (high level), the output node NG1 of the inverter INV2 becomes “L” and the transistor N1 is cut off, and the transistor N4 becomes conductive and its drain node NG2 becomes “L”, and the transistor N2 is also cut off. On the other hand, the output node PG1 of the inverter INV1 becomes “L”. At this time, the fall of the voltage of the node PG1 is slowed by the conduction resistance of the output transistor (not shown) of the inverter INV1 and the capacitance of the capacitive element C1. Therefore, the transistor P1 becomes conductive, but its rise is slow. At this time, immediately after the input terminal IN transitions from “L” to “H”, the voltage at the output terminal OUT is “L”, so that the transistor N3 is cut off. Accordingly, only the transistor P1 is turned on at the beginning when the input terminal IN changes from “L” to “H”. However, when the voltage at the output terminal OUT rises slowly and exceeds the threshold value of the transistor N3, the transistor N3 is turned on. Since the transistor P2 is turned on, the transistor P2 is turned on, and the voltage at the output terminal OUT settles to a steady state of “H”. Thus, when the voltage at the input terminal IN changes from “L” to “H”, the transistor P1 is first turned on slowly, and then the transistor P2 is also turned on to increase the driving capability.

  Next, when the voltage at the input terminal IN transitions from “H” to “L”, the output node PG1 of the inverter INV1 becomes “H”, the transistor P1 is cut off, and the transistor P4 becomes conductive and its drain node. PG2 becomes “H” and also shuts off the transistor P2. On the other hand, the output node NG1 of the inverter INV2 becomes “H”. At this time, the rise of the voltage of the node NG1 is slowed by the conduction resistance of the output transistor of the inverter INV2 and the capacitance of the capacitor C2. Therefore, although the transistor N1 becomes conductive, the fall of its drain voltage is slow. At this time, immediately after the input terminal IN transitions from “H” to “L”, the voltage of the output terminal OUT is “H”, so that the transistor P3 is cut off. Therefore, only the transistor N1 is turned on at the beginning when the input terminal IN changes from “H” to “L”. However, when the voltage at the output terminal OUT drops slowly below the threshold of the transistor P3 due to the conduction, the transistor P3 is turned off. Since the transistor N2 is turned on, the transistor N2 is turned on and the voltage at the output terminal OUT is settled to a steady state of “L”. Thus, when the voltage at the input terminal IN changes from “H” to “L”, the transistor N1 is first turned on slowly, and then the transistor N2 is also turned on to increase the driving force.

  As described above, in the output buffer circuit according to the first embodiment, the load CL is driven with an output impedance higher than that of only the transistor P1 or N1 from immediately after the transition of the voltage of the output terminal OUT to the middle of the transition. Alternatively, the falling waveform can be dulled to reduce the slew rate. At this time, the capacitance values of the capacitive elements C1 and C2 can be reduced and the area thereof can also be reduced. Further, since the gate capacitance is naturally formed at the gate of the transistor and there is a wiring capacitance or the like, the capacitative elements C1 and C2 that are intentionally formed can be deleted depending on a desired slew rate. Further, when the voltage at the output terminal OUT reaches the threshold value of the transistor N3 or P3, the transistor P2 or N2 is driven. As a result, the transistors P1 and P2 or N1 and N2 are conducted, and the load CL is driven with a low output impedance. Even when the load CL increases, a sufficient current can be sourced or sinked, and a large driving force can be exhibited.

  When the capacitive elements C1 and C2 are deleted and the capacitive elements C3 and C4 are connected between the nodes PG2 and NG2 and the ground terminal GND, the gate voltage waveforms of the transistors P2 and N2 may be blunted. Since this is possible, the slew rate can be similarly reduced. If all of the capacitive elements C1, C2, C3, and C4 are used, the slew rate can be further reduced.

  Further, in the output buffer circuit shown in FIG. 1, the waveform of both the rising and falling of the voltage of the output terminal OUT becomes dull. However, when only the falling waveform is dulled, it is configured only on the sink side ( (The INV1, C1, P1, P2, N3, and P4 are deleted.) The PMOS transistor can be replaced with a PNP bipolar transistor having a collector, an emitter, and a base, and the NMOS transistor can be replaced with an NPN bipolar transistor.

  Here, the open drain type output buffer circuit will be compared with the prior art. FIG. 2A is a diagram showing an I2C-compatible output buffer circuit configured only on the sink side of the conventional output buffer circuit of FIG. 4, and LS1 shifts the input voltage from 1.3V to 3.3V for output. A level shifter, R1 is a pull-up resistor, and CL1 is a load. A transistor N11 having a size equivalent to a 4 mA buffer was used.

  FIG. 2B is a diagram showing an I2C-compatible output buffer circuit configured only on the sink side of the output buffer circuit of FIG. 1, and LS2 is a level shifter that shifts the input voltage from 1.3V to 3.3V and outputs it. , R2 is a pull-up resistor, R3 is a protective resistor, and CL2 is a load. A transistor N1 having a size corresponding to a 1 mA buffer was used, and a transistor N2 having a size corresponding to a 3 mA buffer was used.

  2A and 2B, R1 = R2 = 1.3 KΩ, C12 = C2, CL1 = CL2 = 50 pF, VDD1 = 1.3V, and VDD2 = 3.3V. When these output buffer circuits are used in the I2C bus fast mode, the output voltage fall time must be 25 nsec or more as a bus specification. FIG. 3 shows an output waveform by SPICE simulation. Vin is a voltage waveform of the input terminal IN, Vout1 is an output voltage waveform of the output buffer circuit of FIG. 2A, and Vout2 is an output voltage waveform of the output buffer circuit of FIG. 2B.

  As can be seen from FIG. 3, the output buffer circuit of FIG. 2 (b) has a more gradual fall than the output buffer circuit of FIG. 2 (a). When attention is paid to the “L” level of the waveform of the voltage Vout2, it can be seen that the output buffer circuit of FIG. The measured value of the fall time is 15.06 nsec in the output buffer circuit of FIG. 2A and 29.78 nsec in the output buffer circuit of FIG. 2B, and the latter is larger. As described above, even when the capacitance elements C12 and C2 have the same capacitance value, the output buffer circuit of FIG. 2B can satisfy the specification of the I2C bus in the fall time. On the other hand, in order to satisfy the specification of the I2C bus in the output buffer circuit of FIG. 2A, the capacitance value of the capacitive element C12 must be set to a larger value, resulting in an increase in area.

It is a circuit diagram of the output buffer circuit of Example 1 of this invention. 4A is a circuit diagram of an open drain type output buffer circuit configured only on the sink side of the conventional output buffer circuit of FIG. 4, and FIG. 5B is configured only on the sink side of the output buffer circuit of Embodiment 1 of the present invention. FIG. 3 is a circuit diagram of an open drain type output buffer circuit. It is a wave form diagram by simulation of the input voltage and output voltage of the output buffer circuit of Drawing 2 (a) and (b). It is a circuit diagram of a conventional output buffer circuit. It is a circuit diagram of another conventional output buffer circuit.

Explanation of symbols

P1-P4, P11-P13: PMOS transistors N1-N4, N11-N13: NMOS transistors INV1, INV2, INV11-INV14: Inverters C1-C4, C11, C12: Capacitance elements CL, CL1, CL2: Loads R1-R3: Resistors LS1, LS2: Level shifter

Claims (5)

A first transistor and a second transistor of the first conductivity type, each having a drain commonly connected to the output terminal and a source commonly connected to a low-potential power source;
Opposite to the first conductivity type, the source is connected to the gate of the first transistor, the drain is connected to the gate of the second transistor, and the gate is connected to the output terminal directly or via a resistor. A third transistor of the second conductivity type;
A fourth transistor of the first conductivity type having a drain connected to the gate of the second transistor, a source connected to the low potential power supply, and a gate connected to an input terminal;
An inverter connected between the input terminal and the gate of the first transistor;
An output buffer circuit comprising: The output buffer circuit of claim 1, further comprising:
An output buffer circuit comprising a capacitive element connected between an output terminal of the inverter and a low potential power source. The output buffer circuit according to claim 1 or 2,
The output buffer circuit according to claim 1, wherein the first transistor has a smaller current capacity than the second transistor. The output buffer circuit according to any one of claims 1 to 3,
The first conductivity type and the second conductivity type of each transistor are replaced with each other, and the low potential power source of the sources of the first, second, and fourth transistors is replaced with a high potential power source. Output buffer circuit. A first circuit comprising the output buffer circuit according to any one of claims 1 to 3;
A second circuit comprising the output buffer circuit according to claim 4,
An output buffer circuit, wherein the input terminals of the first circuit and the second circuit are connected in common and the output terminals are connected in common.

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