US20130278285A1 - Minimum-spacing circuit design and layout for pica - Google Patents
Minimum-spacing circuit design and layout for pica Download PDFInfo
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- US20130278285A1 US20130278285A1 US13/452,092 US201213452092A US2013278285A1 US 20130278285 A1 US20130278285 A1 US 20130278285A1 US 201213452092 A US201213452092 A US 201213452092A US 2013278285 A1 US2013278285 A1 US 2013278285A1
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- 241001482237 Pica Species 0.000 title abstract 2
- 238000013461 design Methods 0.000 title description 12
- 238000012360 testing method Methods 0.000 claims abstract description 69
- 230000003287 optical effect Effects 0.000 claims abstract description 16
- 238000004519 manufacturing process Methods 0.000 claims abstract description 12
- 238000005516 engineering process Methods 0.000 claims abstract description 11
- 230000001960 triggered effect Effects 0.000 claims abstract description 10
- 239000004065 semiconductor Substances 0.000 claims description 21
- 230000005669 field effect Effects 0.000 claims description 6
- 230000000737 periodic effect Effects 0.000 claims 2
- 238000005286 illumination Methods 0.000 claims 1
- ADHFMENDOUEJRK-UHFFFAOYSA-N 9-[(4-fluorophenyl)methyl]-n-hydroxypyrido[3,4-b]indole-3-carboxamide Chemical compound C1=NC(C(=O)NO)=CC(C2=CC=CC=C22)=C1N2CC1=CC=C(F)C=C1 ADHFMENDOUEJRK-UHFFFAOYSA-N 0.000 abstract 1
- 238000003384 imaging method Methods 0.000 description 19
- 238000010586 diagram Methods 0.000 description 7
- 101150018075 sel-2 gene Proteins 0.000 description 6
- 238000000034 method Methods 0.000 description 5
- 238000004458 analytical method Methods 0.000 description 4
- 239000000758 substrate Substances 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 239000007795 chemical reaction product Substances 0.000 description 2
- 230000006835 compression Effects 0.000 description 2
- 238000007906 compression Methods 0.000 description 2
- -1 e.g. Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005259 measurement Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 239000000047 product Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000013590 bulk material Substances 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000011156 evaluation Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 239000013067 intermediate product Substances 0.000 description 1
- 238000013507 mapping Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012634 optical imaging Methods 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 238000009877 rendering Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 230000001629 suppression Effects 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N17/00—Diagnosis, testing or measuring for television systems or their details
- H04N17/002—Diagnosis, testing or measuring for television systems or their details for television cameras
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01J—MEASUREMENT OF INTENSITY, VELOCITY, SPECTRAL CONTENT, POLARISATION, PHASE OR PULSE CHARACTERISTICS OF INFRARED, VISIBLE OR ULTRAVIOLET LIGHT; COLORIMETRY; RADIATION PYROMETRY
- G01J1/00—Photometry, e.g. photographic exposure meter
- G01J1/42—Photometry, e.g. photographic exposure meter using electric radiation detectors
- G01J1/44—Electric circuits
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01J—MEASUREMENT OF INTENSITY, VELOCITY, SPECTRAL CONTENT, POLARISATION, PHASE OR PULSE CHARACTERISTICS OF INFRARED, VISIBLE OR ULTRAVIOLET LIGHT; COLORIMETRY; RADIATION PYROMETRY
- G01J11/00—Measuring the characteristics of individual optical pulses or of optical pulse trains
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/26—Testing of individual semiconductor devices
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
- H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/14—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using opto-electronic devices, i.e. light-emitting and photoelectric devices electrically- or optically-coupled
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01J—MEASUREMENT OF INTENSITY, VELOCITY, SPECTRAL CONTENT, POLARISATION, PHASE OR PULSE CHARACTERISTICS OF INFRARED, VISIBLE OR ULTRAVIOLET LIGHT; COLORIMETRY; RADIATION PYROMETRY
- G01J1/00—Photometry, e.g. photographic exposure meter
- G01J1/42—Photometry, e.g. photographic exposure meter using electric radiation detectors
- G01J2001/4238—Pulsed light
Abstract
PICA test circuits are shown that include a first transistor and a second transistor laid out drain-to-drain, such that a gap between respective drain regions of the first and second transistors has a minimum size allowed by a given fabrication technology; a first NOR gate having an output connected to the drain region of the first transistor and accepting a first select signal and an input signal; and a second NOR gate having an output connected to the drain region of the second transistor and accepting a second select signal and the input signal. One of said NOR gates biases the connected transistor's drain region, according to the select signal of said NOR gate, to inhibit an optical emission when said connected transistor is triggered.
Description
- This invention was made with Government support under Contract No.: FA8650-11-C-7105 (National Security Agency). The government has certain rights in this invention.
- 1. Technical Field
- The present invention relates to test circuit design, and more particularly to creating test circuits for high-resolution picosecond imaging circuit analysis.
- 2. Description of the Related Art
- Picosecond imaging circuit analysis (PICA) is a technique used for timing measurement and failure analysis of integrated circuits. PICA exploits a side-effect of field effect transistors (FETs) whereby a FET emits a burst of light when its drain region is at a high voltage and its gate transitions from a low voltage to a high voltage. This allows for optical imaging of the back side of an integrated chip circuit to, e.g., locate failed transistors and perform other measurements.
- In PICA systems, higher resolutions are desirable to ensure good imaging that can test the limits of circuit design features. To test the resolution of PICA systems, test circuits are created which are designed to produce optical emissions that are close together. Previous attempts to create such test circuits involved compressing circuit layouts parallel and perpendicular to FET gates. Compression parallel to the transistor gate is limited by either polysilicon gate later end-to-end spacing or n-channel metal-oxide-semiconductor to p-channel metal-oxide-semiconductor spacing. Compression parallel to the transistor gate is limited by gate pitch. Exemplary spacings according to such prior art technologies include 284 nm in the parallel spacing and 220 nm in the perpendicular spacing. As such, previous attempts to create PICA test circuits have been limited in their ability to test PICA resolution.
- A circuit includes a first semiconductor device and a second semiconductor device which emit light during operation, laid out such that light-emitting regions of the respective semiconductor devices are proximal to one another with a gap between the respective light-emitting regions including a target resolution size; and a logic circuit configured to accept an input signal and at least one select signal and to bias light-emitting regions of at least one of the respective semiconductor to inhibit an optical emission when said at least one semiconductor device is triggered.
- A circuit includes a first transistor and a second transistor laid out drain-to-drain, such that a gap between respective drain regions of the first and second transistors has a minimum size allowed by a given fabrication technology; a first NOR gate having an output connected to the drain region of the first transistor and accepting a first select signal and an input signal; and a second NOR gate having an output connected to the drain region of the second transistor and accepting a second select signal and the input signal, wherein one of said NOR gates biases the connected transistor's drain region, according to the select signal of said NOR gate, to inhibit an optical emission when said connected transistor is triggered.
- A test circuit includes a plurality of test cells arranged in a line. Each test cell includes a first transistor and a second transistor laid out drain-to-drain, such that a gap between respective drain regions of the first and second transistors has a minimum size allowed by a given fabrication technology; a first NOR gate having an output connected to the drain region of the first transistor and accepting a first select signal and an input signal provided by the output of a previous test cell; and a second NOR gate having an output connected to the drain region of the second transistor and accepting a second select signal and the input signal. One of said NOR gates in each test cell biases the connected transistor's drain region, according to the select signal of said NOR gate, to inhibit an optical emission when said connected transistor is triggered.
- These and other features and advantages will become apparent from the following detailed description of illustrative embodiments thereof, which is to be read in connection with the accompanying drawings.
- The disclosure will provide details in the following description of preferred embodiments with reference to the following figures wherein:
-
FIG. 1 is a diagram of a field effect transistor according to the present principles; -
FIG. 2 is a diagram of an exemplary PICA imaging test circuit according to the present principles; -
FIG. 3 is a diagram showing an exemplary physical layout of a PICA imaging test circuit on a chip according to the present principles; -
FIG. 4 is a diagram showing an exemplary PICA testing apparatus according to the present principles; -
FIG. 5 is a series of signal graphs showing signal values over time at various points within a PICA imaging test circuit; -
FIG. 6 is a series of signal graphs showing signal values over time at various points within a PICA imaging test circuit; -
FIG. 7 is a diagram of a PICA imaging test chip that includes multiple PICA imaging test circuits according to the present principles; and -
FIG. 8 is a block/flow diagram showing a method for testing an imaging device according the present principles. - Picosecond Imaging for Circuit Analysis (PICA) is a powerful optical tool that permits probing time-resolved emission signals collected from transistors inside a circuit, allowing for non-invasive testing of circuit operation. By neglecting the arrival time of photons and constructing a spatial histogram of the measured light, one can create a “PICA image” of the emission intensity. Bright spots indicate individual transistors or sub-circuit units composed by several transistors. By selecting a portion of the image, one can create a histogram of the photon arrival time and, therefore, a waveform in time of the emission activity from that location.
- Alternatively, 2D images of the photons at specific times can be created and then a video may be constructed by combining frames. It should be noted that more than one bright spot is usually present in such a PICA image, and the emission may correspond to gates that are not switching, or which are switched with a certain frequency.
- Testing the resolution of a PICA camera means determining whether circuit features having a given separation can be distinguished. For example, a PICA camera that can distinguish between adjacent features 100 nm apart has a resolution of at least 100 nm. However, the realities of modern circuit fabrication technologies place practical limitations on how small circuit features can be made and how close together they can be placed.
- Field effect transistors (FETs) emit light from their drain regions during operation. One partial solution to forming a high-resolution test circuit is to form two FETs that share a single gate and source node, but have separate drain nodes. This may be used to achieve drain-to-drain spacing that has diffusion edge-to-edge spacing of about 70 nm in a 32 nm fabrication technology. 70 nm is near the resolution limit of PICA tools, and is therefore an effective design for testing the resolution of such tools. As such, the present principles provide test circuits that have minimally spaced transistors sharing a common gate and source node. NOR gates are used to drive separate signals on the drains of the two transistors. Emission from switching gates may be modulated in time, while non-switching gates either do not have an associated emission, or their emissions are not modulated in time.
- There are several applications which benefit from quickly distinguishing which bright spot or spots correspond to a switching gate and which do not. One example relates to debugging electrical patterns of a circuit to quickly identify which gate is exercised by the specific pattern, pattern tuning, and pattern debugging. This also helps in applications such as logic state mapping. Another exemplary application relates to security and detecting undesired chip modifications, for example by identifying a set of switching gates and their position in the layout and comparing the identified set to an exemplar.
- Being able to detect which gate is switching among many non-switching identical gates helps in circuit probing and diagnostics when limited information about schematic, layout, and circuit behavior is available to a tool operator. Another use for PICA imaging includes assisting a tool operator in better defining and optimizing the region of interest for extracting time resolved waveforms or for further probing with single-point detectors. By readily identifying the regions that correspond to switching gates, one can more easily define the border of the region of interest.
- It is to be understood that the present invention will be described in terms of a given illustrative architecture having a wafer; however, other architectures, structures, substrate materials and process features and steps may be varied within the scope of the present invention.
- It will also be understood that when an element such as a layer, region or substrate is referred to as being “on” or “over” another element, it can be directly on the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” or “directly over” another element, there are no intervening elements present. It will also be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present.
- A design for an integrated circuit chip of photovoltaic device may be created in a graphical computer programming language, and stored in a computer storage medium (such as a disk, tape, physical hard drive, or virtual hard drive such as in a storage access network). If the designer does not fabricate chips or the photolithographic masks used to fabricate chips, the designer may transmit the resulting design by physical means (e.g., by providing a copy of the storage medium storing the design) or electronically (e.g., through the Internet) to such entities, directly or indirectly. The stored design is then converted into the appropriate format (e.g., GDSII) for the fabrication of photolithographic masks, which typically include multiple copies of the chip design in question that are to be formed on a wafer. The photolithographic masks are utilized to define areas of the wafer (and/or the layers thereon) to be etched or otherwise processed.
- Methods as described herein may be used in the fabrication of integrated circuit chips. The resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (that is, as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case the chip is mounted in a single chip package (such as a plastic carrier, with leads that are affixed to a motherboard or other higher level carrier) or in a multichip package (such as a ceramic carrier that has either or both surface interconnections or buried interconnections). In any case the chip is then integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either (a) an intermediate product, such as a motherboard, or (b) an end product. The end product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products having a display, a keyboard or other input device, and a central processor.
- Referring now to the drawings in which like numerals represent the same or similar elements and initially to
FIG. 1 , an exemplary embodiment of a FET according to the present principles is shown. Although only FETs are shown herein, it is contemplated that any semiconductor device can be used in accordance with the present principles if said device produces optical emissions during operation, Asubstrate layer 102 is formed from any suitable bulk material including, e.g., silicon. Adielectric layer 104 on thesubstrate layer 102 is formed from any suitable dielectric material such as, e.g., silicon dioxide. An active layer is formed on thedielectric layer 104 including asource region 106, achannel region 108, and adrain region 110, and may be formed from, e.g., doped silicon. The doping thechannel region 108 may be of the same kind as thesource region 106 and drainregion 110, or may be of the opposite polarity. - An insulating
layer 111 is disposed on thesource 106,channel 108, and drain 110 and may be formed from, e.g., any suitable dielectric. The insulatinglayer 111 has asource contact 112 and adrain contact 114 that run through thelayer 111, providing electrical access to thesource region 106 and drainregion 110. Agate electrode 116 runs through the insulatinglayer 111 and is separated from thechannel region 108 by agate dielectric 118. It should be stressed that the depicted FET design is just one that may be used according to the present principles. There are a wide variety of FET designs in the art, and it is contemplated that any appropriate FET can be used. - A FET such as that shown in
FIG. 1 will produce an optical signal when a voltage applied to thegate electrode 116 rises above a threshold voltage and voltage at thedrain 110 is high, before starting to fall. Thus, if the voltage at thedrain 110 is kept biased at a low voltage (e.g., ground), an FET will not emit light when thegate 116 is triggered. This permits selective suppression of FET emissions by using a control signal to bias theFET drain 110 as desired. - Referring now to
FIG. 2 , atest buffer circuit 200 is shown. The circuit includes twoFETs gate electrode 116 by acommon input signal 206, where said input signal may be provided as the output signal of aprevious buffer circuit 200. TheFETs respective source terminals 106 to acommon ground 216. Thedrain terminals 110 of theFETs gates first node 222 and asecond node 224. The NORgates common input 206 and a respective select input, either sel-1 208 or se1-2 210. The outputs of both NORgates gate 218, which provides its output toinverter 220. - The combination of a NOR
gate 202 andFET 212 as shown essentially forms a three-input NOR gate. The select signals sel-1 208 and sel-2 210 are provided externally as opposing waveforms, such that sel-1 208 will have a high value when sel-2 210 has a low value. The select signals 208 and 210 may therefore be switched at regular intervals according to a desired test pattern. For example, theselect signals input signal 206, to allow a desired number of optical pulses to be emitted from eachtransistor select signals - If select signal se1-1 208 is low (i.e., logical “0”), then the
oscillating input signal 206 will cause the logical value of the signal atnode 222 to oscillate with a value opposite that of theinput signal 206. As a result, thefirst transistor 212 emits flashes of light at thedrain 110, while thesecond transistor 214 does not. This is because select signal sel-2 210 causes thedrain 110 oftransistor 214 to be biased to a logical 0 by the output of the second NORgate 204, such that triggering thesecond transistor 214 does not cause a voltage change. Similarly, if the second select signal sel-2 210 is low, thennode 224 will oscillate with a value opposite that of theinput signal 206 andnode 222 will remain fixed at logical 0. In such a case, thesecond transistor 214 emits a flash of light while thefirst transistor 212 remains quiescent. - The output of each transistor-NOR pair, represented by
nodes gate 218 and inverted atinverter 220. This makes the overall function of thecircuit 200 that of a buffer, where the output ofinverter 220 is the same as theinput signal 206. - It should be noted that the NOR
gates input 206, the twoselect signals biased outputs - Using the
above circuit 200, theselect signals drain 110 oftransistor 212 to that oftransistor 214. By using acommon gate input 116 the physical spacing betweentransistors - Referring now to
FIG. 3 , a top-down view of thecircuit 200 is shown as said circuit could be laid out on a chip. Component interconnections are omitted for clarity. As can be seen, thetransistors transistors spacing 302 between them. Thisspacing 302 represents the physical quantity that the present principles provide for testing PICA camera resolutions. An exemplary spacing has been shown of about 70 nm using 32 nm technology, but because thespacing 302 betweentransistors drains 110 ofgates transistors - Referring now to
FIG. 4 , a diagram of an exemplary testing setup is shown. While it is contemplated that the present principles may employed in any imaging system to test maximum resolution, a PICA system is shown in particular. APICA imager 402 scans atest circuit 404 to detect light emissions from FETs. ThePICA imager 402 may take a picture of the entire test circuit at once or it may capture information in a pixel-at-a-time fashion. ThePICA imager 402 then stores imaging information instorage 406, which may be any appropriate form of storage, including a disk, tape, physical hard drive, or virtual hard drive such as in a storage access network. ThePICA imager 402 may be self-controlled, or may be controlled by atest generator 408. Thetest generator 408 provides pattern data to test circuit according to a predetermined test sequence. For example, thetest generator 408 may controlselect signals transistors PICA imager 402 ortest circuit 404 moves with respect to the other for scanning and imaging purposes. - When the
PICA imager 402 scans thetest circuit 404, it builds a series of images instorage 406. These images are then analyzed to determine whether thePICA imager 402 has met resolution requirements. In particular, it is considered whether thePICA imager 402 is able to distinguish between the light emissions from afirst transistor 212 and asecond transistor 214. In some cases, thePICA imager 402 may not be sensitive to detect the output of a single transistor. In that case, thecircuit 200 may be repeated and chained, with the output ofinverter 220 forming theinput 206 of thenext circuit 200. By lining thecircuits 200 vertically, a strip of active transistors can be created and more easily detected byPICA imager 402. It should also be noted that the exposure length ofPICA imager 402 may be orders of magnitude longer than the clock cycle of theinput signal 206. As such, theselect signals input signal 206. - If a single pixel of recorded light information covers the emissions from both transistors, then the
PICA imager 402 has a resolution lower than that needed to fully capture the emission information from thetest circuit 404. However, if thePICA imager 402 can reliably distinguish between the emissions from the neighboringtransistors imager 402 meets or exceeds the resolution range tested by thetest circuit 404. - Referring now to
FIG. 5 , logical values for signals at a series of points in the circuit ofFIG. 2 , assuming a logical “0” on the firstselect signal 208 and a logical “1” on the secondselect signal 210. The horizontal axis on each graph represents time, while the vertical graph represents the logical value of the signal. It is specifically contemplated that the value may, in turn, represent the voltage of the signal, but the renderings have been kept at a qualitative level for clarity. Theinput signal 206 oscillates between a logical 1 and a logical 0. The input signal is illustratively described as being a digital square wave, though it is contemplated that any appropriate input signal may be employed. With sel-1 208 being fixed at logical 0, the first NORgate 202 outputs tonode 222 an inversion of theinput signal 206. With sel-2 210 being fixed at logical 1, the second NORgate 204 outputs a fixed logical 0. Because FET optical emissions occur if thegate electrode 116 is triggered while voltage is high atdrain 110, and because a low-voltage at 224 biases the drain of thesecond transistor 214, the second transistor will not emit light while se1-2 210 is set to logical 1. In contrast, thefirst transistor 212 will flash in time with theinput signal 206. - Referring now to
FIG. 6 , logical values for signals at a series of points in the circuit ofFIG. 2 , assuming a logical “1” on the firstselect signal 208 and a logical “0” on the secondselect signal 210—inputs that are reversed from those shown inFIG. 5 . Again, the horizontal axis on each graph represents time, while the vertical graph represents the logical value of the signal. Theinput signal 206 continues to oscillate between a logical 1 and a logical 0. With sel-1 208 being fixed at logical 1, the first NORgate 202 outputs a fixed logical 0 tonode 222. With sel-2 210 being fixed at logical 0, the second NORgate 204 outputs an inversion of theinput signal 206 tonode 224. Thus, because a low-voltage at 222 biases the drain of thefirst transistor 212, the first transistor will not emit light while sel-1 208 is set to logical 1. In contrast, thesecond transistor 214 will flash in time with theinput signal 206. - Thus the
select signals transistors PICA imager 402 to detect. - Referring now to
FIG. 7 , an exemplary layout for atesting chip 700 is shown. Thechip 700 includesmultiple banks individual test circuits 200. Thetest circuits 200 are aligned such that an entire row of transistors will activate at once. This increases the amount of light output along the bank, such that the resolution of aPICA imager 402 can be more easily tested. Thebanks input generator 702 andselect generator 704. These signals may be generated on-chip or they may be provided off-chip by, e.g.,test generator 408. Thebanks last test circuit 200 inbank 706 produces the input for thefirst test circuit 200 inbank 708. - The circuit layout described in
FIGS. 2 and 3 has additional applicability in minimizing device mismatch. Device mismatch is a condition where transistor characteristics (e.g., threshold voltage) vary across a single chip. Wafer manufacturing processes may cause undesirable variations in transistor characteristics across the wafer such that, for example, components on the left side of the wafer might have a higher threshold voltage than components on the right side of the wafer. The present principles may therefore be applied to a differential pair of transistors where having matched characteristics is desirable. The present principles allow for the placement of transistors as close together as possible to avoid the negative effects of device mismatch. This may have particular applicability where precise timing is important, because a difference in threshold voltage may cause a FET to trigger sooner or later than intended. - Referring now to
FIG. 8 , a method for testing an imaging device according to the present principles is shown.Block 802 forms a set of semiconductor devices such that their light-emitting regions are next to one another. This could be in the layout shown inFIG. 7 , or could take any other appropriate layout.Block 804 forms logic circuits to control the semiconductor devices. Again, these could be the NORgates Block 806 provides aninput signal 206 to activate the semiconductor devices, and block 808 providesselect signals Block 810 then changes the select signals to change the pattern of light emission.Block 812 determines whether an imaging device, such asPICA camera 402 can discern between the patterns of light emission. If so, the imaging device has sufficient resolution of at least the spacing between the semiconductor devices. - Having described preferred embodiments of a minimum-spacing circuit design and layout for PICA (which are intended to be illustrative and not limiting), it is noted that modifications and variations can be made by persons skilled in the art in light of the above teachings. It is therefore to be understood that changes may be made in the particular embodiments disclosed which are within the scope of the invention as outlined by the appended claims. Having thus described aspects of the invention, with the details and particularity required by the patent laws, what is claimed and desired protected by Letters Patent is set forth in the appended claims.
Claims (21)
1. A circuit, comprising:
a first semiconductor device and a second semiconductor device which emit light during operation, laid out such that light-emitting regions of the respective semiconductor devices are proximal to one another with a gap between the respective light-emitting regions including a target resolution size; and
a logic circuit configured to accept an input signal and at least one select signal and to bias light-emitting regions of at least one of the respective semiconductor to inhibit an optical emission when said at least one semiconductor device is triggered.
2. The circuit of claim 1 , wherein the first and second semiconductor devices are field effect transistors.
3. The circuit of claim 1 , wherein the logic circuit comprises two NOR gates, each accepting respective select signals that alternate logical values.
4. The circuit of claim 1 , wherein the at least one select signal comprises two select signals having opposite logical values.
5. The circuit of claim 1 , wherein the semiconductor devices are field effect transistors.
6. The circuit of claim 5 , wherein the logic circuit is configured to bias a drain region of a field effect transistor at a low voltage to inhibit light emission.
7. A circuit, comprising:
a first transistor and a second transistor laid out drain-to-drain, such that a gap between respective drain regions of the first and second transistors has a minimum size allowed by a given fabrication technology;
a first NOR gate having an output connected to the drain region of the first transistor and accepting a first select signal and an input signal; and
a second NOR gate having an output connected to the drain region of the second transistor and accepting a second select signal and the input signal,
wherein one of said NOR gates biases the connected transistor's drain region, according to the select signal of said NOR gate, to inhibit an optical emission when said connected transistor is triggered.
8. The circuit of claim 7 , further comprising:
a third NOR gate accepting the outputs of the first and second NOR gates; and
an inverter accepting the output of the third NOR gate.
9. The circuit of claim 8 , wherein the inverter has an output that conforms to the input signal.
10. The circuit of claim 7 , wherein the first select signal and the second select signal have opposite logical values.
11. The circuit of claim 7 , wherein the first select signal and the second select signal alternate logical values.
12. The circuit of claim 11 , wherein the first select signal and the second select signal alternate logical values at a periodic interval.
13. The circuit of claim 7 , wherein the input signal is a square wave.
14. The circuit of claim 7 , wherein the gap between the respective drain regions has a size of about 70 nm or less.
15. A test circuit, comprising:
a plurality of test cells arranged in a line, each test cell comprising:
a first transistor and a second transistor laid out drain-to-drain, such that a gap between respective drain regions of the first and second transistors has a minimum size allowed by a given fabrication technology;
a first NOR gate having an output connected to the drain region of the first transistor and accepting a first select signal and an input signal provided by the output of a previous test cell; and
a second NOR gate having an output connected to the drain region of the second transistor and accepting a second select signal and the input signal,
wherein one of said NOR gates in each test cell biases the connected transistor's drain region, according to the select signal of said NOR gate, to inhibit an optical emission when said connected transistor is triggered.
16. The test circuit of claim 15 , wherein adjacent test cells are oriented with respect to one another such that the first transistors of the test cells form a first line and the second transistors of the test cells form a second line.
17. The test circuit of claim 16 , wherein the first and second select signals are chosen to provide a line of illumination for optical testing.
18. The test circuit of claim 15 , wherein each test cell further comprises:
a third NOR gate accepting the outputs of the first and second NOR gates; and
an inverter accepting the output of the third NOR gate and producing an output for the test cell.
19. The test circuit of claim 18 , wherein the inverter has an output that conforms to the input signal.
20. The test circuit of claim 15 , wherein the first select signal and the second select signal have opposite logical values.
21. The test circuit of claim 20 , wherein the first select signal and the second select signal alternate logical values at a periodic interval.
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US13/452,092 US20130278285A1 (en) | 2012-04-20 | 2012-04-20 | Minimum-spacing circuit design and layout for pica |
US13/463,166 US9229044B2 (en) | 2012-04-20 | 2012-05-03 | Minimum-spacing circuit design and layout for PICA |
US14/012,668 US9081049B2 (en) | 2012-04-20 | 2013-08-28 | Minimum-spacing circuit design and layout for PICA |
US14/939,788 US9930325B2 (en) | 2012-04-20 | 2015-11-12 | Minimum-spacing circuit design and layout for PICA |
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US13/452,092 US20130278285A1 (en) | 2012-04-20 | 2012-04-20 | Minimum-spacing circuit design and layout for pica |
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US13/463,166 Continuation US9229044B2 (en) | 2012-04-20 | 2012-05-03 | Minimum-spacing circuit design and layout for PICA |
US14/012,668 Continuation US9081049B2 (en) | 2012-04-20 | 2013-08-28 | Minimum-spacing circuit design and layout for PICA |
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US13/452,092 Abandoned US20130278285A1 (en) | 2012-04-20 | 2012-04-20 | Minimum-spacing circuit design and layout for pica |
US13/463,166 Expired - Fee Related US9229044B2 (en) | 2012-04-20 | 2012-05-03 | Minimum-spacing circuit design and layout for PICA |
US14/012,668 Expired - Fee Related US9081049B2 (en) | 2012-04-20 | 2013-08-28 | Minimum-spacing circuit design and layout for PICA |
US14/939,788 Active US9930325B2 (en) | 2012-04-20 | 2015-11-12 | Minimum-spacing circuit design and layout for PICA |
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US13/463,166 Expired - Fee Related US9229044B2 (en) | 2012-04-20 | 2012-05-03 | Minimum-spacing circuit design and layout for PICA |
US14/012,668 Expired - Fee Related US9081049B2 (en) | 2012-04-20 | 2013-08-28 | Minimum-spacing circuit design and layout for PICA |
US14/939,788 Active US9930325B2 (en) | 2012-04-20 | 2015-11-12 | Minimum-spacing circuit design and layout for PICA |
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US20130278285A1 (en) * | 2012-04-20 | 2013-10-24 | International Business Machines Corporation | Minimum-spacing circuit design and layout for pica |
US9496854B2 (en) * | 2015-03-10 | 2016-11-15 | International Business Machines Corporation | High-speed latch circuits by selective use of large gate pitch |
US9749567B2 (en) | 2015-11-29 | 2017-08-29 | United Microelectronics Corp. | Operating method of image sensor |
TWI738098B (en) * | 2019-10-28 | 2021-09-01 | 阿丹電子企業股份有限公司 | Optical volume-measuring device |
TWI789595B (en) * | 2020-05-29 | 2023-01-11 | 阿丹電子企業股份有限公司 | Volume measuring apparatus having different types of trigger |
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Also Published As
Publication number | Publication date |
---|---|
US20140176183A1 (en) | 2014-06-26 |
US9930325B2 (en) | 2018-03-27 |
US9081049B2 (en) | 2015-07-14 |
US9229044B2 (en) | 2016-01-05 |
US20160150227A1 (en) | 2016-05-26 |
US20130280828A1 (en) | 2013-10-24 |
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