KR100886679B1 - Data processing system and method in wireless broadband internet - Google Patents

Abstract

The present invention relates to a data processing system and method thereof in a WiBro network, and receives a channel power value and a TDD signal of each channel to generate a new TDD signal correcting a difference with a position of an actual power. And a data processor for distinguishing a downlink from a downlink, storing the corresponding power value in a memory, and outputting a frame end signal of the TDD signal in a predetermined time unit, and ending the frame output from the data processor in a predetermined time unit. The controller may include a controller configured to read and process a corresponding power value stored in the memory every time a signal is received.

Description

DATA PROCESSING SYSTEM AND METHOD IN WIRELESS BROADBAND INTERNET}

1 is a diagram showing a difference between a general FDD signal and a TDD signal.

2 is a diagram illustrating an example of a conventional data processing system.

3 shows another example of a data processing system according to the related art.

4 is a diagram illustrating an example of a conventional RF power detection process.

5 is a diagram showing the configuration of a data processing system in a WiBro network according to the present invention.

FIG. 6 is a diagram illustrating a configuration of the FPGA of FIG. 5. FIG.

7 is a diagram illustrating an example of a TDD signal for matching an actual power position in a downlink period according to the present invention.

8 is a diagram illustrating a data processing procedure in a WiBro network according to the present invention.

9 is a diagram illustrating an example in which a CPU running time according to the present invention is compared with a conventional CPU running time.

Explanation of symbols on the main parts of the drawings

10: CPU 20: ADC

30: FPGA 40: Clock Board

50: DPRAM

The present invention relates to a data processing system and method thereof in a WiBro network.

In general, time-sharing systems, such as WiBro's Time Division Duplex (TDD) system, must perform their tasks within a limited time. In such a TDD system, RF power detection places a heavy load on the CPU during Tx / Rx or downlink / uplink. Therefore, it is necessary to reduce the load on the CPU and perform ADC for RF power detection.

In other words, since a large amount of time must be allocated in order to detect RF power conventionally, the CPU load rate is increased. Since the CPU load rate on the control board causes problems in other functions of the board, it is important to lower the CPU load rate for the normal and stable functioning of the system.

1 illustrates a difference between a general FDD signal and a TDD signal.

As shown in FIG. 1, the FDD signal and the TDD signal centered on the time axis, the conventional communication system method is an uplink unlike the TDD signal because the frequency division duplex (FDD) method is used to divide frequency. ) And the downlink section did not need to be divided.

That is, the interval is divided so that RF power is detected without distinguishing whether the current output is an uplink section or a downlink section. Currently, a representative example of the FDD scheme is divided into 4Ghz / 6Ghz satellite communications.

However, time division systems, such as TDD systems, must perform their tasks within a limited time. In the RF power detection method of such a TDD system, since the uplink and downlink sections are divided by time, the CPU must continuously detect the TDD signal to distinguish the current state. In addition, since the processor must be driven to calculate the output value at that time, the CPU load ratio increases.

2 is a diagram illustrating an example of a data processing system according to the related art, and FIG. 3 is a diagram illustrating another example of a data processing system according to the prior art.

First, as shown in Figure 2, the first conventional scheme is designed around the CPU (1). The CPU 1 directly clocks the ADC Device 2 and receives data, and the CPLD 3 receives the TDD signal from the clock board 4 and delays it to the CPU 1. When the Delayed TDD signal is provided, the CPU 1 receives the Delayed TDD signal to process data by distinguishing an uplink / downlink section.

On the other hand, in the second conventional method as shown in Figure 3, by using an interrupt to reduce the CPU load in the method of Figure 2, the CPU 5 directly clocks the ADC Device 6 and receives data, The CPLD 7 receives the TDD signal from the clock board 8 and gives the delayed TDD signal to the CPU 5.

In particular, when the CPLD 7 transmits the downlink / uplink interrupt DN_int / UP_int to the CPU 5, it generates an interrupt in the uplink / downlink, so that the CPU 7 only generates an interrupt. RF power is detected. However, frequent interrupts (twice every 5ms) affect other CPU functional blocks.

4 is a diagram illustrating an example of a conventional RF power detection process.

As shown in FIG. 4, when the RF power detecting algorithm is executed (S1), the register of the TDD signal is checked (S2) to determine whether it is currently uplink or downlink. (S3).

As a result, if it is uplink, it is again checked whether it is downlink (S4). If it is downlink, the downlink ADC output value is detected (S5), and then the average of downlink ADC output value is calculated (S6). DBm is displayed (S7).

On the other hand, in the case of the downlink in the step S3 of checking whether the current uplink (Downlink) or downlink (Downlink), it is checked whether the ALC function is ON (S8).

As a result, if the ALC function is not ON, it is checked whether it is uplink (S9). If it is uplink, the uplink ADC output value is detected (S10), and then the average of the uplink ADC output value is calculated (S11). The dBm is displayed by comparing the average value table (S12).

However, if the ALC function is ON, it is determined whether the uplink is an uplink (S13), and if it is an uplink, the uplink ADC output value is detected (S14), and then the average of the uplink ADC output value is calculated (S15). Atten control (S16) is performed by comparing the tables.

As described above, in case of the ADC detection, all processors depend on the function of the CPU. When the ADC value is detected, the running time of the CPU is long and there is no idle time of the CPU. Not only does the CPU's load rate increase, which prevents the CPU from functioning normally, but when the load rate rises for a long time, the function for the ADC also becomes impossible to measure accurately and cannot guarantee the accuracy of the functions of the other blocks.

In addition, in the conventional method, one of the methods for reducing the CPU load rate has a problem in that the accuracy of the measured ADC value cannot be obtained unless both the uplink section and the downlink section are detected.

Accordingly, an object of the present invention is to solve the above problems, while detecting the ADC value of several channels continuously while ensuring the accuracy of the detected value while at the same time reducing the CPU load rate for the stable function of the CPU A data processing system in a network and a method thereof are provided.

According to an aspect of a data processing system in a WiBro network according to the present invention for achieving the above object, by receiving the channel power value and the TDD signal of each channel to a new TDD signal corrected for the difference with the position of the actual power A data processor for generating an uplink and a downlink, storing the corresponding power values in a memory, and outputting a frame end signal of the TDD signal in units of predetermined time; The controller may include a controller configured to read and process a corresponding power value stored in the memory whenever the frame end signal output in units of time is received.

In particular, the memory uses DPRAM (Dual Ported RAM) that can read the memory value at the same time as the operation in the data processing unit.

The data processor generates an uplink and an uplink that receives a channel power value of each channel through an input pin, and generates a new TDD signal correcting a difference between a TDD signal input from a clock board and an actual power position. An uplink power measurement for identifying a downlink and a channel power value input from the input unit and a new TDD signal input from the TDD signal processor to determine whether the current signal is valid as an uplink signal And an uplink power calculator for calculating uplink power when the current signal is valid as an uplink signal by the uplink power measuring unit, a channel power value input from the input unit, and a new TDD input from the TDD signal processor. A downlink power measurement unit that receives a signal and checks whether the current signal is valid as a downlink signal; A downlink power calculator for calculating downlink power when the current signal is valid as a downlink signal by the downlink power measuring unit, and an uplink power value calculated by the uplink power calculator or the downlink power calculator And a memory control unit for receiving the downlink power value calculated in the memory and storing the received downlink power value in the memory, and a synchronization signal generator for receiving a TDD signal from the clock board and transmitting a synchronization signal generated once at a predetermined time interval to the controller.

The controller may process data with a previous frame value based on the synchronization signal generated from the synchronization signal generator.

On the other hand, according to an aspect of the data processing method in the WiBro network according to the present invention for achieving the above object, the process of checking the interrupt signal generated by a predetermined time unit, and when the interrupt signal is generated and input the memory And extracting the data necessary for the operation, and displaying the corresponding power value by comparing the data extracted from the memory with a previously stored data table.

In addition, when the automatic level control (ALC) function is ON after the display of the corresponding power value, the method may further include performing attenuation control.

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, detailed descriptions of preferred embodiments of the present invention will be described with reference to the accompanying drawings. It should be noted that reference numerals and like elements among the drawings are denoted by the same reference numerals and symbols as much as possible even though they are shown in different drawings. In the following description of the present invention, if it is determined that a detailed description of a related known function or configuration may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted.

5 is a diagram illustrating a configuration of a data processing system in a WiBro network according to the present invention.

As shown in FIG. 5, in the present invention, the CPU 10 is connected to the FPGA 30, and by performing the existing CPU role in the FPGA 30, a CPU-centric design to a CPU- and FPGA-oriented design It is designed to reduce the load on the CPU.

That is, the FPGA 30 directly clocks the ADC device 20, receives data from the ADC device 20, and transfers the received data to the CPU 10 through the DPRAM 50. ) Receives the TDD signal from the clock board 40 and gives the CPU 10 one frame signal.

6 is a diagram illustrating a configuration of the FPGA of FIG. 5, and FIG. 7 is a diagram illustrating an example of a TDD signal for matching an actual power position in a downlink period according to the present invention.

As shown, the FPGA 30 of the present invention includes an FPGA input unit 31, a TDD signal processing unit 32, an uplink power measuring unit 33, an uplink power calculating unit 34, and a downlink. And a power measuring section 35, a downlink power calculating section 36, a memory control section 37 and a synchronization signal generating section 38.

The FPGA input unit 31 receives the channel power value of each channel converted into analog to digital through the ADC through the input pin, and receives the input channel power value from the uplink power measuring unit 33 and the downlink power measuring unit 35. ).

The TDD signal processor 32 distinguishes the uplink and the downlink by making the TDD signal input from the clock board into a new delayed TDD signal corrected for the difference from the position of the actual power. . For example, as illustrated in FIG. 7, a delayed TDD signal for adjusting the actual power position in the downlink period is generated.

The uplink power measurement unit 33 receives the channel power value input from the FPGA input unit 31 and the delayed TDD signal input from the TDD signal processor 32 to check whether the current signal is valid as an uplink signal. .

The uplink power calculating unit 34 calculates the uplink power (effective value average) when the uplink power measuring unit 33 confirms that the current signal is valid as the uplink signal.

The downlink power measurement unit 35 receives the channel power value input from the FPGA input unit 31 and the delayed TDD signal input from the TDD signal processor 32 to check whether the current signal is valid as the downlink signal. .

The downlink power calculator 36 calculates the downlink power (effective value average) when the downlink power measurement unit 35 determines that the current signal is valid as the downlink signal.

The memory controller 37 receives the uplink power value calculated by the uplink power calculator 34 and the downlink power value calculated by the downlink power calculator 36 and stores the uplink power value in the DPRAM memory 50.

That is, the downlink value and the uplink value are calculated by logic inside the FPGA and written to a specific register inside the FPGA, or, if necessary, written to the DPRAM memory 50 using DPRAM.

Here, since the DPRAM is a memory structure that can be read and written in both directions, the CPU can read the memory value at the same time as the FPGA writes. At this time, if read / write occurs at the same address at the same time, an error may occur, so logic is implemented to use different addresses.

In particular, the data value to be read by the CPU 10 may selectively take a required value among many channels of the ADC 20, or may use a required partial value by reading all data.

The synchronization signal generator 38 receives the TDD signal from the clock board and transfers a signal generated once every 5 ms to the CPU 10. That is, the CPU 10 is notified that one frame (5ms / 1 frame) is finished at 5ms intervals.

Accordingly, the CPU 10 performs a function with a value before 1 Frame based on the synchronization signal generated from the synchronization signal generator 38. At this time, the processing time of the data after the CPU 10 reads the data is affected by the speed of the DPRAM, but since the speed is fast, almost all data can be processed without delay.

In particular, the TDD signal is not changed 5 ms in 1 frame, but since the ratio of the uplink section and the downlink section can be changed according to the service provider's request, the internal logic for correcting the difference from the actual power value is based on the TDD signal. Changes to the TDD should be possible.

In other words, in order to maintain the accuracy of the power measured value of the uplink section and the downlink section, it must be done. This can also be realized through Detecting in S / W or through an internal timer. In terms of accuracy and accuracy, making changes using logic is more efficient.

In particular, the Auto Level Control (ALC) function has a detecting value and adjusts the attenuation in the board to protect the internal circuits. Not only should the load be light, but the value to be detected must be accurate.

8 is a diagram illustrating a data processing process in a WiBro network according to the present invention.

As shown in FIG. 8, the CPU of the present invention first checks whether 5 ms interrupt is generated (S10), and when 5 ms interrupt is generated, necessary data is extracted from DPRAM (S20).

Subsequently, after comparing the data extracted from the DPRAM to the data table, dBm is displayed (S30). Then, the ALC function is turned on (S40). When the ALC function is ON, the Atten control (S50) is performed. Done.

As described above, in the present invention, since the FPGA processes the part to be processed in the CPU, the CPU receives only the data processed in the FPGA and works to reduce the CPU load rate.

9 is a diagram illustrating an example of comparing a CPU running time according to the present invention with a conventional CPU driving time.

As shown in FIG. 9, in the conventional scheme, the uplink / downlink interval can be distinguished only by detecting the entire period of the TDD signal. In other words, the CPU will continue to work without idle time because the CPU run time must be TDD-wide.

On the other hand, in the present invention, the CPU reads and processes data from the memory in accordance with a 5ms sync signal, so that the CPU's driving time is in a state in which other tasks can be performed in standby time except processing time.

As described above, it can be seen that the driving time of the CPU is much improved as compared with the conventional method.

In the above, specific preferred embodiments of the present invention have been illustrated and described. However, the present invention is not limited to the above-described embodiments, and various modifications can be made by any person having ordinary skill in the art without departing from the scope of the present invention attached to the scope of the claims. will be.

According to the present invention, since the CPU receives only the data processed by the FPGA and works, firstly, it reduces the dependency of the CPU and divides the work of the CPU into the FPGA instead of the conventional method, thereby reducing the CPU load rate by that much. Can be.

Second, one board of the new method can process three TDD signals (Uplink, Downlink), thereby reducing the production cost of the system because three existing boards can be reduced to one.

Third, since the functions of three existing boards can be used as one, the system can reduce unnecessary space.

Fourth, since the load on the CPU is less, the same CPU can perform more functions.

Claims (6)

In a data processing system in a WiBro network, An input unit to receive a channel power value of each channel; A TDD signal processor configured to receive a TDD signal from a clock board and distinguish uplink and downlink; An uplink power measurement unit receiving a channel power value input from the input unit and a TDD signal input from the TDD signal processing unit and checking whether a current signal is valid as an uplink signal; An uplink power calculator for calculating uplink power when the current signal is valid as an uplink signal by the uplink power measuring unit; A downlink power measurement unit receiving a channel power value input from the input unit and a TDD signal input from a TDD signal processor to determine whether a current signal is valid as a downlink signal; A downlink power calculator configured to calculate downlink power when the current signal is valid as a downlink signal by the downlink power measurement unit; A memory controller configured to receive an uplink power value calculated by the uplink power calculator or a downlink power value calculated by the downlink power calculator, and store the received downlink power value in a memory; And a synchronization signal generator for receiving a TDD signal from the clock board and generating a synchronization signal at predetermined time intervals. A data processor comprising a; And A controller which reads a corresponding power value stored in the memory only when receiving a synchronization signal output from the data processor in a predetermined time unit; Data processing system in a WiBro network comprising a. The method of claim 1, The memory, And a dual ported RAM (DPRAM) capable of reading a memory value from the controller at the same time as the writing by the data processor. delete The method of claim 1, The control unit, The data processing system in the WiBro network, characterized in that for processing data with a value before 1Frame based on the synchronization signal output from the data processing unit. delete delete

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