KR101469674B1 - Method for preventing malfunction of processor - Google Patents

Method for preventing malfunction of processor Download PDF

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Publication number
KR101469674B1
KR101469674B1 KR1020130125376A KR20130125376A KR101469674B1 KR 101469674 B1 KR101469674 B1 KR 101469674B1 KR 1020130125376 A KR1020130125376 A KR 1020130125376A KR 20130125376 A KR20130125376 A KR 20130125376A KR 101469674 B1 KR101469674 B1 KR 101469674B1
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South Korea
Prior art keywords
processor
error count
watchdog
malfunction
time
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KR1020130125376A
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Korean (ko)
Inventor
이철주
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주식회사 현대케피코
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Publication of KR101469674B1 publication Critical patent/KR101469674B1/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/14—Time supervision arrangements, e.g. real time clock
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/004—Error avoidance
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/30—Monitoring
    • G06F11/3003—Monitoring arrangements specially adapted to the computing system or computing system component being monitored
    • G06F11/3024—Monitoring arrangements specially adapted to the computing system or computing system component being monitored where the computing system component is a central processing unit [CPU]

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Quality & Reliability (AREA)
  • Computing Systems (AREA)
  • Mathematical Physics (AREA)
  • Debugging And Monitoring (AREA)

Abstract

Disclosed is a method for preventing malfunctions of a processor by variably changing the watch-dog time of a watch-dog timer. The present invention prevents the malfunctions of the processor by variably changing the watch-dog time based on the attribute information of a task assigned to the processor and error count information received in the watch-dog timer.

Description

[0001] The present invention relates to a method for preventing malfunction of a processor,

The present invention relates to a method of preventing a malfunction of a processor, and more particularly, to a method of preventing malfunction of a processor by variably changing a watch-dog time of a watch-dog timer.

A watch-dog device performs a function of monitoring each processor that processes an assigned task and returning normally using a reset signal when the processor is in an erroneous or infinite loop state.

Figure 1 shows the construction of a watchdog system according to the prior art. As shown in FIG. 1, the conventional watch-and-dock system is implemented using a counter, and includes a counter 10 for periodically generating a reset signal to the outside, and a clock signal for enabling the counter 10 to operate And a processor 12 for processing the assigned task.

The processor 12 transmits a watch-dog signal that prevents the counter 10 from being reset when it is operating normally.

The oscillation unit 11 includes an oscillation circuit, a crystal and an oscillator and provides a clock signal to the counter 10. The counter 10 receives a clock signal of the oscillation unit 11 and generates a periodic pulse waveform And outputs a reset signal to the processor 12 by selecting a cycle suitable for monitoring the processor 12 from the output of the counter 10. [ Therefore, even when the processor 12 is in a malfunction or an infinite loop state, it can return normally.

That is, when the processor 12 is normally operating, the processor 12 outputs a watch-dog signal to the counter 10 to prevent the counter 10 from periodically resetting itself, 10) performs a normal operation while clearing the timer according to the watch-dog signal.

On the other hand, when the processor 12 is in a malfunction or an infinite loop state, the processor 12 can not generate a watch-dog signal for clearing the counter 10, The clock signal is received from the oscillation unit 11 to increase the output, and by resetting the processor 12 by generating a reset signal, as shown in 'section A' of FIG. 2, The operation causes the processor 12 to return from a malfunction or an infinite loop state to a normal operation state.

On the other hand, according to the above-described conventional technique, by resetting the watch-dog timer within a fixed time, the reset of the processor is prevented. In this case, as an exceptional case, when a specific task having a high priority is allocated to the processor, the watch-dog timer is reset within a predetermined time (response waiting time for resetting the watch-dog timer, hereinafter referred to as " Can not be prevented. Also, if the watchdog time is set to the maximum value for such an exception, a quick processor error may cause the system to fail due to a failure to reset at the appropriate time.

SUMMARY OF THE INVENTION The present invention has been made in order to solve the problems of the related art described above, and it is an object of the present invention to variably change a watch-dog time based on attribute information of a task assigned to a processor, and error count information received from a watch- And to provide a method for preventing a malfunction of the apparatus.

The objects of the present invention are not limited to the above-mentioned objects, and other objects not mentioned can be clearly understood by those skilled in the art from the following description.

According to another aspect of the present invention, there is provided a method for preventing a malfunction of a processor, the method comprising: detecting a malfunction of the processor and a watchdog timer; Receiving and monitoring an error count signal from the error counter; And variably changing a watchdog time (WDT) of the watchdog timer according to whether the processor increases or decreases the error count signal.

In a preferred embodiment, the error count signal is incremented by the number of times that the watchdog timer does not receive a watchdog signal for timer reset from the processor within the watchdog time set for a particular execution period, and the watchdog timer The number of times of receiving the watchdog signal for resetting the timer from the processor within the watchdog time set in the specific execution cycle can be reduced by the number of times.

In one embodiment, the step of varying the watchdog time may include increasing the watchdog time in proportion to the increment of the error count included in the error count signal.

In another embodiment, the step of varying the watchdog time may include decreasing the watchdog time in proportion to the decrease in the error count included in the error count signal.

In still another embodiment, the step of variably changing the watchdog time may include increasing or decreasing the watchdog time according to whether the error count is included in the error count signal, May be determined to be a predetermined value according to attribute information of a task assigned to the processor which causes the error count increase / decrease.

According to another aspect of the present invention, there is provided a method for preventing a malfunction of a processor, the method comprising the steps of: detecting a malfunction of the processor and a watchdog timer; Receiving an error count signal from the watchdog timer to determine whether the error count has increased; And increasing the watchdog time (WDT) of the watchdog timer in proportion to the increment of the error count if the error count is increased as a result of the determination.

On the other hand, a method for preventing a malfunction of a processor according to the present invention includes: in the second execution period after the first execution period, the processor receives an error count signal from the watchdog timer to determine whether the error count has decreased; And determining if the error count is greater than zero if the error count is less than zero, if the error count is greater than zero, and if the error count is greater than zero, comparing the watchdog time of the watchdog timer with the decrease in the error count The method further comprising:

As described above, according to the present invention, it is possible to improve the error detection capability of the watch-dog timer and to cope with an exceptional situation that may occur in the processor, so that the processor can stably operate System environment can be implemented.

1 is an exemplary view showing a configuration of a watch-dog system according to the prior art;
FIG. 2 is a timing chart showing the flow of each signal in FIG. 1; FIG.
3 is a block diagram showing a general configuration of a watch-dog system to which a malfunction prevention method of a processor according to an embodiment of the present invention is applied.
4 is a flowchart showing a method of preventing malfunction of a processor according to an embodiment of the present invention.
5 is an exemplary diagram illustrating a correlation between a watch-dog error count and an increased or decreased watch-dog time (response latency) in an embodiment of the present invention;

BRIEF DESCRIPTION OF THE DRAWINGS The advantages and features of the present invention, and the manner of achieving them, will be apparent from and elucidated with reference to the embodiments described hereinafter in conjunction with the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Is provided to fully convey the scope of the invention to those skilled in the art, and the invention is only defined by the scope of the claims. It is to be understood that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. In the present specification, the singular form includes plural forms unless otherwise specified in the specification.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the drawings, the same reference numerals are used to designate the same or similar components throughout the drawings. In the following description of the present invention, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear.

3 is a block diagram illustrating a general configuration of a watch-dog system to which a method for preventing malfunction of a processor according to an embodiment of the present invention is applied.

Referring to FIG. 3, the watch-dog system includes a processor 10 for assigning and processing a specific task, a processor 10 for detecting malfunction of the processor 10, And a watch-dog timer 20.

The watch-dog timer 20 may be embedded in and operate as a component of the processor 10 or may be configured to form a separate circuit from the processor 10 and to control the processor 10 through data communication, Signals can be transmitted and received.

The present invention relates to an improved method for preventing a malfunction of a processor in a watch-to-talk system as described above, wherein not only when a watch-and-dog timer is embedded in the processor but also when a separate circuit is configured, .

For the sake of convenience of explanation, the following description will be made on the assumption that the watch-dog timer 20 constitutes a separate circuit from the outside of the processor 10.

Hereinafter, a method for preventing malfunction of the processor according to the embodiment of the present invention will be described in detail with reference to FIGS. 4 and 5. FIG.

FIG. 4 is a flowchart showing a method of preventing a malfunction of a processor according to an embodiment of the present invention, and FIG. 5 is a flowchart showing a correlation between a watch-poison error count and an increased or decreased watch- Fig.

As shown in FIG. 4, the processor 10 performs an assigned specific task (S10) and receives and monitors an error count signal from the watchdog timer 20 during task execution.

For example, the processor 10 processes a number of tasks at the same time. Some tasks require a large amount of processing time, some require a relatively small processing time, or some require varying processing time depending on the situation.

If the processor 10 receives a watch-dog signal (reset request signal) from the watchdog timer 20 within a preset time (response wait time for timer reset, hereinafter referred to as watchdog time) A situation that can not be sent may occur.

As a result, the error count increases in the watchdog timer 20, and the error count increases by the number of times this occurs.

On the other hand, when the watchdog timer 20 receives a watchdog signal for resetting the timer from the processor 10 within the watchdog time set in a specific period, the error count decreases by the number of times.

The processor 10 continuously or periodically monitors an error count of the watchdog timer 20, which is increased or decreased through the above-described process, and checks whether the error count is increased (S20).

If it is determined that the error count has increased, the processor 10 increases the watch dog time of the watchdog timer 20 according to the increment (S30).

In one embodiment, the processor 10 may increase the watch dog time in proportion to the increment of the error count. FIG. 5 shows that the watch dog time is increased by a constant ratio or a certain size according to the increment of the error count. While the error count increases from 1 to 5 in Fig. 5, the watch dog time (response wait time) is shown to increase from t1 to t5.

The increment of the watchdog time may be variably determined to a predetermined value according to the attribute information of the task assigned to the processor 10 which causes the error count increase / decrease.

For example, it is assumed that the task (Task 1) currently being processed by the processor 10 has the attribute information of P1 according to the processing difficulty or the like. At this time, attribute information such as P1 may be preset and stored in the internal memory of the processor 10 or the like according to the type of the task.

If it is confirmed that the error count of the watchdog timer 20 is increased during the processing of the task 1 by the processor 10, the watchdog time is increased by the predetermined value of the watchdog time increment according to the P1 attribute information. At this time, the watchdog time increase amount may be proportional to the predetermined number of watchdog time increments multiplied by the increased error count number.

By variably increasing the watchdog time through the above-described process, it is possible to prevent the processor from being reset in the course of processing a specific task in the processor. Accordingly, when the task processing in an exceptional situation is terminated, the processor 10 can normally transmit the watchdog signal to the watchdog timer 20 within the watchdog time set in the execution cycle.

In this case, the error count in the position docking timer 20 is reduced by the number of times of normal operation.

On the other hand, if the increased watchdog time is continuously maintained even in a normal operating environment, the processing time for a malfunction of the processor may be delayed. To prevent this, the processor 10 monitors the error count periodically or periodically to check whether the error count has decreased (S40).

As a result of checking, if the error count is decreased, it is checked whether the current error count has a value exceeding 0 (S50). If the current error count exceeds 0, the processor 10, according to the decrease, The watchdog timer 20 decrements the watchdog timer (S60).

The determination of the watchdog time reduction can be applied in the same way as determining the increment described above. Therefore, a detailed description thereof will be omitted.

Thereafter, the processor 10 transmits the watchdog signal for the watchdog timer 20 reset to the watchdog timer 20 in the current execution cycle (S70) within the increased or decreased watchdog time.

It will be understood by those skilled in the art that the present invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. It is therefore to be understood that the above-described embodiments are illustrative in all aspects and not restrictive. The scope of the present invention is defined by the appended claims rather than the detailed description, and all changes or modifications derived from the scope of the claims and their equivalents should be construed as being included within the scope of the present invention.

Claims (7)

A method for preventing malfunction of a processor in a system including a processor and a watchdog timer for monitoring a malfunction of the processor,
The processor receiving and monitoring an error count signal from the watchdog timer; And
And varying a watchdog time (WDT) of the watchdog timer according to whether the processor increases or decreases the error count signal,
Wherein the error count signal comprises:
When the watchdog timer does not receive a watchdog signal for timer reset from the processor within a watchdog time set in a specific execution cycle,
When the watchdog timer receives a watchdog signal for timer reset from the processor within a watchdog time set in a specific execution cycle,
A method for preventing a malfunction of a processor.
delete 2. The method of claim 1, wherein varying the watchdog time comprises:
And increasing the watchdog time in proportion to the increment when the error count included in the error count signal is increased
A method for preventing a malfunction of a processor.
2. The method of claim 1, wherein varying the watchdog time comprises:
And decreasing the watchdog time in proportion to the decrease when the error count included in the error count signal is decreased
A method for preventing a malfunction of a processor.
2. The method of claim 1, wherein varying the watchdog time comprises:
And increasing or decreasing the watchdog time according to whether the error count is included in the error count signal,
The increment / decrement of the watch dog time is determined to be a predetermined value according to attribute information of a task allocated to the processor which causes the error count increase / decrease
A method for preventing a malfunction of a processor. A method for preventing malfunction of a processor in a system including a processor and a watchdog timer for monitoring a malfunction of the processor,
The processor receiving an error count signal from the watchdog timer in a first execution period to determine whether the error count has increased; And
As a result of the determination, if the error count is increased, increasing the WatchDog Time (WDT) of the watchdog timer in proportion to the increment of the error count
Wherein the processor is operable to detect a malfunction of the processor.
The method according to claim 6,
Receiving, in a second execution period after the first execution period, the processor an error count signal from the watchdog timer to determine whether the error count has decreased; And
If it is determined that the error count is less than 0, if the error count is less than 0, the watchdog timer of the watchdog timer is decreased in proportion to the decrease of the error count, Step
Further comprising the steps of:
KR1020130125376A 2013-10-21 2013-10-21 Method for preventing malfunction of processor KR101469674B1 (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20190014387A (en) * 2017-08-02 2019-02-12 현대오트론 주식회사 Mcu operation monitoring system and controlling method thereof

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09244923A (en) * 1996-03-11 1997-09-19 Hitachi Ltd Abnormality monitoring device using watchdog timer
KR100664842B1 (en) * 2005-11-28 2007-01-04 엘지노텔 주식회사 Watchdog reset control circuit for programmable logic array
KR20070040186A (en) * 2005-10-11 2007-04-16 엘지노텔 주식회사 An apparatus for generating a watch dog signal in a communication system
KR20100007608A (en) * 2008-07-14 2010-01-22 콘티넨탈 오토모티브 시스템 주식회사 System and method for preventing malfunction of electronic control unit

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09244923A (en) * 1996-03-11 1997-09-19 Hitachi Ltd Abnormality monitoring device using watchdog timer
KR20070040186A (en) * 2005-10-11 2007-04-16 엘지노텔 주식회사 An apparatus for generating a watch dog signal in a communication system
KR100664842B1 (en) * 2005-11-28 2007-01-04 엘지노텔 주식회사 Watchdog reset control circuit for programmable logic array
KR20100007608A (en) * 2008-07-14 2010-01-22 콘티넨탈 오토모티브 시스템 주식회사 System and method for preventing malfunction of electronic control unit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20190014387A (en) * 2017-08-02 2019-02-12 현대오트론 주식회사 Mcu operation monitoring system and controlling method thereof
KR101988723B1 (en) * 2017-08-02 2019-06-12 현대오트론 주식회사 Mcu operation monitoring system and controlling method thereof

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