KR100878916B1 - Solder bump - Google Patents

Solder bump Download PDF

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Publication number
KR100878916B1
KR100878916B1 KR1020070094273A KR20070094273A KR100878916B1 KR 100878916 B1 KR100878916 B1 KR 100878916B1 KR 1020070094273 A KR1020070094273 A KR 1020070094273A KR 20070094273 A KR20070094273 A KR 20070094273A KR 100878916 B1 KR100878916 B1 KR 100878916B1
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KR
South Korea
Prior art keywords
copper post
layer
tin
silver
solder
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KR1020070094273A
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Korean (ko)
Inventor
김호진
서수정
김장현
박인수
이용호
나성훈
백용호
최영식
Original Assignee
삼성전기주식회사
성균관대학교산학협력단
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Priority to KR1020070094273A priority Critical patent/KR100878916B1/en
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    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K35/00—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting
    • B23K35/22—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting characterised by the composition or nature of the material
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K35/00—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting
    • B23K35/02—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting characterised by mechanical features, e.g. shape
    • B23K35/0222—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting characterised by mechanical features, e.g. shape for use in soldering, brazing
    • B23K35/0244—Powders, particles or spheres; Preforms made therefrom
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B32—LAYERED PRODUCTS
    • B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B15/00—Layered products comprising a layer of metal
    • B32B15/01—Layered products comprising a layer of metal all layers being exclusively metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/36—Material effects
    • H01L2924/365—Metallurgical effects
    • H01L2924/3651—Formation of intermetallics

Abstract

A solder bump is provided to prevent mechanical strength of the solder bump from decreasing by sequentially forming a copper post, silver plating layers and tin plating layers, thereby suppressing the production of Ag3Sn that is an intermetallic compound produced on an interface of the copper post and a solder. A solder bump(30) comprises a copper post(2), silver plating layers(4,8), and tin plating layers(6,10). The copper post is formed on a metal layer(12) forming an electronic component through the electroplating process. The silver plating layers and tin plating layers are sequentially formed on the copper post. The metal layer means a circuit pattern formed on a printed circuit board or a wafer level package. The solder bump further comprises a gold plating layer(14) formed between the metal layer and the copper post.

Description

솔더 범프{Solder Bump}Solder Bump

본 발명은 솔더 범프에 관한 것으로, 특히 구리 포스트 위에 은도금층 및 주석도금층을 순차적으로 형성하여 구리 포스트와 주석도금층의 직접적인 접합을 방지하고 시효 효과로 주석과 금속간 화합물을 형성할 수 있는 구리의 농도를 낮춤으로써 크랙 전파 경로를 길게 하여 접합 신뢰성을 향상시킬 수 있는 솔더 범프에 관한 것이다.The present invention relates to solder bumps, in particular, to form a silver plating layer and a tin plating layer sequentially on the copper post to prevent direct bonding of the copper post and the tin plated layer and the concentration of copper which can form an intermetallic compound with tin by the aging effect The present invention relates to a solder bump that can improve the bonding reliability by lengthening the crack propagation path by lowering.

최근 들어 전자제품의 소형화와 전기적 고성능화를 위하여 접속 길이를 짧게 할 수 있는 플립칩 기술이 크게 대두되고 있다.In recent years, flip chip technology that can shorten the connection length for the miniaturization of the electronic products and high electrical performance has emerged.

이때, 플립칩의 전기적인 접속을 위해 납(Pb)/63주석(Sn), 주석(Sn)-은(Ag), 주석(Sn)-구리(Cu), 주석(Sn)-은(Ag)-구리(Cu)(-비스무스(Bi)) 등의 솔더 범프를 이용한 방법이 많이 이용되고 있다.At this time, lead (Pb) / 63 tin (Sn), tin (Sn)-silver (Ag), tin (Sn)-copper (Cu), tin (Sn)-silver (Ag) for the electrical connection of the flip chip Many methods using solder bumps, such as copper (Cu) and bismuth (Bi), are used.

이러한, 솔더 범프는 주로 납/63주석 솔더가 많이 사용되었으나 환경적인 문제에 따른 납의 규제 방침에 따라 현재 거의 사용되지 않는다.These solder bumps are mainly used for lead / 63 tin solder, but are currently rarely used in accordance with the regulation of lead due to environmental problems.

이에 따라, 현재 솔더 범프는 주석을 기반으로 한 무연 솔더의 추세로 바뀌고 있다.As a result, solder bumps are now turning to tin-based lead-free solder.

이러한, 무연 솔더는 크게 볼 접착(Ball Attachment), 스크린 프린팅(Screen/Stencil Printing), 전해 도금(Electroplating) 등의 방법에 의해 형성된다.The lead-free solder is largely formed by a method such as ball attachment, screen / stencil printing, and electroplating.

이 중, 볼 접착 방법 및 스크린 프린팅 방법은 미세한 크기의 솔더 볼을 만들기가 어렵거나 페이스트(Paste)의 빠짐성이 좋지 않아 미세 피치 대응에 어려운 문제가 있다.Among these, the ball bonding method and the screen printing method have a problem in that it is difficult to make a solder ball having a fine size or the paste is not good because it is difficult to cope with fine pitch.

이에 반해, 전해 도금 방법은 위의 두 가지 방법에 비해 첨가 원소의 표준 화원 전위의 차이로 인해 이원계 이상의 도금에서는 각 도금 용액의 농도와 도금조(Bath)의 크기 및 상태, 시편의 위치 및 형태, 전극의 크기 및 형태 등에 따라 도금 조성 및 상태에 큰 영향을 받지만, 위의 두 가지 방법에 비해 미세 피치를 갖는 솔더 범프를 형성할 수 있는 이점이 있다.On the other hand, electrolytic plating method is compared with the above two methods, due to the difference in the standard source potential of the additive element in the two or more plating, the concentration of each plating solution, the size and condition of the bath (Bath), the location and shape of the specimen, Although it is greatly influenced by the plating composition and state depending on the size and shape of the electrode, there is an advantage that can form a solder bump having a fine pitch compared to the above two methods.

도 1은 종래 기술에 따른 솔더 범프를 나타내는 도면이다.1 is a view showing a solder bump according to the prior art.

도 1을 참조하면, 종래 기술에 따른 솔더 범프는 전자부품을 구성하는 금속층(106) 위에 형성된 구리 포스트(Cu Post)(102), 구리 포스트(102) 위에 주석(Sn)-은(Ag) 합금으로 형성된 솔더 범프(104)를 포함한다.Referring to FIG. 1, a solder bump according to the related art is a copper post 102 formed on a metal layer 106 constituting an electronic component, and a tin (Sn) -silver (Ag) alloy on the copper post 102. It includes a solder bump 104 formed as.

구리 포스트(102)는 전해 도금 공정을 통해 전자부품을 구성하는 금속층(106) 위에 형성된다.The copper post 102 is formed on the metal layer 106 constituting the electronic component through the electroplating process.

여기서, 금속층(106)은 인쇄회로기판이나 웨이퍼 레벨 패키지(Wafer Level Package; WLP)에 형성되는 회로패턴을 의미한다.Here, the metal layer 106 means a circuit pattern formed on a printed circuit board or a wafer level package (WLP).

이때, 금속층(106)이 인쇄회로기판에 형성될 경우 금속층(106)은 절연 층(108) 위에 형성되고, 금속층(106)의 일부를 제외한 나머지 부분의 절연층(108) 위에 솔더 레지스터층(110)이 형성된다.In this case, when the metal layer 106 is formed on the printed circuit board, the metal layer 106 is formed on the insulating layer 108, and the solder resistor layer 110 on the insulating layer 108 of the remaining portion except for a part of the metal layer 106. ) Is formed.

또한, 금속층(106) 위에는 금속층(106)을 외부로부터 보호하기 위해 금도금층(112)이 형성된다.In addition, a gold plating layer 112 is formed on the metal layer 106 to protect the metal layer 106 from the outside.

솔더 범프(104)는 구리 포스트(102) 위에 주석(Sn)-은(Ag) 합금 도금을 실시 한 후 리플로우 공정을 통해 상부가 원형 또는 타원형이 되도록 형성된다.The solder bumps 104 are formed on the copper posts 102 by tin (Sn) -silver (Ag) alloy plating and then formed to have a round or elliptical top portion through a reflow process.

이러한, 솔더 범프(104)를 주석(Sn)-은(Ag) 합금 도금을 통해 형성할 때 주석(Sn)-은(Ag) 합금 도금시 금속간 화합물(InterMetallic Compound; IMC)인 Ag3Sn 화합물이 생성되며, Ag3Sn 화합물에 의해 솔더 범프(104)의 기계적 강도가 향상되게 된다.When the solder bumps 104 are formed through tin (Sn) -silver (Ag) alloy plating, Ag 3 Sn compounds which are intermetallic compounds (IMC) during tin (Sn) -silver (Ag) alloy plating are formed. Is generated, and the mechanical strength of the solder bumps 104 is improved by the Ag 3 Sn compound.

그러나, 이와 같은 종래의 솔더 범프는 리플로우 공정에서 주석(Sn)-은(Ag) 합금 도금 시 생성된 Ag3Sn 금속간 화합물이 성장하며, 장시간 사용에 따라 시효 효과에 의해 더욱 조대화 되어 솔더 범프(104)의 강도를 감소시키는 문제가 있다.However, such a conventional solder bump is a Ag 3 Sn intermetallic compound formed during the plating of the tin (Sn)-silver (Ag) alloy in the reflow process, and is further coarsened by the aging effect with prolonged use, the solder There is a problem of reducing the strength of bump 104.

또한, 종래의 솔더 범프는 시효 효과에 의해 구리 포스트(102)와 주석(Sn)-은(Ag) 솔더 계면에서 연속적인 구리(Cu)-주석(Sn) 금속간 화합물(114)인 Cu6Sn5, CuSn3이 형성되어 짧은 크랙(Crack) 전파 경로를 제공하게 되므로 칩과 기판 사이의 접합 신뢰성이 저하되어 전기적 신호 전달 수행이 어려운 문제가 있다.In addition, the conventional solder bumps are Cu 6 Sn, which is a continuous copper (Cu) -tin (Sn) intermetallic compound (114) at the copper post 102 and tin (Sn) -silver (Ag) solder interface by the aging effect. 5 , CuSn 3 is formed to provide a short crack propagation path, thereby deteriorating the bonding reliability between the chip and the substrate, thereby making it difficult to perform electrical signal transmission.

따라서, 상술한 문제점을 해결하기 위해 본 발명의 실시 예에 따른 솔더 범프는 전자부품을 구성하는 금속층 위에 전해 도금 공정을 통해 형성된 구리 포스트; 상기 구리 포스트 위에 순차적으로 형성된 은도금층 및 주석도금층을 포함하는 것을 특징으로 한다.Accordingly, in order to solve the above-described problems, the solder bumps may include a copper post formed through an electroplating process on a metal layer constituting an electronic component; It characterized in that it comprises a silver plated layer and a tin plated layer formed sequentially on the copper post.

또한, 본 발명의 실시 예에 따른 솔더 범프는 상기 구리 포스트 위에 순차적으로 형성된 상기 은도금층 및 주석도금층이 다수 개 적층 된다.In addition, the solder bump according to the embodiment of the present invention is a plurality of the silver plating layer and tin plating layer sequentially formed on the copper post.

또한, 본 발명의 실시 예에 따른 솔더 범프는 상기 금속층과 상기 구리 포스트 사이에 형성된 금도금층을 더 포함하는 것을 특징으로 한다.In addition, the solder bump according to an embodiment of the present invention is characterized in that it further comprises a gold plated layer formed between the metal layer and the copper post.

본 발명은 구리 포스트, 은도금층 및 주석도금층 순으로 솔더 범프를 형성되기 때문에 구리 포스트와 솔더 계면에서 생성되는 금속간 화합물인 Ag3Sn의 생성이 억제되어 리플로우 및 시효 효과에 의한 Ag3Sn 성장으로 인해 야기되는 솔더 범프의 기계적 강도 감소를 방지할 수 있다.In the present invention, since the solder bumps are formed in the order of the copper posts, the silver plating layer, and the tin plating layer, the generation of Ag 3 Sn, which is an intermetallic compound generated at the copper post and the solder interface, is suppressed, so that Ag 3 Sn growth is caused by reflow and aging effects. It is possible to prevent a decrease in the mechanical strength of the solder bumps caused by.

또한, 본 발명은 구리 포스트 위에 은도금층이 형성되기 때문에 은도금층이 버퍼층 역할을 하게 되어 구리 포스트와 주석도금층의 직접적인 접합을 방지하기 때문에 시효 효과로 인해 주석(Sn)과 금속간 화합물을 생성할 수 있는 구리(Cu)의 농도를 낮출 수 있게 되어 구리 포스트와 솔더 계면에서 생성되는 금속간 화합물인 Ag3Sn의 생성이 억제되므로 구리(Cu)-주석(Sn)계 금속간 화합물 생성을 억제할 수 있게 되어 크랙 전파 경로가 길어지게 되어 솔더 범프의 접합 신뢰성을 향상시킬 수 있다.In addition, in the present invention, since the silver plated layer is formed on the copper post, the silver plated layer serves as a buffer layer to prevent direct bonding between the copper post and the tin plated layer, thereby generating tin (Sn) and an intermetallic compound due to an aging effect. It is possible to lower the concentration of copper (Cu), thereby inhibiting the formation of Ag 3 Sn, an intermetallic compound formed at the copper post and solder interface, thereby suppressing the formation of copper (Cu) -tin (Sn) -based intermetallic compounds. This results in longer crack propagation paths, which improves solder bump joint reliability.

이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시 예를 상세하게 설명한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

도 2는 본 발명의 실시 예에 따른 솔더 범프를 나타내는 도면이다.2 is a view showing a solder bump according to an embodiment of the present invention.

도 2를 참조하면, 본 발명의 실시 예에 따른 솔더 범프는 전자부품의 금속층(12) 위에 전해 도금 공정을 통해 형성된 구리 포스트(2), 도금 공정을 통해 구리 포스트(2) 위에 형성된 제 1 은도금층(4), 도금 공정을 통해 제 1 은도금층(4) 위에 형성된 제 1 주석도금층(6), 도금 공정을 통해 제 1 주석도금층(6) 위에 형성 된 제 2 은도금층(8), 도금 공정을 통해 제 2 은도금층(8) 위에 형성된 제 2 주석도금층(10)을 포함한다.Referring to FIG. 2, a solder bump according to an embodiment of the present invention is a copper post 2 formed through an electroplating process on a metal layer 12 of an electronic component, and a first silver plating formed on a copper post 2 through a plating process. Layer 4, a first tin plating layer 6 formed on the first silver plating layer 4 through a plating process, a second silver plating layer 8 formed on the first tin plating layer 6 through a plating process, a plating process It includes a second tin plating layer 10 formed on the second silver plating layer 8 through.

구리 포스트(2)는 전해 도금 공정을 통해 전자부품의 금속층(12) 위에 형성된다.The copper post 2 is formed on the metal layer 12 of the electronic component through an electroplating process.

여기서, 금속층(12)은 인쇄회로기판이나 웨이퍼 레벨 패키지에 형성되는 회로패턴을 의미한다.Here, the metal layer 12 means a circuit pattern formed on a printed circuit board or a wafer level package.

이때, 금속층(12)이 인쇄회로기판에 형성될 경우 금속층(12)은 절연층(18) 위에 형성되고, 금속층(12)의 일부를 제외한 나머지 부분의 절연층(18) 위에 솔더 레지스터층(16)이 형성된다.In this case, when the metal layer 12 is formed on the printed circuit board, the metal layer 12 is formed on the insulating layer 18, and the solder resistor layer 16 on the insulating layer 18 of the remaining portion except for a part of the metal layer 12. ) Is formed.

또한, 금속층(12) 위에는 금속층(12)을 외부로부터 보호하기 위해 금도금층(14)이 형성된다.In addition, a gold plated layer 14 is formed on the metal layer 12 to protect the metal layer 12 from the outside.

즉, 금속층(12)이 인쇄회로기판에 형성되어 있을 경우 금도금층(14)은 금속층(12)과 구리 포스트(2) 사이에 형성된다.That is, when the metal layer 12 is formed on the printed circuit board, the gold plated layer 14 is formed between the metal layer 12 and the copper post (2).

그러나, 금속층(12)이 웨이퍼 레벨 패키지에 형성될 경우에는 솔더 레지스터층(16) 및 금도금층(14)은 형성되지 않는다.However, when the metal layer 12 is formed in the wafer level package, the solder resist layer 16 and the gold plated layer 14 are not formed.

제 1 은도금층(4), 제 1 주석도금층(6), 제 2 은도금층(8) 및 제 2 주석도금층(10)은 도금 공정을 통해 구리 포스트(2) 위에 순차적으로 형성된다.The first silver plating layer 4, the first tin plating layer 6, the second silver plating layer 8, and the second tin plating layer 10 are sequentially formed on the copper post 2 through a plating process.

즉, 도금 공정을 통해 구리 포스트(2) 위에 제 1 은도금층(4)을 형성한 후 도금 공정을 통해 제 1 은도금층(4) 위에 제 1 주석도금층(6)을 형성한다.That is, after the first silver plating layer 4 is formed on the copper post 2 through the plating process, the first tin plating layer 6 is formed on the first silver plating layer 4 through the plating process.

이때, 제 2 은도금층(8) 및 제 2 주석도금층(10)은 제 1 은도금층(4) 및 제 1 주석도금층(6)과 동일하게 형성된다.In this case, the second silver plating layer 8 and the second tin plating layer 10 are formed in the same manner as the first silver plating layer 4 and the first tin plating layer 6.

즉, 도금 공정을 통해 제 1 주석도금층(6) 위에 제 2 은도금층(8)을 형성한 후 도금 공정을 통해 제 2 은도금층(8) 위에 제 2 주석도금층(10)을 형성한다.That is, after the second silver plating layer 8 is formed on the first tin plating layer 6 through the plating process, the second tin plating layer 10 is formed on the second silver plating layer 8 through the plating process.

여기서, 은도금층 및 주석도금층은 구리 포스트(2) 위에 한 층으로만 적층 되거나 다수의 층이 적층 될 수 있다.Here, the silver plated layer and the tin plated layer may be stacked only one layer on the copper post 2 or a plurality of layers may be stacked.

다시 말해, 구리 포스트(2) 위에는 제 1 은도금층(4) 및 제 1 주석도금층(6)만 적층 되거나 제 2 주석도금층(10) 위에 은도금층 및 주석도금층이 순차적으로 다수개가 더 적층 될 수도 있다.In other words, only the first silver plating layer 4 and the first tin plating layer 6 may be stacked on the copper post 2, or a plurality of silver plating layers and tin plating layers may be sequentially stacked on the second tin plating layer 10. .

이와 같이 본 발명의 실시 예에 따른 솔더 범프(30)는 구리 포스트(2), 제 1 은도금층(4), 제 1 주석도금층(6), 제 2 은도금층(8), 제 2 주석도금층(10) 순으로 솔더 범프(30)를 형성할 경우 구리 포스트(2)와 솔더 계면에서 생성되는 금속간 화합물인 Ag3Sn이 종래 기술과 같이 주석(Sn)-은(Ag) 합금 도금을 이용할 때보다 억제되기 때문에 리플로우 및 시효 효과에 의한 Ag3Sn 성장으로 인해 야기되는 솔더 범프(30)의 기계적 강도 감소를 방지할 수 있게 된다.Thus, the solder bump 30 according to the embodiment of the present invention is a copper post 2, the first silver plating layer 4, the first tin plating layer 6, the second silver plating layer 8, the second tin plating layer ( 10) In the case of forming the solder bumps 30 in this order, Ag 3 Sn, an intermetallic compound generated at the copper post 2 and the solder interface, is used when using tin (Sn) -silver (Ag) alloy plating as in the prior art. Since all are suppressed, it is possible to prevent a decrease in the mechanical strength of the solder bumps 30 caused by Ag 3 Sn growth due to reflow and aging effects.

또한, 종래 기술에 따른 솔더 범프(30)는 구리 포스트와 솔더 계면의 접합구조가 구리(Cu)-주석(Sn)/은(Ag)로 되어 있기 때문에 장시간 사용 시 구리(Cu)-주석(Sn)계 금속간 화합물이 형성되어 짧은 크랙 전파 경로를 제공하여 솔더 범프의 접합 신뢰성을 저하시키는 데 반해 본 발명은 구리 포스트(2) 위에 제 1 은도금층(4)이 형성되기 때문에 구리(Cu)-주석(Sn)계 금속간 화합물 생성을 억제할 수 있 게 되어 솔더 범프(30)의 접합 신뢰성을 향상시킬 수 있게 된다.In addition, the solder bump 30 according to the prior art has a copper (Cu) -tin (Sn) / silver (Ag) bonding structure between a copper post and a solder interface, and thus, copper (Cu) -tin (Sn) may be used for a long time. In the present invention, the first silver plated layer 4 is formed on the copper post 2, whereas the (Cu) —intermetallic compound is formed to provide a short crack propagation path. It is possible to suppress the generation of the tin (Sn) -based intermetallic compound, thereby improving the bonding reliability of the solder bumps 30.

도 1은 종래 기술에 따른 솔더 범프를 나타내는 도면이다.1 is a view showing a solder bump according to the prior art.

도 2는 본 발명의 실시 예에 따른 솔더 범프를 나타내는 도면이다.2 is a view showing a solder bump according to an embodiment of the present invention.

<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>

2, 102 : 구리 포스트 4, 8 : 은도금층2, 102: copper post 4, 8: silver plated layer

6, 10 : 주석도금층 12, 106 : 금속층6, 10: tin plated layer 12, 106: metal layer

14, 112 : 금도금층 16, 110 : 솔더 레지스터층14, 112: gold plated layer 16, 110: solder resistor layer

18, 108 : 절연층18, 108: insulation layer

Claims (3)

전자부품을 구성하는 금속층 위에 전해 도금 공정을 통해 형성된 구리 포스트; 및A copper post formed on the metal layer constituting the electronic component through an electroplating process; And 상기 구리 포스트 위에 순차적으로 형성된 은도금층 및 주석도금층을 포함하는 것을 특징으로 하는 솔더 범프.Solder bumps comprising a silver plated layer and a tin plated layer formed sequentially on the copper post. 청구항 1에 있어서,The method according to claim 1, 상기 구리 포스트 위에는 순차적으로 형성된 상기 은도금층 및 주석도금층이 다수 개 적층 되는 것을 특징으로 하는 솔더 범프.Solder bumps, characterized in that a plurality of the silver plating layer and tin plating layer formed sequentially on the copper post is laminated. 청구항 1에 있어서,The method according to claim 1, 상기 금속층과 상기 구리 포스트 사이에 형성된 금도금층을 더 포함하는 것을 특징으로 하는 솔더 범프.The solder bump further comprises a gold plated layer formed between the metal layer and the copper post.
KR1020070094273A 2007-09-17 2007-09-17 Solder bump KR100878916B1 (en)

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI465333B (en) * 2012-07-25 2014-12-21 Jx Nippon Mining & Metals Corp Electronic material for electronic parts and method for manufacturing the same, use of its connector terminals, connectors and electronic parts
TWI465334B (en) * 2012-06-27 2014-12-21 Jx Nippon Mining & Metals Corp Electronic material for electronic parts and method for manufacturing the same, use of its connector terminals, connectors and electronic parts
TWI466773B (en) * 2012-06-27 2015-01-01 Jx Nippon Mining & Metals Corp Electronic material for electronic parts and method for manufacturing the same, use of its connector terminals, connectors and electronic parts
TWI473707B (en) * 2012-06-27 2015-02-21 Jx Nippon Mining & Metals Corp Electronic material for electronic parts and method for manufacturing the same, use of its connector terminals, connectors and electronic parts

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0737935A (en) * 1993-07-16 1995-02-07 Matsushita Electric Ind Co Ltd Mounting method for flip chip
KR20040056367A (en) * 2002-12-23 2004-06-30 삼성전자주식회사 Method of fabricating Pb-free solder bumps

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0737935A (en) * 1993-07-16 1995-02-07 Matsushita Electric Ind Co Ltd Mounting method for flip chip
KR20040056367A (en) * 2002-12-23 2004-06-30 삼성전자주식회사 Method of fabricating Pb-free solder bumps

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI465334B (en) * 2012-06-27 2014-12-21 Jx Nippon Mining & Metals Corp Electronic material for electronic parts and method for manufacturing the same, use of its connector terminals, connectors and electronic parts
TWI466773B (en) * 2012-06-27 2015-01-01 Jx Nippon Mining & Metals Corp Electronic material for electronic parts and method for manufacturing the same, use of its connector terminals, connectors and electronic parts
TWI473707B (en) * 2012-06-27 2015-02-21 Jx Nippon Mining & Metals Corp Electronic material for electronic parts and method for manufacturing the same, use of its connector terminals, connectors and electronic parts
TWI465333B (en) * 2012-07-25 2014-12-21 Jx Nippon Mining & Metals Corp Electronic material for electronic parts and method for manufacturing the same, use of its connector terminals, connectors and electronic parts

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