JP6024079B2 - Semiconductor device, method for manufacturing the same, and electronic device - Google Patents

Description

  The present invention relates to a semiconductor device, a manufacturing method thereof, and an electronic device, for example, a semiconductor device that joins an element and a substrate using bumps, a manufacturing method thereof, and an electronic device.

  Solder bumps are used for joining elements such as semiconductor elements and substrates such as circuit boards. For high integration, it is known that a mesa-shaped post electrode whose bottom surface is smaller than the top surface and spherical solder is provided on the post electrode, and bumps are formed by the post electrode and the spherical solder (for example, Patent Document 1). Further, it is known that a refractory metal layer, a first solder, a refractory metal layer, and a second solder having a melting point lower than that of the first solder are sequentially laminated on a substrate and used as bumps (for example, Patent Document 2).

JP 2010-3793 A JP 2010-27849 A

  For example, the solder bumps relieve thermal stress caused by heat treatment when the element and the substrate are joined. However, when the bumps are highly integrated, if the amount of solder is reduced so that adjacent bumps do not come into contact with each other, the thermal stress of the element or / and the substrate cannot be alleviated with the solder bumps alone. Thereby, peeling of a bump or a crack in a bump occurs. Further, for example, as in Patent Document 1, when bumps are formed with post electrodes and spherical solder, the spherical bumps bonded to the element relieve thermal stress. For example, in Patent Document 2, the second solder joined to the element relieves thermal stress. As described above, when the thermal stress is relieved by the solder bonded to the element or the substrate, the solder bonded to the element or the substrate is deformed. Therefore, there is a possibility that contact between adjacent bumps may occur, and it is difficult to increase the integration of the bumps.

  An object of the present semiconductor device, a manufacturing method thereof, and an electronic device is to relieve thermal stress caused by heat treatment at the time of bonding an element and a substrate at a central portion of a bump.

For example, a step of forming a first conductor on one of the element and the substrate, a step of forming a second conductor on the first conductor, and a third conductor on the second conductor Forming a body, forming a fourth conductor having a melting point higher than that of the second conductor on the other of the element and the substrate, the first conductor , the second conductor , and the first Three conductors are bonded to one of the element and the substrate, and the fourth conductor is connected to the other of the element and the substrate, and below the melting point of the first conductor and the third conductor. And a step of joining the third conductor and the fourth conductor by heating to a temperature equal to or higher than the melting points of the second conductor and the fourth conductor. A method for manufacturing a semiconductor device is used.

  For example, an electronic device including the semiconductor device is used.

  According to the semiconductor device, the manufacturing method thereof, and the electronic device, the thermal stress caused by the heat treatment at the time of joining the element and the substrate can be reduced at the central portion of the bump.

FIG. 1A to FIG. 1D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to a comparative example. 2A to 2D are cross-sectional views illustrating the method for manufacturing the semiconductor device according to the first embodiment. 3 (a) and 3 (b) are enlarged views of the bumps 30a and 30b in FIG. 2 (b). 4A to 4D are cross-sectional views (part 1) illustrating the method for manufacturing the semiconductor device according to the second embodiment. FIG. 5A to FIG. 5D are cross-sectional views (part 2) illustrating the method for manufacturing the semiconductor device according to the second embodiment. FIG. 6A and FIG. 6B are cross-sectional views (part 3) illustrating the method for manufacturing the semiconductor device according to the second embodiment. 7A and 7B are cross-sectional views (part 4) illustrating the method for manufacturing the semiconductor device according to the second embodiment. FIG. 8 is a sectional view of the bump. FIG. 9A to FIG. 9C are cross-sectional views illustrating heat treatment. FIG. 10 is a cross-sectional view of the semiconductor device according to the third embodiment. FIG. 11 is an enlarged view of region B in FIG. FIG. 12 is a cross-sectional view of the electronic device according to the fourth embodiment.

  Before describing the examples, comparative examples will be described. First, the bonding between the element using the solder bump and the substrate will be described. FIG. 1A to FIG. 1D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to a comparative example. As shown in FIG. 1A, an element 10 such as a silicon element includes an element substrate 11 and an electrode pad 12 formed on the lower surface of the element substrate 11. The element substrate 11 is, for example, a silicon substrate having an electronic circuit formed on the substrate 20 side. A substrate 20 such as a circuit wiring substrate includes an insulating substrate 21 and a wiring electrode 22 formed on the upper surface of the insulating substrate 21. The insulating substrate 21 is a circuit board using, for example, a glass epoxy resin. Solder bumps 14 are formed on the lower surface of the electrode pads 12. Preliminary solder 24 is provided on the upper surface of the wiring electrode 22. The solder bump 14 and the spare solder 24 are, for example, lead-free solder such as Sn-3.0Ag-0.5Cu.

  As shown in FIG. 1B, the preliminary solder 24 is melted. The preliminary solder 24 is provided so that the bonding of the solder bumps 14 can be maintained even when the substrate 20 is warped, for example, due to thermal stress at the time of bonding between the element 10 and the substrate 20. However, when the solder bump 14 and the preliminary solder 24 are highly integrated, the interval between the adjacent preliminary solders 24 is reduced. For this reason, the amount of the preliminary solder 24 is reduced so that adjacent preliminary solders 24 are not in contact and short-circuited. For example, the height of the preliminary solder 24 is reduced.

  As shown in FIG. 1C, the element 10 and the substrate 20 are heat-treated at, for example, 250 ° C. in a state where the solder bump 14 and the preliminary solder 24 are in contact with each other. Thereby, the solder bump 14 and the preliminary solder 24 are melted. As shown in FIG. 1D, the heat treatment is completed, and the element 10 and the substrate 20 are cooled to room temperature (for example, 25 ° C.). At this time, for example, the substrate 20 may warp due to thermal stress. In FIG. 1D, the substrate 20 is warped upward. When the amount of the spare solder 24 is small, the warp cannot be reduced by the spare solder 24. For this reason, the solder bumps 14 and the spare solder 24 around the element 10 are peeled off as in the region 52 of FIG. Alternatively, a crack 50 is generated between the solder bump 14 and the preliminary solder 24. In addition, in FIG.1 (d), although the case where the board | substrate 20 curved in convex shape was demonstrated to the example, the board | substrate 20 may curve in concave shape. Further, the element 10 may warp in a convex shape or a concave shape. Furthermore, due to the difference in thermal expansion coefficient between the element 10 and the substrate 20, a shear stress may occur between the solder bump 14 and the preliminary solder 24. In either case, there is a possibility that the solder bump 14 and the spare solder 24 will be peeled off. In addition, a crack 50 may occur between the solder bump 14 and the preliminary solder 24.

  Further, for example, in the examples of Patent Documents 1 and 2, the thermal stress is relieved by the solder bonded to the element or the substrate. For this reason, contact etc. of adjacent bumps may arise, and high integration of bumps becomes difficult. Examples that solve the problems of the comparative example and the examples of Patent Documents 1 and 2 will be described below.

  2A to 2D are cross-sectional views illustrating the method for manufacturing the semiconductor device according to the first embodiment. As shown in FIG. 2A, the fourth conductor 38 is formed under the electrode pad 12 of the element 10. The fourth conductor 38 has a hemispherical shape, and is formed of a brazing material containing Sn and Zn such as Sn—Zn. A first conductor 32 is formed on the wiring electrode 22 of the substrate 20. The first conductor 32 is a metal such as Cu (copper), for example, and has a trapezoidal shape in which the upper surface is narrower on the left and right sides than the bottom.

  As shown in FIG. 2B, the second conductor 34 and the third conductor 36 are stacked on the first conductor 32. The second conductor 34 includes, for example, Sn and Bi such as Sn—Bi or In, or is formed of a brazing material including In. A third conductor 36 is formed on the second conductor 34. For example, the left and right widths of the first conductor 32 on the substrate 20 side are larger than the left and right widths on the second conductor 34 side. In other words, the first conductor 32 has a larger cross-sectional area on the substrate 20 side than a cross-sectional area on the second conductor 34 side. The third conductor 36 is formed of a conductor containing Sn, Ag, and Cu, such as Sn—Ag—Cu solder. The left and right widths of the second conductor 34 and the fourth conductor 38 are, for example, approximately the same as the upper surface of the first conductor 32. The first conductor 32 and the third conductor 36 are higher than the melting points of the second conductor 34 and the fourth conductor 38. The fourth conductor 38 has a higher melting point than the second conductor 34.

  As shown in FIG. 2C, the element 10 and the substrate 20 are aligned using a flip chip bonder. Pressure is applied to the element 10 and the substrate 20 so that the third conductor 36 and the fourth conductor 38 are in contact with each other. In this state, the third conductor 36 and the fourth conductor 38 are joined by heating. The heating temperature is set to a temperature not higher than the melting points of the first conductor 32 and the third conductor 36 and not lower than the melting points of the second conductor 34 and the fourth conductor 38. Thereby, the bump 30 that electrically connects the element 10 and the substrate 20 is formed from the first conductor 32, the second conductor 34, the third conductor 36, and the fourth conductor 38. In the heated state, the second conductor 34 melts but does not form an alloy with the first conductor 32 and the third conductor 36, and only adapts. In addition, the fourth conductor 38 melts but does not alloy with the third conductor 36, and only conforms. In addition, since the third conductor 36 does not melt, the second conductor 34 and the fourth conductor 38 can be prevented from being alloyed.

  As shown in FIG. 2D, the heat treatment is completed, and the element 10 and the substrate 20 are cooled to room temperature (for example, 25 ° C.). At this time, the substrate 20 warps as shown in FIG. However, the second conductor 34 is cooled in a molten state, and finally the second conductor 34 is solidified. For this reason, the second conductor 34 functions as a relaxation layer.

  3 (a) and 3 (b) are enlarged views of the bumps 30a and 30b in FIG. 2 (b). As shown in FIG. 3A, the positions of the first conductor 32 and the fourth conductor 38 in the bump 30a at the center of the element 10 are not significantly different from the heating state in FIG. As shown in FIG. 3B, in the bump 30 b in the peripheral portion of the element 10, the substrate 20 warps in a convex manner, so that the first conductor 32 faces outward, and the first conductor 32 and the fourth conductor 38. And the distance will come apart. However, the second conductor 34 is deformed as a relaxation layer, and the bonding between the first conductor 32 and the fourth conductor 38 is maintained. Note that the second conductor 34 similarly functions as a buffer layer when the substrate 20 warps in a concave shape or when the element 10 warps in a convex shape or a concave shape.

  According to the first embodiment, when the bumps 30 are formed by bonding the fourth conductor 38 such as a brazing material and the first conductor 32 such as a refractory metal, the first conductor 32 and the fourth conductor 38 are formed. And the second conductor 34 having the lowest melting point. As a result, the second conductor 34 functions as a thermal stress relaxation layer. Further, a third conductor 36 having a higher melting point than the second conductor 34 and the fourth conductor 38 is provided between the second conductor 34 and the fourth conductor 38. Thereby, when the 2nd conductor 34 and the 4th conductor 38 are fuse | melted, it can suppress that the 2nd conductor 34 and the 4th conductor 38 alloy.

  That is, in the first embodiment, the first conductor 32 and the third conductor 36 have a higher melting point than the second conductor 34 and the fourth conductor 38. The fourth conductor 38 has a higher melting point than the second conductor. As a result, the second conductor 34 having the lowest melting point solidifies last when cooled, and functions as a thermal stress relaxation layer. Therefore, when the fourth conductor 38 such as a brazing material and the first conductor 32 such as a refractory metal are joined, the thermal stress caused by the heat treatment can be relaxed in the central portion of the bump 30. Thereby, peeling of the bumps or cracks in the bumps can be suppressed, and the bumps can be highly integrated.

  Furthermore, the first conductor 32 preferably has a higher melting point than the third conductor 36. Accordingly, a metal having a relatively high melting point such as Cu or Au can be used as the first conductor 32.

  The first conductor 32, the second conductor 34, the third conductor 36, and the fourth conductor 38 may all have the same width. For example, the cross sections of the first conductor 32, the second conductor 34, the third conductor 36, and the fourth conductor 38 parallel to the substrate 20 may all be the same. The widths of the first conductor 32, the second conductor 34, the third conductor 36, and the fourth conductor 38 may be different.

  However, since the second conductor 34 has the lowest melting point, it is most easily deformed. Therefore, when the volume of the second conductor 34 is large, the second conductor 34 may be crushed by the compressive stress between the first conductor 32 and the third conductor 36. In this case, the 2nd conductor 34 deform | transforms into the side surface direction of the bump 30, and it becomes easy to contact adjacent bumps 30 mutually.

  According to the first embodiment, the width of the second conductor 34 is the smallest among the bumps 30. For example, the cross-sectional area of the second conductor 34 parallel to the substrate 20 is the smallest among the bumps 30. Thereby, even when the compressive stress between the first conductor 32 and the third conductor 36 is applied to the second conductor 34, the amount by which the second conductor 34 is deformed in the side surface direction of the bump 30. Can be reduced. Therefore, it becomes difficult for the adjacent bumps 30 to contact each other. As a result, the bumps 30 can be highly integrated.

  In order to reduce the width of the second conductor 34, the width of the first conductor 32 on the second conductor 34 side is preferably smaller than the substrate 20 side. For example, the cross-sectional area of the first conductor 32 on the second conductor 34 side is preferably smaller than the substrate side. The 1st conductor 32 can be made into a truncated cone shape, for example. Further, the first conductor 32 may have an elliptical shape, a rectangular shape, or a polygonal planar shape, and a trapezoidal side shape. Furthermore, the width of the second conductor 34 is preferably the same as the width of the first conductor 32 on the second conductor 34 side.

  Furthermore, the width of the fourth conductor 38 on the third conductor 36 side is preferably smaller than the element 10 side. In the case where the fourth conductor 38 is formed in the element 10, the width of the fourth conductor 38 on the element 10 side is increased if an attempt is made to secure the height of the fourth conductor 38. Similarly, when the first conductor 32 is formed on the substrate 20, the width of the fourth conductor 38 or the first conductor 32 on the substrate 20 side is increased if the height of the first conductor 32 is to be secured. End up. On the other hand, as described above, the width of the second conductor 34 is preferably small from the viewpoint of suppressing contact with adjacent bumps. Therefore, the width of the first conductor 32 on the second conductor 34 side is made smaller than that on the substrate 20 side, and the width of the fourth conductor 38 on the third conductor 36 side is made smaller than that on the element 10 side. The width of the second conductor 34 is made smaller than the width of the first conductor 32 on the substrate 20 side and the width of the fourth conductor 38 on the element 10 side. Thereby, the height of the bump 30 can be secured and contact with the adjacent bump can be suppressed. Therefore, the bumps 30 can be highly integrated.

  Although the metal which forms the 1st conductor 32, the 2nd conductor 34, the 3rd conductor 36, and the 4th conductor 38 is not restricted to what was illustrated, it is preferable not to mutually alloy by heat processing. In order to reduce the resistance of the bump 30, the first conductor 32 is preferably a low-resistance metal such as Cu or Au.

  4A to 7B are cross-sectional views illustrating a method for manufacturing a semiconductor device according to the second embodiment. As shown in FIG. 4A, the substrate 20 is a multilayer circuit board, and a plurality of insulating layers 21a to 21e are stacked. The size of the substrate 20 is, for example, 50 mm × 50 mm, and the thickness of the substrate 20 is, for example, 1 mm. The insulating layers 21a to 21e are formed of an insulator such as glass epoxy resin. A wiring 25 formed of a metal film such as Cu is formed between the insulating layers 21a to 21e. Via wirings 26 are formed through the insulating layers 21a to 21e so as to electrically connect the wirings 25 to each other. A wiring electrode 22 made of a metal such as Cu is formed on the lower surface of the insulating layer 21a and the upper surface of the insulating layer 21e. A solder resist 28 having an opening is formed on the wiring electrode 22. The solder resist 28 is formed of an insulating film such as an epoxy resin. The thickness of the solder resist 28 is, for example, 20 μm. The wiring electrodes 22 exposed from the solder resist 28 have a diameter of 100 μm and are arranged in a grid at a pitch of 150 μm.

A dry film resist 60 is pasted on the substrate 20 and dried at 90 ° C. for 30 minutes using an oven. Thereafter, a mask is disposed on the dry film resist 60 and exposed at an exposure amount of 400 mJ / cm ² . Development is performed using a 1 wt% aqueous sodium carbonate solution. As a result, an opening 62 having the same size as the opening of the solder resist 28 is formed on the opening of the solder resist 28.

As shown in FIG. 4B, Cu is electroplated in the opening 62. The conditions for electrolytic plating are as follows.
Electrolytic plating conditions Plating solution composition Copper sulfate (pentahydrate) 225g / L
Sulfuric acid (98wt%) 55g / L
Chloride ion 60mg / L
Reaction condensate of amines and glycidyl ether 250 mg / L
Bisusuruho organic compounds _{(SO 3 HC 3 H 6 -SSC} 3 H 6 -SO 3 H) 6mg / L
Plating conditions Anode metal Cu
Current density 2A / dm ²
Plating time 80 minutes Thereby, for example, a cylindrical Cu post 31 having a diameter of about 100 μm is formed.

As shown in FIG. 4C, the dry film resist 60 is peeled off with acetone and washed with water. Then, it is dried. As shown in FIG. 4D, a liquid resist is applied using a spin coater. Dry using an oven for 30 minutes at a temperature of 90 ° C. As a result, a resist 64 having a thickness of about 15 μm is formed on the substrate 20 and the Cu post 31. A mask is arranged and the resist 64 is exposed with an exposure amount of 350 mJ / cm ² . Then develop. Thereby, a ring-shaped opening 66 is formed in the resist 64 around the Cu post 31. The inner diameter and outer diameter of the opening 66 are 65 μm and 95 μm, respectively. Note that the outer diameter of the opening 66 may be smaller than the diameter of the Cu post 31 in consideration of an over-etching process margin in etching.

  As shown in FIG. 5A, the substrate 20 is immersed for about 45 minutes in an etchant in which penioxo II ammonium sulfate and pure water are mixed at a ratio of 1:20. A part of the Cu post 31 is etched by the etchant entering from the opening 66. Thereby, the shape of the Cu post 31 changes from a cylindrical shape to a truncated cone shape (a shape in which the diameter of the upper surface is smaller than that of the bottom surface). The substrate 20 is taken out from the etching solution.

  As shown in FIG. 5B, the resist is peeled off and washed with water. Then, it dries. Thus, the first conductor 32 having a truncated cone shape is formed from the Cu post 31. The diameters of the top surface and the bottom surface of the first conductor 32 are, for example, 60 μm and 90 μm, respectively.

As shown in FIG. 5C, a dry film resist 68 having a thickness of about 35 μm is pasted on the substrate 20 and the first conductor 32. Dry using an oven for 30 minutes at a temperature of 90 ° C. Thereafter, a mask is disposed on the dry film resist 60 and exposed at an exposure amount of 400 mJ / cm ² . Development is performed using a 1 wt% aqueous sodium carbonate solution. As a result, an opening 70 having the same size as the upper surface of the first conductor 32 is formed on the first conductor 32.

As shown in FIG. 5D, Sn-Bi having a thickness of about 15 μm is electrolytically plated on the upper surface of the first conductor 32 in the opening 70 using the following electrolytic plating conditions.
Conditions for electrolytic plating Plating solution composition Tin sulfate 10g / L
Bismuth sulfate 7.5g / L
Glucoheptonic acid 120 g / L
Ammonium methanesulfonate 80g / L
Peptone 1g / L
Plating conditions Anode metal Pt
Current density 5A / dm ²
Thus, the second conductor 34 having a thickness of about 15 μm and a diameter of about 60 μm is formed on the first conductor 32.

As shown in FIG. 6A, Sn—Ag—Cu having a thickness of about 20 μm is electroplated on the upper surface of the second conductor 34 in the opening 70 using the following electroplating conditions.
Electrolytic plating conditions Plating solution composition Stannous methanesulfonate 0.34 mol / L
Copper hydroxide 0.005 mol / L
Silver oxide 0.024 mol / L
Methanesulfonic acid 2.64 mol / L
Acetylcysteine 0.15 mol / L
2,2-dithiodianiline 0.025 mol / L
α-Naphthol polyethoxylate 3g / L
Plating conditions Anode metal Sn
Current density 6A / dm ²
Plating time 15 minutes Thereby, the third conductor 36 having a thickness of about 20 μm and a diameter of about 60 μm is formed on the second conductor 34.

  As shown in FIG. 6B, the dry film resist 60 is peeled off with acetone and washed with water. Then, it dries. As described above, the frustoconical first conductor 32 is formed on the wiring electrode 22, the second conductor 34 having the same width as the upper surface of the first conductor 32, and the second conductor 34 on the first conductor 32. The third conductor 36 is formed.

  As shown in FIG. 7A, an electrode pad 12 is formed on the lower surface of the element 10. A protective film 16 having an opening in the electrode pad 12 is formed on the lower surface of the element 10. A fourth conductor 38 is formed under the electrode pad 12. The fourth conductor 38 is made of, for example, Sn—Zn. The fourth conductor 38 has a diameter of 100 μm and a pitch of 150 μm. The element 10 and the substrate 20 are set in a flip chip bonder. The element 10 and the substrate 20 are aligned so that the third conductor 36 and the fourth conductor 38 face each other. The third conductor 36 and the fourth conductor 38 are temporarily joined.

  As shown in FIG. 7B, heat treatment is performed at a temperature between 199 ° C., which is the melting point of Sn—Zn, and 219 ° C., which is the melting point of Sn—Ag—Cu, in a reflow furnace in a nitrogen atmosphere. Thereby, the 3rd conductor 36 and the 4th conductor 38 join. A bump 30 is formed in which the first conductor 32, the second conductor 34, the third conductor 36, and the fourth conductor 38 are sequentially laminated. In the second embodiment, Sn: 55 wt% -Bi: 45 wt% is used as the second conductor 34. The melting point of the second conductor 34 is 145 ° C. As the third conductor 36, Sn: 96.3 wt% -Ag: 3 wt% -Cu: 0.7 wt% is used. The melting point of the third conductor 36 is 219 ° C. As the fourth conductor 38, Sn: 91wt% -Zn: 9wt% is used. The melting point of the fourth conductor 38 is 199 ° C.

  FIG. 8 is a cross-sectional view of the bump 30. The diameter W1 of the bottom surface of the first conductor 32 is 90 μm, the diameter W1 of the top surface of the first conductor 32 is 60 μm, and the height H1 of the first conductor 32 is 50 μm. The height H2 of the second conductor 34 is 15 μm, and the diameter of the second conductor 34 is 60 μm. The height H3 of the third conductor 36 is 20 μm, and the diameter of the third conductor 36 is 60 μm. The diameter W3 of the fourth conductor 38 is 100 μm.

  FIG. 9A to FIG. 9C are cross-sectional views illustrating heat treatment. As shown in FIG. 9A, the temperature gradually increases at the beginning of the heat treatment. As the substrate 20 is softened, the substrate 20 is gradually warped. When the temperature is near the melting point of the second conductor 34, the second conductor 34 starts to melt.

  As shown in FIG. 9B, when the temperature is maintained at the maximum temperature of the heat treatment, the warpage of the substrate 20 due to heating becomes the maximum. Since the temperature exceeds the melting point of the fourth conductor 38, the fourth conductor 38 melts. The first conductor 32 and the third conductor 36 do not melt and are in a solid state. The second conductor 34 does not flow out to the substrate 20 side because the first conductor 32 is solid. The second conductor 34 is not mixed with the fourth conductor 38 because the third conductor 36 is solid. Thus, the second conductor 34 stays between the first conductor 32 and the third conductor 36, and the heat treatment proceeds. The second conductor 34 is compatible with the first conductor 32 and the third conductor 36. The fourth conductor 38 is compatible with the third conductor 36.

  As shown in FIG. 9C, the warping of the substrate 20 returns to the original state in the cooling step to room temperature. Since the linear thermal expansion coefficient of the substrate 20 is about 15 ppm / ° C. and the linear thermal expansion coefficient of the element is about 3 ppm / ° C., the substrate 20 is contracted from the element 10. First, the fourth conductor 38 is solidified near the melting point of the fourth conductor 38 to form a strong bond with the third conductor 36. At this time, the second conductor 34 is still melted and in a state of high fluidity. Thereafter, in the vicinity of the melting point of the second conductor 34, the second conductor 34 is solidified to form a strong bond between the second conductor 34, the first conductor 32, and the third conductor 36. As described above, since the second conductor 34 is solidified at a low temperature, there is no warpage of the substrate 20 and the second conductivity is reduced in a state where the thermal stress caused by the difference in thermal expansion coefficient between the substrate 20 and the element 10 is small. The body 34 solidifies. Therefore, thermal stress can be relaxed by the second conductor 34. Thus, in the cooling process, the entire bump 30 does not solidify at the same speed, but solidifies after a time difference. For this reason, the bump 30 can follow the warp of the substrate 20 in the cooling process (that is, the stress relaxation action works), and suppresses the occurrence of peeling or / and cracking in the bump 30. Further, the bump 30 can follow the difference in contraction between the substrate 20 and the element 10 due to the difference in thermal expansion coefficient, and suppresses peeling or / and cracking in the bump 30.

  2D to 3B of the first embodiment, the example in which the second conductor 34 relaxes the warpage of the substrate 20 has been described. As shown in FIGS. 9A to 9C, the thermal stress caused by the difference in thermal expansion coefficient between the element 10 and the substrate 20 can be relaxed by using the second conductor 34.

  When the cross-sectional SEM (Scanning electron microscope) observation of the bump 30 was performed on the semiconductor device produced using Example 2, there was no contact between the adjacent bumps 30 and no cracks or peeling in the bumps 30 were observed. It was. Furthermore, a temperature cycle test of −25 ° C. to 125 ° C. was performed. Even after 1000 cycles, the electrical resistance value of the bump 30 did not change from the initial value. As described above, according to the second embodiment, the second conductor 34 is provided as a thermal stress relaxation layer in the central portion of the bump 30, whereby the bump 30 can be highly integrated, and the separation and cracking of the bump can be prevented. I was able to suppress it.

  In Example 2, the composition ratio of Sn—Bi that forms the second conductor 34, Sn—Ag—Cu that forms the third conductor 36, and Sn—Zn that forms the fourth conductor 38 is the purpose. The melting point can be arbitrarily set. For example, the melting point of the second conductor 34 can be in the range of 175 ° C. to 139 ° C. by setting the Bi content in the range of 40 wt% to 57 wt% as the second conductor 34.

In FIG. 5D of the second embodiment, the second conductor 34 can be formed using In. In can be formed using electroless plating or electrolytic plating. The electroless plating conditions and the electrolytic plating conditions are as follows.
Electroless plating conditions Plating solution composition Trisodium citrate 0.17 mol / L
Nitrilotriacetic acid trisodium 0.2 mol / L
Indium sulfate 0.08mol / L
Titanium sulfate (III) 0.02 mol / L
Plating conditions Bath temperature 50 ℃
Plating time 8 minutes Electrolytic plating conditions Plating solution composition Indium sulfate 60g / L
Methanesulfonic acid 30g / L
Imidazole-epichlorohydrin copolymer 100 g / L
Plating conditions Anode metal Pt
Current density 10 / dm ²
Plating time 7 minutes

  The melting point of In is 155 ° C., and can be used as a relaxation layer in the same manner as Sn—Bi.

  Example 3 is an example in which the element is a semiconductor element and the substrate is a laminated substrate. FIG. 10 is a cross-sectional view of the semiconductor device 102 according to the third embodiment. FIG. 11 is an enlarged view of region B in FIG. As shown in FIGS. 10 and 11, a multilayer wiring layer 80 is formed on the element substrate 11 (lower in FIG. 10). The multilayer wiring layer 80 is formed by an insulating film 72, a wiring 74 formed in the insulating film 72, and a through electrode 76 that vertically penetrates the insulating film 72. The insulating film 72 is made of, for example, silicon oxide. The wiring 74 and the through electrode 76 are made of a metal such as Cu, for example. An electrode pad 12 is formed under the multilayer wiring layer 80. A bump 30 is formed under the electrode pad 12, and a protective film 16 is formed so as to cover the electrode pad 12. The protective film 16 is an insulating film such as a polyimide film.

  As the insulating substrate 21, insulating layers 21a to 21d such as glass epoxy resin are laminated. A wiring 25 is formed between the insulating layers 21a to 21d. In addition, a via wiring 26 that penetrates the insulating layers 21a to 21d vertically is formed. A wiring electrode 22 is formed on the upper surface of the insulating substrate 21. Bumps 30 are formed on the wiring electrodes 22. A solder resist 28 is formed between the wiring electrodes 22. The solder resist 28 is an insulating film such as an epoxy resin. The solder resist 28 suppresses a short circuit between the wiring electrodes 22. A pad 23 is formed on the lower surface of the insulating substrate 21. A solder ball 41 is formed under the pad 23. The wiring 25, the via wiring 26, and the wiring electrode 22 are formed of a metal film such as Cu, for example.

  The bump 30 is formed by the first conductor 32, the second conductor 34, the third conductor 36, and the fourth conductor 38 as in the first and second embodiments. An underfill material 40 is provided between the element 10 and the substrate 20. The underfill material 40 suppresses foreign matters and the like from being mixed between the element 10 and the substrate 20. The element 10 is sealed with a sealing resin 42. The sealing resin 42 is a resin such as an epoxy resin, for example. As described above, in the semiconductor device 102 in which the semiconductor element is flip-chip mounted on the circuit board, the bumps 30 similar to those in the first and second embodiments can be used.

  In Examples 1 to 3, the example in which the first conductor 32 is bonded to the substrate 20 and the fourth conductor 38 is bonded to the element 10 has been described. However, the fourth conductor 38 is bonded to the substrate 20 and the element 10 may be joined to the first conductor 32.

  Example 4 is an example of an electronic device in which the semiconductor device according to Example 4 is mounted. FIG. 12 is a cross-sectional view of the electronic device according to the fourth embodiment. The semiconductor device 102 according to the third embodiment is mounted on the motherboard 88 of the electronic device 103. The semiconductor device 102 is the semiconductor device of FIG. As in the fourth embodiment, the semiconductor device according to the first to third embodiments can be mounted on an electronic device.

The following additional remarks are disclosed regarding the embodiment including Examples 1 to 4.
Appendix 1:
An element, a substrate, a first conductor, a second conductor formed on the first conductor, a third conductor formed on the second conductor, and the third conductor A fourth conductor formed on the substrate, wherein one of the first conductor and the fourth conductor is joined to the element, and the other of the first conductor and the fourth conductor is A bump bonded to the substrate and electrically connecting the element and the substrate, wherein the first conductor and the third conductor are more than the second conductor and the fourth conductor, respectively. A semiconductor device having a high melting point, wherein the fourth conductor has a higher melting point than the second conductor.
Appendix 2:
The semiconductor device according to appendix 1, wherein the first conductor has a higher melting point than the third conductor.
Appendix 3:
The semiconductor device according to appendix 1 or 2, wherein the second conductor has the smallest width among the bumps.
Appendix 4:
The second conductor includes Sn and Bi or includes In, the third conductor includes Sn, Ag, and Cu, and the fourth conductor includes Sn and Zn. The semiconductor device according to any one of appendices 1 to 3.
Appendix 5:
5. The semiconductor device according to any one of appendices 1 to 4, wherein a width of the first conductor on the second conductor side is smaller than the element or the substrate side.
Appendix 6:
6. The semiconductor device according to any one of appendices 1 to 5, wherein a width of the fourth conductor on the third conductor side is smaller than the element or the substrate side.
Appendix 7:
The semiconductor device according to appendix 5, wherein the width of the second conductor is the same as the width of the first conductor on the second conductor side.
Appendix 8:
Forming a first conductor on one of the element and the substrate;
Forming a second conductor on the first conductor;
Forming a third conductor on the second conductor;
Forming a fourth conductor having a melting point higher than that of the second conductor on the other of the element and the substrate;
The first conductor, the second conductor, the third conductor, and the fourth conductor are less than the melting points of the first conductor and the third conductor, and the second conductor and And a step of heating to a temperature equal to or higher than the melting point of the fourth conductor.
Appendix 9:
An electronic device comprising the semiconductor device according to any one of appendices 1 to 6.

10 element 20 substrate 30 bump 32 first conductor 34 second conductor 36 third conductor 38 fourth conductor

Claims (6)

Forming a first conductor on one of the element and the substrate;
Forming a second conductor on the first conductor;
Forming a third conductor on the second conductor;
Forming a fourth conductor having a melting point higher than that of the second conductor on the other of the element and the substrate;
In a state where the first conductor, the second conductor, and the third conductor are bonded to one of the element and the substrate, and the fourth conductor is connected to the other of the element and the substrate, The third conductor and the fourth conductor are heated to a temperature not higher than the melting points of the first conductor and the third conductor and not lower than the melting points of the second conductor and the fourth conductor. And a step of bonding the semiconductor device. The method for manufacturing a semiconductor device according to claim 1, wherein the first conductor has a higher melting point than the third conductor. The second conductor is made of Sn-Bi or In,
The third conductor is made of Sn-Ag-Cu,
Said fourth conductors, the method of manufacturing a semiconductor device according to claim 1 or 2, wherein the formed of Sn-Zn. 4. The step of bonding the third conductor and the fourth conductor, wherein the second conductor is not alloyed with the first conductor and the third conductor . A manufacturing method of a semiconductor device given in any 1 paragraph . Elements,
A substrate,
A first conductor; a second conductor formed on the first conductor; a third conductor formed on the second conductor; and a fourth conductor formed on the third conductor. A conductor, wherein one of the first conductor and the fourth conductor is bonded to the element, and the other of the first conductor and the fourth conductor is bonded to the substrate, A bump for electrically connecting the element and the substrate;
Comprising
The first conductor and the third conductor have a higher melting point than the second conductor and the fourth conductor, the fourth conductor has a higher melting point than the second conductor,
The second conductor is made of Sn-Bi or In,
The third conductor is made of Sn-Ag-Cu,
The semiconductor device, wherein the fourth conductor is made of Sn-Zn. An electronic device comprising the semiconductor device according to claim 5 .

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