KR100876965B1 - Chip pick-up tool for manufacturing semiconductor package - Google Patents

Chip pick-up tool for manufacturing semiconductor package Download PDF

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Publication number
KR100876965B1
KR100876965B1 KR1020070080444A KR20070080444A KR100876965B1 KR 100876965 B1 KR100876965 B1 KR 100876965B1 KR 1020070080444 A KR1020070080444 A KR 1020070080444A KR 20070080444 A KR20070080444 A KR 20070080444A KR 100876965 B1 KR100876965 B1 KR 100876965B1
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chip
adsorption
tool
pick
semiconductor package
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KR1020070080444A
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Korean (ko)
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김윤주
정지영
성경술
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앰코 테크놀로지 코리아 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/677—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations
    • H01L21/67703—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations between different workstations
    • H01L21/67712—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations between different workstations the substrate being handled substantially vertically
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/677—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations
    • H01L21/67703—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations between different workstations
    • H01L21/67721—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations between different workstations the substrates to be conveyed not being semiconductor wafers or large planar substrates, e.g. chips, lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6838—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping with gripping and holding devices using a vacuum; Bernoulli devices
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K13/00—Apparatus or processes specially adapted for manufacturing or adjusting assemblages of electric components
    • H05K13/04—Mounting of components, e.g. of leadless components
    • H05K13/0404—Pick-and-place heads or apparatus, e.g. with jaws
    • H05K13/0408—Incorporating a pick-up tool

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)

Abstract

A chip pick-up tool for manufacturing semiconductor package is provided to a void between a chip mounting area and the substrate by improving the structure of the semiconductor chip. A semiconductor package for manufacture chip pickup tool(130) is composed of a pick-up body(230) and an absorbing body(210). A pick-up body is connected to vacuum absorbing unit which is formed in the lower part of the pick-up body so that chip is absorbed to the absorbing body. The absorbing body is made of the porous member where a plurality of minute adsorption holes is formed. An expansion hole is formed inside of the absorbing body, and the space of the expansion hole becomes narrow in outside direction. The expansion hole is connected to the compression presentation unit providing the compressed air.

Description

반도체패키지 제조용 칩 픽업툴{Chip pick-up tool for manufacturing semiconductor package}Chip pick-up tool for manufacturing semiconductor package

본 발명은 반도체패키지 제조용 칩 픽업툴에 관한 것으로서, 더욱 상세하게는 웨이퍼 상태의 개개 반도체 칩을 섭스트레이트의 칩부착영역으로 이송시켜 부착시키는 수단인 칩 픽업툴의 구조를 개선하여, 섭스트레이트의 칩부착영역과 칩의 저면 사이에 보이드(void)가 발생되는 것을 방지할 수 있도록 한 반도체패키지 제조용 칩 픽업툴에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a chip pick-up tool for manufacturing a semiconductor package, and more particularly, to improve the structure of the chip pick-up tool, which is a means for transferring individual semiconductor chips in a wafer state to a chip attaching region of a substrate, thereby providing a chip of the substrate. The present invention relates to a chip pick-up tool for manufacturing a semiconductor package to prevent voids from occurring between an attachment region and a bottom of a chip.

일반적으로 반도체패키지는 웨이퍼에서 낱개의 반도체 칩을 소잉(sawing)하여 분리하는 소잉 단계와, 소잉된 낱개의 반도체 칩을 섭스트레이트(substrate) 위에 액상 에폭시(epoxy)로 접착하는 칩 어태치(die attach) 단계와, 반도체 칩(=다이)과 섭스트레이트를 도전성 와이어로 본딩하는 와이어 본딩(wire bonding) 단계와, 반도체 칩, 도전성 와이어 등을 봉지재로 성형하는 밀봉 단계 등으로 이루어져 있다.In general, a semiconductor package includes a sawing step of sawing and separating individual semiconductor chips from a wafer, and a chip attach for attaching each of the sawed semiconductor chips with a liquid epoxy onto a substrate. ), A wire bonding step of bonding the semiconductor chip (= die) and the substrate with a conductive wire, and a sealing step of molding the semiconductor chip, the conductive wire, or the like into an encapsulant.

상기 칩을 섭스트레이트의 칩부착영역에 부착하기 위한 접착수단은 반도체 패키지의 종류에 따라 칩부착영역에 직접 도포되기도 하지만, 접착수단의 일종인 접착필름(film adhesive)이 웨이퍼 상태에서 그 저면에 미리 부착되기도 한다.Although the adhesive means for attaching the chip to the chip attaching region of the substrate is directly applied to the chip attaching region according to the type of semiconductor package, a film adhesive, which is a kind of bonding means, is formed on the bottom surface of the wafer in advance. Sometimes attached.

즉, 상기 웨이퍼의 저면에 접착수단의 일종인 접착필름이 미리 부착된 상태에서 웨이퍼에 대한 소잉 단계가 진행되면, 접착필름도 개개 칩의 크기에 맞게 소잉된다.That is, when the sawing step is performed on the wafer in a state in which the adhesive film, which is a kind of adhesive means, is attached to the bottom of the wafer in advance, the adhesive film is sawed according to the size of the individual chips.

따라서, 웨이퍼 소잉 단계후, 섭스트레이트의 칩부착영역에 대한 칩 부착 공정을 위하여 개개의 칩 저면에 접착필름이 미리 부착된 상태가 된다.Therefore, after the wafer sawing step, the adhesive film is previously attached to the bottom of each chip for the chip attaching process to the chip attaching region of the substrate.

다음으로, 위와 같이 소잉 구비된 개개 칩을 칩 픽업툴을 이용하여 들어 올린 다음, 섭스트레이트의 칩부착영역에 대한 칩 부착 단계가 진행되는 바, 상기 접착필름이 섭스트레이트의 칩부착영역에 먼저 부착되어 칩의 부착이 이루어지게 된다.Next, after raising the individual chips provided as sawing as above using a chip pick-up tool, a chip attaching step is performed on the chip attaching region of the substrate, and the adhesive film is first attached to the chip attaching region of the substrate. The chip is attached.

이러한 칩 어태치 공정을 거치는 반도체패키지는 근래 크기를 증가시키지 않으면서도 다기능 및 고집적화를 이루기 위해, 섭스트레이트 위에 다수의 반도체 칩을 수직 방향으로 스택(stack)하는 기술이 개발되고 있다. In recent years, semiconductor packages undergoing the chip attach process have been developed to stack a plurality of semiconductor chips vertically on a substrate in order to achieve multifunction and high integration without increasing the size.

이와 같이, 반도체 패키지는 낮은 개발비용으로 칩을 적층하여 그 집적도를 높이고자 하는 경향이 있고, 이에 따라 주어진 패키지의 한정된 공간에 더 많은 칩을 적층하기 위해서 섭스트레이트에 접착되는 칩이 점점 얇아 지고 있다.As such, semiconductor packages tend to stack chips at a low development cost and increase their density, and as a result, chips bonded to substrates in order to stack more chips in a limited space of a given package are becoming thinner. .

이하 첨부 도면을 참조하여 종래 반도체 칩 픽업툴로 얇은 칩을 분리 및 부착시키는 경우 발생하는 문제점을 살펴보기로 한다.Hereinafter, with reference to the accompanying drawings will be described a problem that occurs when detaching and attaching a thin chip with a conventional semiconductor chip pickup tool.

첨부한 도 1a 및 도 1b는 종래 반도체 칩 픽업툴에 의해 반도체 칩이 장착되는 도면이다.1A and 1B are diagrams in which a semiconductor chip is mounted by a conventional semiconductor chip pickup tool.

반도체 칩 픽업툴의 칩 부착 공정은 상기 칩 픽업 툴의 저면에 칩이 흡착되는 단계와, 흡착된 칩을 섭스트레이트의 칩부착영역으로 픽업하여 이송하는 단계와, 픽업툴이 칩을 소정의 압으로 가압하여 칩부착영역에 칩을 부착시키는 단계로 진행된다.The chip attaching process of the semiconductor chip pick-up tool includes the steps of adsorbing the chip to the bottom surface of the chip pick-up tool, picking up and transporting the adsorbed chip to the chip attaching area of the substrate, and the pick-up tool transferring the chip to a predetermined pressure. Pressing proceeds to attach the chip to the chip attachment region.

상기에서 설명한 바와 같이 고집적화를 위해 얇은 두께로 형성되는 칩(100)은 플렉서블(flexible)한 특성이 있어 흡착 단계에서 칩(100)이 칩 픽업툴(130)에 흡착되는 경우 칩(100)의 형상은 칩 픽업툴(130)의 흡착부(120) 저면에 밀착되는 구조로 형성된다. As described above, the chip 100 formed in a thin thickness for high integration has a flexible characteristic, so that the shape of the chip 100 when the chip 100 is adsorbed to the chip pick-up tool 130 in the adsorption step Is formed in a structure in close contact with the bottom surface of the adsorption portion 120 of the chip pick-up tool 130.

이에, 첨부한 도 1a에 도시된 종래의 칩 픽업툴(130)은 그 흡착부(120)가 평평한 구조로 되어 있는 바, 흡착단계에서 칩(100)을 눌러주는 가압력이 전체 면적에 고르게 작용하여 흡착부(120)의 흡착력이 증대됨으로써, 칩 픽업툴(130)의 흡착공정이 용이하게 이루어진다.Accordingly, in the conventional chip pickup tool 130 shown in FIG. 1A, the adsorption part 120 has a flat structure, and thus the pressing force for pressing the chip 100 in the adsorption step evenly acts on the entire area. As the adsorption force of the adsorption part 120 is increased, the adsorption process of the chip pick-up tool 130 is easily performed.

또한, 상기 칩(100)을 섭스트레이트(110)에 접착시키는 부착단계에서도 상기 반도체 칩 픽업툴(130)의 흡착부(120) 형상은 평평한 구조로 유지되어 이 흡착부에 부착된 칩 역시 흡착부에 밀착되는 평평한 구조로 형성된다.In addition, even in the attaching step of adhering the chip 100 to the substrate 110, the shape of the adsorption part 120 of the semiconductor chip pickup tool 130 is maintained in a flat structure so that the chip attached to the adsorption part is also the adsorption part. It is formed into a flat structure that is in close contact with it.

그러나, 이와같이 부착단계에서 상기 흡착부 및 칩이 평평한 구조로 형성되는 경우 도 1a에서 도시한 바와 같이 섭스트레이트(110) 중앙 위치(접착필름의 중앙부와 칩부착영역의 중앙부 사이)의 공기가 외부쪽으로 빠져나가지 못함으로써, 결국 중앙 위치에 보이드(150)가 발생되는 문제점이 있었다.However, when the adsorption unit and the chip are formed in a flat structure in the attaching step as described above, air at the center of the substrate 110 (between the center of the adhesive film and the center of the chip attaching region) toward the outside as shown in FIG. 1A. By not exiting, there was a problem that the void 150 is generated in the center position in the end.

또한, 도 1b에서 도시한 바와 같이 상기 칩이 접착필름(140)에 의해 피부착 칩(160)에 적층되는 경우 부착칩(100)과 접착필름(140)의 사이 또는 접착필름(140)과 피부착칩(160) 사이에도 상기와 같은 평평한 구조로 인해 보이드(150)가 발생하는 문제점이 있었다.In addition, as shown in FIG. 1B, when the chip is stacked on the adhesion chip 160 by the adhesive film 140, the adhesion chip 100 and the adhesive film 140 are interposed therebetween, or the adhesive film 140 and the blood. There was a problem in that the voids 150 occur due to the flat structure as described above between the attachment chip 160.

따라서, 이와 같이 칩(100) 또는 접착필름(140)의 저면 중앙에 보이드(150)가 형성되는 경우 칩(100)의 부착 및 적층 작업의 효율성이 떨어지고, 이러한 보이드(150)가 형성되지 않도록 하는 최적의 조건을 설계하는데 많은 시간이 소요되는 문제점이 있었다.Therefore, when the void 150 is formed in the center of the bottom surface of the chip 100 or the adhesive film 140 as described above, the efficiency of attaching and laminating the chip 100 is reduced, and such voids 150 are not formed. There was a problem that it takes a lot of time to design the optimum conditions.

본 발명은 상기와 같은 문제점을 해결하기 위하여 안출한 것으로서, 반도체 칩이 부착되는 픽업몸체 하부의 다공성 재질로 이루어진 흡착부에 일정온도 이상에서 그 구조가 변형되는 형상기억 합금이 포함되거나, 진공압을 제공하는 진공제공수단과 연결되어 진공상태에서 외측부가 상승하는 진공홀이 형성되거나, 또는 압축공기를 제공하는 압축제공수단과 연결되어 팽창상태에서 중앙부가 팽창하는 팽창홀이 형성되어, 칩 부착시에는 흡착부가 칩 방향으로 볼록하게 변형됨으로써, 칩과 섭스트레이트 사이에 보이드가 형성되는 것을 방지시킬 수 있는 반도체패키지 제조용 칩 픽업툴을 제공하는데 그 목적이 있다.The present invention has been made to solve the above problems, the shape memory alloy is deformed at a predetermined temperature or more in the adsorption portion made of a porous material of the lower portion of the pickup body to which the semiconductor chip is attached, or vacuum pressure A vacuum hole is formed in which the outer portion rises in a vacuum state in connection with the providing vacuum providing means, or an expansion hole in which the center portion is expanded in the expanded state is formed in connection with the compression providing means providing compressed air. It is an object of the present invention to provide a chip pick-up tool for manufacturing a semiconductor package which can prevent a void from being formed between the chip and the substrate by convex deformation of the adsorption part in the chip direction.

상기한 목적을 달성하기 위한 본 발명은 진공흡착수단과 연결되는 픽업몸체와, 칩이 흡착되도록 상기 픽업몸체의 하부에 형성되는 흡착부로 구성되는 반도체패키지 제조용 칩 픽업툴에 있어서, In the present invention for achieving the above object is a chip pickup tool for semiconductor package manufacturing comprising a pickup body connected to the vacuum suction means, and the suction portion formed in the lower portion of the pickup body so that the chip is sucked,

상기 흡착부는 다수의 미세 흡착홀이 형성된 다공성 재질로 이루어지고, 일정온도 이상에서 흡착부가 칩방향으로 볼록해지도록 이 흡착부 내부에 형상기억 합금이 내장된 것을 특징으로 한다.The adsorption part is made of a porous material formed with a plurality of fine adsorption holes, characterized in that the shape memory alloy is embedded in the adsorption part so that the adsorption part is convex in the chip direction at a predetermined temperature or more.

또한, 상기 형상기억 합금은 상기 흡착부의 내부에 사각배열 구조, 이선배열 구조 및 엑스자배열 구조 중 어느 하나로 형성되는 것을 특징으로 한다.In addition, the shape memory alloy is characterized in that formed in any one of a rectangular array structure, two-line array structure and X-shaped array structure inside the adsorption portion.

바람직한 다른 구현예로서, 진공흡착수단과 연결되는 픽업몸체와, 칩이 흡착되도록 상기 픽업몸체의 하부에 형성되는 흡착부로 구성되는 반도체패키지 제조용 칩 픽업툴에 있어서,In another preferred embodiment, in the chip pickup tool for semiconductor package manufacturing comprising a pickup body connected to the vacuum suction means, and the suction unit formed in the lower portion of the pickup body to suck the chip,

상기 흡착부는 다수의 미세 흡착홀이 형성된 다공성 재질로 이루어지고, 이 흡착부 내부에는 외측 방향으로 그 공간이 더 넓어지는 진공홀이 형성되고, 이 진공홀은 진공압을 제공하는 진공제공수단과 연결되는 것을 특징으로 한다.The adsorption part is made of a porous material formed with a plurality of fine adsorption holes, and a vacuum hole is formed inside the adsorption part, the space being wider in the outward direction, and the vacuum hole is connected to a vacuum providing means for providing a vacuum pressure. It is characterized by.

바람직한 또 다른 구현예로서, 진공흡착수단과 연결되는 픽업몸체와, 칩이 흡착되도록 상기 픽업몸체의 하부에 형성되는 흡착부로 구성되는 반도체패키지 제조용 칩 픽업툴에 있어서,In another preferred embodiment, in the semiconductor package manufacturing chip pick-up tool consisting of a pickup body connected to the vacuum suction means, and the suction portion formed in the lower portion of the pickup body so that the chip is sucked,

상기 흡착부는 다수의 미세 흡착홀이 형성된 다공성 재질로 이루어지고, 이 흡착부 내부에는 외측 방향으로 그 공간이 더 좁아지는 팽창홀이 형성되고, 이 팽창홀은 압축공기를 공급하는 압축제공수단과 연결되는 것을 특징으로 한다.The adsorption part is made of a porous material formed with a plurality of fine adsorption holes, the expansion hole is formed inside the adsorption portion is narrower in the outer direction, the expansion hole is connected to the compression providing means for supplying compressed air It is characterized by.

이상에서 본 바와 같이 본 발명에 따른 반도체패키지 제조용 칩 픽업툴은 다음과 같은 효과를 제공한다.As described above, the chip pick-up tool for manufacturing a semiconductor package according to the present invention provides the following effects.

우선, 반도체 칩이 픽업툴에 의해 웨이퍼로부터 이탈되는 경우 픽업툴의 흡착부가 평평한 구조로 형성되어 칩을 들어올리는 것이 용이하고, First, when the semiconductor chip is separated from the wafer by the pick-up tool, the adsorption part of the pick-up tool is formed in a flat structure so that it is easy to lift the chip.

또한, 픽업툴에 흡착된 반도체 칩이 섭스트레이트에 접착되는 경우 흡착부가 칩방향으로 볼록하게 형성되어 칩의 중앙부가 섭스트레이트에 먼저 눌림으로써, 흡착부의 평평한 구조에서 칩과 섭스트레이트 사이에 형성되는 보이드의 발생이 방지되고,In addition, when the semiconductor chip adsorbed on the pickup tool is adhered to the substrate, the adsorption portion is convexly formed in the chip direction, and the center portion of the chip is pressed on the substrate first, thereby forming a void formed between the chip and the substrate in the flat structure of the adsorption portion. The occurrence of

따라서, 픽업툴이 칩을 섭스트레이트에 접착시키는 본딩 작업의 작업성이 증대되고, 종래 보이드를 최소화시키기 위해 픽업툴의 최적조건을 설계하는데 소요되던 시간을 줄일 수 있으며,Therefore, the workability of the bonding operation in which the pick-up tool adheres the chip to the substrate is increased, and the time required for designing the optimum condition of the pick-up tool to minimize the voids can be reduced.

덧붙여, 반도체 칩이 부착되는 흡착부의 흡착면은 다수의 흡착홀이 형성되어 흡착부의 흡착력이 향상되는 효과가 있다.In addition, the adsorption surface of the adsorption part to which the semiconductor chip is attached has an effect that a plurality of adsorption holes are formed and the adsorption force of the adsorption part is improved.

이하, 본 발명의 바람직한 실시예를 첨부도면을 참조로 상세하게 설명한다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

첨부한 도 2a는 본 발명의 일실시예에 따른 반도체패키지 제조용 칩 픽업툴의 개시도이고, 도 2b은 도 2a의 작동 변형도이고, 도 2c는 도 2a의 실시예 개시도이다.2A is a view illustrating a chip pickup tool for manufacturing a semiconductor package according to an embodiment of the present invention, FIG. 2B is an operational variation of FIG. 2A, and FIG. 2C is an embodiment view of FIG. 2A.

도 2a에서 도시한 바와 같이, 반도체 칩 픽업툴(130)은 칩(100)을 이동시키는 픽업몸체(230) 하부에 흡착부(210)가 형성되고, 이 흡착부(210)의 측면에는 흡착부(210)를 지지하는 홀더(200)가 형성된다.As shown in FIG. 2A, in the semiconductor chip pickup tool 130, an adsorption part 210 is formed under the pickup body 230 for moving the chip 100, and an adsorption part is formed on the side of the adsorption part 210. Holder 200 for supporting 210 is formed.

여기서, 상기 칩(100)은 웨이퍼 마운트 테이프에서 이탈되는 흡착단계에서 흡착부(210)의 흡입에 의해 상기 픽업몸체(230)의 하부에 형성된 흡착부(210)에 달라 붙게 되고, 흡착부(210)에 부착된 칩(100)은 칩 픽업툴(130)에 의해 이송된후 접착제 또는 접착필름(140)에 의해 섭스트레이트(110) 상에 접착된다.Here, the chip 100 is attached to the adsorption unit 210 formed on the lower portion of the pickup body 230 by suction of the adsorption unit 210 in the adsorption step that is separated from the wafer mount tape, the adsorption unit 210. The chip 100 attached to the) is transferred onto the substrate 110 by an adhesive or an adhesive film 140 after being transferred by the chip pickup tool 130.

본 발명에 따른 일 실시예에 있어서, 상기 흡착부(210)는 도 2c에서 도시한 바와 같이 전체적으로 균일하게 다수의 미세 흡착홀(250)이 형성된 다공성 재질로 이루어져 흡착 단면적이 넓어짐으로써, 이 흡착부(210)에 칩이 부착되는 흡착력이 향상되고, 이 흡착부(210)의 저면은 공정조건에 따라 그 구조가 용이하게 변형되도록 탄력적인 재질로 이루어지는 것이 바람직하다.In one embodiment according to the present invention, the adsorption unit 210 is made of a porous material formed with a plurality of fine adsorption holes 250 uniformly as shown in FIG. Adsorption force to which the chip is attached to 210 is improved, and the bottom of the adsorption portion 210 is preferably made of an elastic material so that its structure is easily deformed according to the process conditions.

또한, 상기 흡착부(210)는 칩(100)을 흡착시키는 별도의 진공흡착수단(350)과 연결되어 이 진공흡착수단(350)이 흡착부(210)에 진공압력을 제공함으로써, 미세 흡착홀(250)을 통해 작용하는 진공압력에 의해 칩이 흡착부에 흡착되도록 한다.In addition, the adsorption unit 210 is connected to a separate vacuum adsorption means 350 for adsorbing the chip 100 so that the vacuum adsorption means 350 provides a vacuum pressure to the adsorption unit 210, thereby providing fine adsorption holes. The chip is attracted to the adsorption unit by the vacuum pressure acting through the 250.

덧붙여, 도 2a에서 도시한 바와 같이 상기 흡착부(210)는 내부에 형상기억 합금(220)이 형성되어 일정온도 이하에서는 칩(100)이 부착되는 흡착면이 평평한 구조를 이루고, 일정온도 이상에서는 이 흡착면이 칩방향으로 볼록하게 형성된다.In addition, as shown in FIG. 2A, the adsorption part 210 has a shape memory alloy 220 formed therein so that the adsorption surface to which the chip 100 is attached has a flat structure at a predetermined temperature or less. This suction surface is formed convexly in the chip direction.

따라서, 상기 칩이 픽업툴(130)에 의해 웨이퍼로부터 이탈되는 흡착단계에서 상기 흡착부(210)는 일정온도 이하에 노출되어 평평한 구조를 형성함으로써, 이 흡착부(210)의 가압력이 얇은 두께의 평평한 칩(100) 전면에 작용하여 칩의 흡착이 용이하게 이루어진다. Therefore, in the adsorption step in which the chip is separated from the wafer by the pickup tool 130, the adsorption unit 210 is exposed to a predetermined temperature or less to form a flat structure, whereby the pressing force of the adsorption unit 210 has a thin thickness. The adsorption of the chip is made easily by acting on the front surface of the flat chip (100).

이후, 상기 흡착부(210)에 흡착된 칩(100)이 칩 픽업툴(130)에 의해 이송되어 섭스트레이트(110) 또는 다른 칩에 접착되는 경우 접착필름(140)의 활성화를 위해 흡착부(210)가 가열되고, 이에 따라 도 2b에서 도시한 바와 같이 흡착부(210) 내부의 형상기억 합금(220)이 일정온도 이상이 되어, 형상기억 합금(220)이 포함된 흡착부(210)는 미리 기억된 볼록 형상으로 변형된다.Subsequently, when the chip 100 adsorbed to the adsorption unit 210 is transferred by the chip pick-up tool 130 and adhered to the substrate 110 or another chip, the adsorption unit may be activated to activate the adhesive film 140. 210 is heated, and as shown in FIG. 2B, the shape memory alloy 220 inside the adsorption unit 210 becomes a predetermined temperature or more, so that the adsorption unit 210 including the shape memory alloy 220 is formed. It is deformed into a convex shape stored in advance.

여기서, 상기 접착필름(140)이 활성화되기 위해서는 이 접착필름이 흡착부(210)에 부착된 칩 저면에 부착되어 칩이 섭스트레이트(110)에 접착시 용융되도록 별도의 가열장치에 의해 가열되는 것이 바람직하고, 이에 따라 이 접착필름(140)이 부착된 흡착부(210)는 일정온도 이상에 노출된다. Here, in order for the adhesive film 140 to be activated, the adhesive film is attached to the bottom surface of the chip attached to the adsorption unit 210 and heated by a separate heating device so that the chip melts when the chip is adhered to the substrate 110. Preferably, the adsorption part 210 to which the adhesive film 140 is attached is exposed to a predetermined temperature or more.

이와 같은 구조에서 칩(100)의 접착이 이루어지는 경우 칩의 중앙부가 먼저 섭스트레이트(110)에 닿게 되어 중앙의 공기가 외측으로 빠져 나감으로써, 칩과 섭스트레이트(110) 사이에 보이드가 발생되는 것이 방지된다.In this structure, when the chip 100 is bonded, the center portion of the chip first touches the substrates 110 so that the air in the center escapes to the outside, thereby generating voids between the chips and the substrates 110. Is prevented.

여기서, 상기 형상기억 합금(220)이 형상기억 효과를 가지게 하기 위해서는 일정한 열처리가 요구되는데, 이러한 열처리는 형상기억 합금(220)으로 볼록한 구조의 흡착부(210)를 형성하는 고정형상을 만들고, 이 고정된 합금형상을 고온에서 일정시간 노출시키는 것으로 진행된다.In this case, in order to have the shape memory alloy 220 has a shape memory effect, a certain heat treatment is required. This heat treatment creates a fixed shape to form the adsorption part 210 of the convex structure with the shape memory alloy 220. Proceeding by exposing the fixed alloy shape at a high temperature for a certain time.

이러한 열처리가 완료된 상기 형상기억 합금(220)은 일정온도 이상이 되면 열처리 과정에서 고정되었던 형상으로 변형된다.When the heat treatment is completed, the shape memory alloy 220 is deformed to a shape that was fixed in the heat treatment process when a predetermined temperature or more.

상기 일정온도는 접착필름(140)이 가열되는 조건에 따라 섭씨 50도 내외로 설계되는 것이 바람직하고, 상기 형상기억 합금(220)의 재료는 니켈-티타늄 합금 또는 구리-아연-알루미늄 합금으로 사용되는 것이 바람직하다.The predetermined temperature is preferably designed to be around 50 degrees Celsius according to the conditions in which the adhesive film 140 is heated, the material of the shape memory alloy 220 is used as a nickel-titanium alloy or copper-zinc-aluminum alloy It is preferable.

또한, 상기 형상기억 합금(220)이 흡착부(210) 내부에 배치된 구조는 형상기억 합금(220)의 변형에 의해 흡착부(210)가 칩방향으로 볼록해지는 것이 가능하다면, 도 2c에서 도시한 바와 같이 사각배열 구조(a), 이선배열 구조(b) 또는 엑스자배열 구조(c) 어느 것이라도 가능하다.In addition, the structure in which the shape memory alloy 220 is disposed inside the adsorption part 210 may be convex in the chip direction by the deformation of the shape memory alloy 220, as illustrated in FIG. 2C. As described above, any one of the rectangular array structure (a), the bilinear array structure (b), or the X-shaped array structure (c) may be used.

여기서, 상기 사각배열 구조(a)는 일정 온도이상에서 흡착부(210)의 볼록 형상이 정교하고 용이하게 형성될 수는 있으나, 형상기억 합금(220)의 필요량이 증가하여 생산비가 늘어나고, 반면에 이선배열 구조(b) 및 엑스자배열 구조(c)는 합금의 필요량은 감소하지만, 볼록 형상이 정교하게 형성되지 못하는 단점이 있다.Here, the rectangular array structure (a) can be formed in the convex shape of the adsorption portion 210 more than a predetermined temperature and easily, but the required amount of the shape memory alloy 220 increases, while the production cost increases, while The two-line array structure (b) and the X-shaped array structure (c) have a disadvantage in that the amount of alloy is reduced, but the convex shape is not formed precisely.

첨부한 도 3a는 본 발명의 다른 실시예에 따른 반도체패키지 제조용 칩 픽업툴의 개시도이고, 도 3b는 도 3a의 작동 변형도이다.FIG. 3A is a view showing a chip pickup tool for manufacturing a semiconductor package according to another embodiment of the present invention, and FIG. 3B is an operation modified view of FIG. 3A.

본 발명에 따른 다른 바람직한 실시예에 있어서, 도 3a에 도시한 바와 같이 상기 흡착부(210) 내부에는 진공홀(300)이 형성되고, 이 진공홀(300)은 외측에서 픽업몸체(230)를 관통하는 흡입로(320)를 통해 진공제공수단(310)과 연결된다.In another preferred embodiment according to the present invention, as shown in Figure 3a, the vacuum hole 300 is formed inside the suction unit 210, the vacuum hole 300 is the pickup body 230 from the outside It is connected to the vacuum providing means 310 through a through suction passage 320.

또한, 상기 진공홀(300)은 중앙이 흡착부(210)의 하단에 연결된 상태에서 외 곽 방향으로 갈수록 그 공간이 넓게 형성되는바, 이 진공홀(300)의 단면은 도 3a에서 도시한 바와 같이 중앙선을 중심으로 직각 삼각형이 마주보는 형상을 이루는 것이 바람직하다.In addition, the vacuum hole 300 is formed in the center toward the outer direction in the state connected to the lower end of the adsorption unit 210, the space is wider, the cross section of the vacuum hole 300 is shown in Figure 3a As described above, it is preferable to form a shape in which the right triangles face the center line.

이에 따라, 상기 진공제공수단(310)에 의해 상기 진공홀(300)이 진공상태가 되는 경우 도 3b에서 도시한 바와 같이 상기 흡착부(210)는 외측에서 중앙으로 갈수록 그 상승폭이 작아짐으로써, 이 흡착부(210)는 칩 방향으로 볼록한 구조가 형성된다.Accordingly, when the vacuum hole 300 is in a vacuum state by the vacuum providing means 310, as shown in FIG. 3B, the rising width of the adsorption part 210 decreases from the outside to the center, thereby decreasing the rising width. The adsorption part 210 is formed with a convex structure in the chip direction.

이때, 상기 흡착부(210)를 지지하는 홀더(200)는 접착단계에서 칩(100)이 홀더(200)에 걸리지 않도록 흡착부(210)의 외측이 상승하는 폭 만큼 이 흡착부(210)와 단차면(330)을 형성되는 것이 바람직하다.At this time, the holder 200 for supporting the adsorption unit 210 and the adsorption unit 210 as much as the width of the outer side of the adsorption unit 210 is raised so that the chip 100 is not caught in the holder 200 in the bonding step. Preferably, the stepped surface 330 is formed.

따라서, 상기 칩(100)이 웨이퍼 마운팅 테이프로부터 이탈되는 흡착단계에서 평평한 구조로 형성된 흡착부(210)는 이탈된 칩이 섭스트레이트(110)에 접착되는 접착단계에서 진공제공수단(310)의 진공압에 의해 칩방향으로 볼록해짐으로써, 형상기억 합금(220)이 형성된 실시예와 마찬가지로 보이드가 발생되는 것을 방지할 수 있다.Therefore, the adsorption part 210 formed in a flat structure in the adsorption step in which the chip 100 is separated from the wafer mounting tape has a vacuum of the vacuum providing means 310 in the bonding step in which the detached chip is bonded to the substrate 110. By being convex in the chip direction by pneumatic pressure, it is possible to prevent the generation of voids as in the embodiment in which the shape memory alloy 220 is formed.

첨부한 도 4a는 본 발명의 또 다른 실시예에 따른 반도체패키지 제조용 칩 픽업툴의 개시도이고, 도 4b는 도 4a의 작동 변형도이다.4A is a view illustrating a chip pickup tool for manufacturing a semiconductor package according to still another embodiment of the present invention, and FIG. 4B is an operation modified view of FIG. 4A.

본 발명에 따른 또 다른 바람직한 실시예에 있어서, 도 4a에 도시한 바와 같이 상기 흡착부(210) 내부에는 팽창홀(400)이 형성되고, 이 팽창홀(400)은 외측에서 픽업몸체(230)를 관통하는 압축로(420)를 통해 압축제공수단(410)과 연결된다.In another preferred embodiment according to the present invention, as shown in Figure 4a, the expansion hole 400 is formed inside the suction unit 210, the expansion hole 400 is the pickup body 230 from the outside It is connected to the compression providing means 410 through the compression passage 420 through the.

또한, 상기 팽창홀(400)은 상기 진공홀(300)과는 반대로 중앙의 공간이 넓게 형성되어 외측으로 갈수록 그 공간이 좁아지게 되는바, 이 팽창홀의 단면은 도 4a에서 도시한 바와 같이 중앙선을 중심으로 대칭되는 이등변 삼각형 형상으로 이루어지는 것이 바람직하다.In addition, the expansion hole 400 has a central space wider as opposed to the vacuum hole 300 so that the space becomes narrower toward the outside, the cross section of the expansion hole as shown in Figure 4a It is preferred to have an isosceles triangle shape that is symmetric about the center.

이에 따라, 상기 압축제공수단(410)에 의해 상기 팽창홀(400)로 압축공기가 공급되는 경우 도 4b에서 도시한 바와 같이 상기 흡착부(210)는 공간이 넓게 형성되는 중앙의 하강폭이 커지고, 외측으로 갈수록 그 하강폭이 작아짐으로써, 칩 방향으로 볼록한 구조가 형성된다.Accordingly, when compressed air is supplied to the expansion hole 400 by the compression providing means 410, as shown in FIG. 4B, the adsorption portion 210 has a large descending width at the center of which the space is wide. As the fall width becomes smaller toward the outside, a convex structure is formed in the chip direction.

따라서, 상기 칩(100)이 웨이퍼로부터 이탈시 평평한 구조로 형성된 흡착부(210)는 이탈된 칩이 섭스트레이트(110)에 접착되는 접착단계에서 압축제공수단(410)의 압축공기에 의해 칩방향으로 볼록해짐으로써, 다른 실시예와 마찬가지로 보이드가 발생되는 것을 방지할 수 있다.Therefore, the adsorption part 210 having a flat structure when the chip 100 is detached from the wafer has a chip direction by the compressed air of the compression providing means 410 in the bonding step in which the detached chip is bonded to the substrate 110. By convex, the voids can be prevented from occurring as in the other embodiments.

여기서, 각 실시예에서는 칩(100)의 접착단계에서 상기 흡착부(210)의 형상이 변형되므로 상기 흡착부(210)의 저면은 팽창 및 수축이 용이하게 이루어지는 탄력적인 재질로 이루어지는 것이 바람직하다.Here, in each embodiment, since the shape of the adsorption part 210 is deformed in the bonding step of the chip 100, the bottom surface of the adsorption part 210 is preferably made of an elastic material that facilitates expansion and contraction.

그리고, 일 실시예에서 설명한 바와 같이 마찬가지로 상기 흡착부(210)는 다수의 미세 흡착홀(250)이 형성된 다공성 재질로 이루어지고, 이 흡착부(210)는 진공흡착수단(350)에 의해 진공압력이 제공됨으로써, 흡착홀(250)을 통해 제공되는 진공압력에 의해 칩(100)이 흡착부(210)에 부착되는 것이 바람직하다.In addition, as described in the embodiment, the adsorption part 210 is made of a porous material having a plurality of micro adsorption holes 250, and the adsorption part 210 is vacuum pressure by the vacuum adsorption means 350. By this, it is preferable that the chip 100 is attached to the adsorption part 210 by the vacuum pressure provided through the adsorption hole 250.

이러한 바람직한 실시예에 있어서 상기 진공제공수단(310) 및 압축제공수 단(410)은 흡착단계에서는 작동하지 않아 흡착부(210)의 흡착면이 평평한 구조로 형성되고, 칩의 접착시 별도의 제어장치 또는 조작에 의해 작동하여 흡착부(210)의 구조가 볼록형상으로 변형된다.In this preferred embodiment, the vacuum providing means 310 and the compression providing water stage 410 does not work in the adsorption step, so that the adsorption surface of the adsorption part 210 is formed in a flat structure, and when the chip is bonded, separate control is performed. Operated by an apparatus or operation, the structure of the adsorption part 210 is deformed into a convex shape.

이상에서는 본 발명을 특정의 바람직한 실시예에 대하여 도시하고 설명하였으나, 본 발명은 이러한 실시예에 한정되지 않으며, 당해 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 특허청구범위에서 청구하는 본 발명의 기술적 사상을 벗어나지 않는 범위내에서 실시할 수 있는 다양한 형태의 실시예들을 모두 포함한다.While the invention has been shown and described with respect to certain preferred embodiments thereof, the invention is not limited to these embodiments, and has been claimed by those of ordinary skill in the art to which the invention pertains. It includes all the various forms of embodiments that can be carried out without departing from the spirit.

도 1a 및 도 1b는 종래 반도체 칩 픽업툴에 의해 반도체 칩이 장착되는 도면,1A and 1B are views in which a semiconductor chip is mounted by a conventional semiconductor chip pickup tool,

도 2a는 본 발명의 일실시예에 따른 반도체패키지 제조용 칩 픽업툴의 개시도, Figure 2a is a start view of the chip pickup tool for manufacturing a semiconductor package according to an embodiment of the present invention,

도 2b은 도 2a의 작동 변형도, FIG. 2B is an operational variation of FIG. 2A;

도 2c는 도 2a의 실시예 개시도,FIG. 2C is an exemplary view of the embodiment of FIG. 2A; FIG.

도 3a는 본 발명의 다른 실시예에 따른 반도체패키지 제조용 칩 픽업툴의 개시도, 3A is a view showing a chip pickup tool for manufacturing a semiconductor package according to another embodiment of the present invention;

도 3b는 도 3a의 작동 변형도,FIG. 3B is an operational variation of FIG. 3A;

도 4a는 본 발명의 또 다른 실시예에 따른 반도체패키지 제조용 칩 픽업툴의 개시도, 4A is a view illustrating a chip pickup tool for manufacturing a semiconductor package according to still another embodiment of the present invention;

도 4b는 도 4a의 작동 변형도.4B is an operational variant of FIG. 4A.

<도면의 주요부분에 대한 부호의 설명><Description of the symbols for the main parts of the drawings>

100 : 반도체 칩 110 : 섭스트레이트 100 semiconductor chip 110

120, 210 : 흡착부 130 : 칩 픽업툴 140 : 접착필름 200 : 홀더120, 210: adsorption unit 130: chip pick-up tool 140: adhesive film 200: holder

220 : 형상기억 합금 230 : 픽업몸체220: shape memory alloy 230: pickup body

Claims (4)

삭제delete 삭제delete 삭제delete 진공흡착수단과 연결되는 픽업몸체와, 칩이 흡착되도록 상기 픽업몸체의 하부에 형성되는 흡착부로 구성되는 반도체패키지 제조용 칩 픽업툴에 있어서,In the chip pickup tool for manufacturing a semiconductor package consisting of a pickup body connected to the vacuum suction means, and a suction unit formed in the lower portion of the pickup body to suck the chip, 상기 흡착부는 다수의 미세 흡착홀이 형성된 다공성 재질로 이루어지고, 이 흡착부 내부에는 외측 방향으로 그 공간이 더 좁아지는 팽창홀이 형성되고, 이 팽창홀은 압축공기를 공급하는 압축제공수단과 연결되는 것을 특징으로 하는 반도체패키지 제조용 칩 픽업툴.The adsorption part is made of a porous material formed with a plurality of fine adsorption holes, the expansion hole is formed inside the adsorption portion is narrower in the outer direction, the expansion hole is connected to the compression providing means for supplying compressed air Chip pick-up tool for manufacturing a semiconductor package, characterized in that.
KR1020070080444A 2007-08-10 2007-08-10 Chip pick-up tool for manufacturing semiconductor package KR100876965B1 (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101135622B1 (en) * 2009-10-26 2012-04-17 강원대학교산학협력단 Adhesion controllable transfer stamper
US9698117B2 (en) 2014-02-10 2017-07-04 Samsung Electronics Co., Ltd. Die bonding apparatus
KR20210080540A (en) * 2018-10-30 2021-06-30 오스람 옵토 세미컨덕터스 게엠베하 Transfer tool and method for transferring semiconductor chips

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06151366A (en) * 1992-11-06 1994-05-31 Nippon Steel Corp Dry etching apparatus
JPH10583A (en) * 1996-06-11 1998-01-06 Koganei Corp Work holding device
JP2003203964A (en) * 2001-12-21 2003-07-18 Esec Trading Sa Pickup tool for mounting semiconductor chip

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06151366A (en) * 1992-11-06 1994-05-31 Nippon Steel Corp Dry etching apparatus
JPH10583A (en) * 1996-06-11 1998-01-06 Koganei Corp Work holding device
JP2003203964A (en) * 2001-12-21 2003-07-18 Esec Trading Sa Pickup tool for mounting semiconductor chip

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101135622B1 (en) * 2009-10-26 2012-04-17 강원대학교산학협력단 Adhesion controllable transfer stamper
US9698117B2 (en) 2014-02-10 2017-07-04 Samsung Electronics Co., Ltd. Die bonding apparatus
KR20210080540A (en) * 2018-10-30 2021-06-30 오스람 옵토 세미컨덕터스 게엠베하 Transfer tool and method for transferring semiconductor chips
KR102585657B1 (en) 2018-10-30 2023-10-05 에이엠에스-오스람 인터내셔널 게엠베하 Transfer tool and method for transferring semiconductor chips
US12020973B2 (en) 2018-10-30 2024-06-25 Osram Opto Semiconductors Gmbh Transfer tool and method for transferring semiconductor chips

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