KR100861303B1 - Inter voltage generation circuit and semiconductor memory device including the same - Google Patents

Abstract

An internal voltage generation circuit and a semiconductor memory device including the same are provided to prevent a boosted voltage from exceeding a target voltage level by blocking the supply of a source voltage. An internal voltage generation circuit includes a level controller(30) and a charge pumping unit(34). The level controller detects the level of a source voltage and generates a control signal according to the source voltage level. The charge pumping unit generates a boosted voltage by pumping the source voltage in power up and controls rising of the boosted voltage by controlling the supply of the source voltage according to the control signal.

Description

An internal voltage generating circuit and a semiconductor memory device including the same {INTER VOLTAGE GENERATION CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME}

1 is a circuit diagram showing a charge pump unit included in a conventional internal voltage generation circuit.

FIG. 2 is a DC level graph illustrating a relationship between a boosted voltage VPP and a power supply voltage VDD output from the charge pump unit of FIG. 1. FIG.

3 is a block diagram showing an internal voltage generating circuit of the present invention.

4 is a detailed circuit diagram of the level control unit 30 of FIG.

5 is a DC level graph illustrating a relationship between a control signal CTRL output from the level control unit 30 of FIG. 4 and a power supply voltage VDD.

FIG. 6 is a detailed circuit diagram of the charge pump unit 34 of FIG. 3.

FIG. 7 is a DC level graph illustrating a relationship between a boosted voltage VPP and a power supply voltage VDD output from the charge pump unit 34 of FIG. 6.

The present invention relates to a semiconductor memory device of the present invention, and more particularly, to an internal voltage generator circuit for generating an internal voltage using a predetermined voltage and a semiconductor memory device including the same.

In general, semiconductor memory devices make internal power sources having different potentials from external power sources and use them differently according to their purpose. As one of the methods of making an internal power source using an external power source, there is a method of making an internal electric potential higher than the external electric power potential or lower than the ground electric potential by using a charge pump.

Among the internal power supplies generated by charge pumping, power supplies most commonly used in semiconductor memory devices include a boost voltage VPP and a back bias voltage VBB. The boosted voltage VPP is a voltage applied to the gate of the cell transistor, and has a potential higher than the power supply voltage VDD so that there is no loss of cell data when the cell is accessed. The back bias voltage VBB is a voltage applied to the bulk of the cell transistor. It has a potential lower than the external ground voltage VSS to prevent loss of data stored in it.

On the other hand, conventionally, as a circuit for generating the boosted voltage VPP, as shown in FIG. 1, a doubler pump having a good puncture efficiency is mainly used. That is, as shown in FIG. 1, the conventional charge pump circuit pumps the power supply voltage VDD in response to the pumping control signals P1, P2, G1, and G2 to generate a boosted voltage VPP.

In this case, in the conventional charge pump circuit, the boost voltage VPP is supplied to the power supply voltage through the NMOS transistor type diode NM1 when the boost voltage VPP is lower than the power supply voltage VDD in order to prevent latch-up during power-up. Operate to follow the VDD level.

That is, referring to FIG. 2, the boosted voltage VPP at power-up follows the power supply voltage VDD level, and then, at a predetermined point in time, the target level is indicated by the pumping control signals P1, P2, G1, and G2. A 'level). When the level of the power supply voltage VDD rises above the target level of the boosted voltage VPP, the boosted voltage VPP again follows the power supply voltage VDD level.

However, when the power supply voltage VDD rises higher than the target level of the boosted voltage VPP after power-up, for example, when the target level of the boosted voltage VPP is 3.3V and the power supply voltage VDD is 4V, the boosted voltage VPP is an NMOS transistor type. The diode NM1 may have a level higher than the target level.

In this case, the devices using the boosted voltage VPP are applied with the boosted voltage VPP at a level higher than the original target voltage, thereby degrading the reliability of the device. In particular, in the case of a cell transistor receiving the boosted voltage VPP as a gate, when the boosted voltage VPP rises above the target level, there is a problem in that the characteristics of the cell transistor are changed and a defect may occur.

In addition, when it is necessary to make the boost voltage VPP at a level lower than the power supply voltage VDD during a predetermined test among various tests of the memory, the conventional charge pump circuit must control the boost voltage VPP to a level lower than the power supply voltage VDD.

However, even when the pumping control signals P1, P2, G1, and G2 are all disabled during the test, the boosted voltage VPP is driven by the NMOS transistor-type diode NM1 and the threshold voltage Vt of the NMOS transistor-type diode NM1 at the power supply voltage VDD. Does not go below the voltage level (VDD-Vt).

As described above, the conventional charge pump circuit is basically configured to operate the boosted voltage VPP to follow the power supply voltage VDD level by the NMOS transistor type diode NM1 even when the pumping control signals P1, P2, G1, and G2 are disabled. In other words, it is impossible to perform the test by making the boosted voltage VPP to a level lower than the power supply voltage VDD.

An object of the present invention is to prevent a failure in the device using the boosted voltage because the boosted voltage rises above the target voltage level.

Another object of the present invention is to prevent the boosted voltage from rising in response to the increase of the power supply voltage level when the power supply voltage level rises higher than the target level of the boosted voltage.

Still another object of the present invention is to enable a test to be performed in a state in which the boosted voltage is lower than the power supply voltage.

An internal voltage generation circuit of the present invention for achieving the above object, the level control unit for detecting the level of the power supply voltage to generate a control signal according to the level of the power supply voltage; And a charge pump unit configured to generate a boosted voltage by pumping the power supply voltage during power-up, and supply of the power supply voltage is controlled by the control signal to control a level increase of the boosted voltage.

The level control unit may disable the control signal when the level of the power supply voltage is higher than or equal to a predetermined level, and the charge pump unit may maintain the level of the boosted voltage in response to the disabled control signal. .

The level control unit may divide the power supply voltage according to a set ratio to determine a logic value of the control signal according to the level of the divided voltage.

The level controller may include: a first detector configured to distribute the power voltage at a first ratio to generate a first logic signal corresponding to the level of the divided voltage; A second detector configured to distribute the power supply voltage at a second ratio to generate a second logic signal corresponding to the level of the divided voltage; And a combiner for combining the first and second logic signals to output the control signal.

The first sensing unit provided in the level control unit includes: first and second resistance elements connected in series to distribute the power voltage at a first ratio; And a first logic element configured to output the first logic signal by performing one of pull up and pull down by the divided voltage.

In addition, the second sensing unit provided in the level control unit includes third and fourth resistance elements connected in series to distribute the power voltage at a second ratio; And a second logic element configured to output the second logic signal by performing one of pull-up and pull-down by the divided voltage.

Preferably, in the first and second sensing units, the first and second logic elements each include an inverter, and any one of the first and second resistance elements and any of the third and fourth resistance elements. One preferably has the same resistance value.

The combination unit provided in the level controller may disable the control signal when both the first and second logic signals have a first logic value.

The charge pump unit may include: a voltage supply unit configured to selectively supply the power voltage according to a state of the control signal; And a pumping unit for pumping a power supply voltage supplied from the voltage supply unit and outputting the boosted voltage when the power-up is performed.

The voltage supply unit provided in the charge pump unit preferably includes a switch for selectively connecting between a node to which the power voltage is supplied and a node to which the boosted voltage is output according to a state of the control signal.

In the voltage supply unit, the switch may include a MOS transistor connected between a node to which the power voltage is supplied and a node to which the boost voltage is output, and receiving the control signal as a gate.

According to an aspect of the present invention, there is provided a semiconductor memory device including: a level controller configured to detect a level of a power supply voltage and generate a control signal according to the level of the power supply voltage; And generating a boosted voltage corresponding to the reference voltage level by comparing a level of a reference voltage and a boosted voltage during power-up and pumping a power supply voltage according to the compared result, and supplying the power supply voltage according to a state of the control signal. And an internal voltage generator circuit controlling the level of the boosted voltage by controlling the voltage.

Here, the level control unit disables the control signal when the level of the power supply voltage is higher than or equal to a predetermined level, and the internal voltage generation circuit keeps the level of the boosted voltage constant in response to the disabled control signal. desirable.

The level controller may be further configured to divide the power supply voltage according to a set ratio to determine a logic value of the control signal according to the level of the divided voltage.

The level controller may include: a first detector configured to distribute the power voltage at a first ratio to generate a first logic signal according to the level of the divided voltage; A second detector configured to divide the power supply voltage at a second ratio to generate a second logic signal according to the level of the divided voltage; And a combiner for combining the first and second logic signals to output the control signal.

The first sensing unit provided in the level control unit includes: first and second resistance elements connected in series to distribute the power voltage at a first ratio; And a first logic element configured to output the first logic signal by performing one of pull up and pull down by the divided voltage.

In addition, the second sensing unit provided in the level control unit includes third and fourth resistance elements connected in series to distribute the power voltage at a second ratio; And a second logic element configured to output the second logic signal by performing one of pull-up and pull-down by the divided voltage.

Preferably, in the first and second sensing units, the first and second logic elements each include an inverter, and any one of the first and second resistance elements and any of the third and fourth resistance elements. One preferably has the same resistance value.

The combination unit provided in the level controller may disable the control signal when both the first and second logic signals have a first logic value.

The internal voltage generation circuit may include: a level detector configured to compare a level of the reference voltage generated during the power-up with a level of the boosted voltage fed back to output a detection signal; An oscillator for generating a periodic signal in response to the sensed signal; A pumping control signal generator configured to generate a pumping control signal in response to the periodic signal; And a charge pump unit configured to pump the power supply voltage in response to the pumping control signal to generate the boosted voltage, and to control the level increase of the boosted voltage by the control signal.

The charge pump unit included in the internal voltage generation circuit may include a voltage supply unit configured to selectively supply the power voltage according to a state of the control signal; And a pumping part configured to pump the power supply voltage supplied from the voltage supply part and output the boosted voltage in response to the pumping control signal.

In the charge pump unit, the voltage supply unit preferably includes a switch for selectively connecting between the node to which the power supply voltage is supplied and the node to which the boosted voltage is output according to the state of the control signal.

In the voltage supply unit, the switch may include a MOS transistor connected between a node to which the power voltage is supplied and a node to which the boost voltage is output, and receiving the control signal as a gate.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

The semiconductor memory device of the present invention is characterized in that the booster voltage VPP is generated by pumping the power supply voltage VDD, and the level of the booster voltage VPP is controlled to a desired level by sensing the level of the power supply voltage VDD.

Specifically, referring to FIG. 3, the semiconductor memory device of the present invention includes a level controller 30 and an internal voltage generator circuit 32.

The level controller 30 detects the level of the power supply voltage VDD and generates a control signal CTRL whose state is determined according to the level of the power supply voltage VDD. The internal voltage generation circuit 32 compares the level of the reference voltage VREF and the boosted voltage VPP at power-up, pumps the power supply voltage VDD according to the result of comparison, and generates a boosted voltage VPP corresponding to the reference voltage VREF level. The level of the boosted voltage VPP is adjusted by controlling the supply of the supply voltage VDD in accordance with the state of the signal CTRL.

The power supply voltage VDD may be an external power supply voltage or an internal power supply voltage used in the semiconductor memory device. The internal power supply voltage may be divided into a power supply voltage used in a core region including a bank and a power supply voltage used in a peripheral circuit region such as a pad and a peripheral control circuit.

The level control unit 30 disables the control signal CTRL when the level of the power supply voltage VDD is higher than or equal to a predetermined level, and the internal voltage generation circuit 32 constantly adjusts the level of the boosted voltage VPP in response to the disabled control signal CTRL. Keep it.

Here, the level controller 30 divides the power supply voltage VDD according to a set ratio to determine a logic value of the control signal CTRL according to the level of the divided voltage. Preferably, as shown in FIG. 40 and 42 and combination 44.

That is, referring to FIG. 4, the detector 40 distributes the power supply voltage VDD at a first ratio to generate a first logic signal according to the level of the divided voltage. In addition, the detector 42 distributes the power supply voltage VDD at a second ratio to generate a second logic signal according to the level of the divided voltage. In addition, the combination unit 44 combines the first and second logic signals to determine whether the control signal CTRL is enabled.

For example, the sensing unit 40 performs a first logic signal by performing one of pull-up and pull-down based on the first and second resistor elements connected in series to distribute the power voltage VDD at a first ratio and the divided voltage. It may be configured to include a first logic element for outputting.

Here, the first resistance element may be composed of a resistor R1 connected between the line to which the power supply voltage VDD is supplied and the first logic element, and the second resistance element is an NMOS connected between the first logic element and the ground voltage VSS line. It may be composed of a transistor NM2. At this time, the gate of the NMOS transistor NM2 is connected to the first logic element. In addition, the first logic element may be configured as an inverter INV1.

For example, the sensing unit 42 performs a second logic signal by performing one of pull-up and pull-down by the third and fourth resistor elements connected in series to distribute the power voltage VDD at a second ratio, and the divided voltage. It may be configured to include a second logic element for outputting.

Here, the third resistance element may be composed of an NMOS transistor NM3 connected between the line to which the power supply voltage VDD is supplied and the second logic element, and the second resistance element is connected between the second logic element and the ground voltage VSS line. It may be composed of a resistor (R2). At this time, the gate of the NMOS transistor NM3 is connected to the second logic element. In addition, the second logic element may be configured as an inverter INV2.

The combiner 44 includes, for example, a noah gate NR1 for quinoaming the first and second logic signals, and an inverter INV3 for inverting the output of the noah gate NR1 and outputting the control signal CTRL. Can be configured.

The level control unit 30 having the above configuration operates to disable the control signal CTRL when the power supply voltage VDD is higher than or equal to a predetermined level through the resistance elements.

That is, in the sensing unit 40, the power supply voltage VDD is distributed by the resistor R1 and the NMOS transistor NM2, and the PMOS transistor (not shown) and the NMOS transistor where the divided voltage is provided in the inverter INV1. By turning on any one of (not shown), a high or low level signal is input to either of the two input terminals of NOR gate NR1.

Further, in the sensing unit 42, the power supply voltage VDD is distributed by the NMOS transistor NM3 and the resistor R2, and the PMOS transistor (not shown) and the NMOS transistor where the divided voltage is provided in the inverter INV2. By turning on any one of (not shown), a high or low level signal is input to the other of the two input terminals of NOR gate NR1.

When the signals input from the two sensing units 40 and 42 are both at the low level through the NOR gate NR1 and the inverter INV3, the control signal CTRL at a low level, that is, the disabled state is output.

As such, the level controller 30 may determine the time of disabling the control signal CTRL according to the resistance values of the two resistors R1 and R2 and the two NMOS transistors NM2 and NM3, and the two NMOS transistors NM2 and NM3. When the sizes of the same are the same, the timing of disabling the control signal CTRL may be determined by the ratio of the two resistors R1 and R2. For example, as shown in FIG. 5, when the level of the power supply voltage VDD is between 'B' and 'C', the resistance values of the two resistors R1 and R2 are set so that the control signal CTRL is disabled. Can be.

Referring to the configuration of the internal voltage generator circuit 32 again with reference to FIG. 3, the internal voltage generator circuit 32 includes a level detector 33, an oscillator 34, a pumping control signal generator 35, and a charge pump. It is comprised including the part 34.

The level detector 63 compares the reference voltage VREF with the level of the boosted voltage VPP fed back from the charge pump 34 to the sense signal PPE as a reference voltage VREF, which is a target level of the boosted voltage VPP, is input from the outside during power-up. Output In this case, the sensing signal PPE may be enabled when the boosted voltage VPP level is lower than the reference voltage VREF level.

The oscillator 34 operates when the sensing signal PPE output from the level sensing unit 63 is enabled to output a predetermined periodic signal OSC. Here, the oscillator 34 may be configured as a ring oscillator.

The pumping control signal generator 35 outputs the pumping control signals P1, P2, G1, and G2 for the pumping operation of the charge pump unit 34 in response to the periodic signal OSC output from the oscillator 34.

The charge pump unit 34 generates the boosted voltage VPP by pumping the power supply voltage VDD in response to the pumping control signals P1, P2, G1, and G2 output from the pumping control signal generator 35, and the level controller 30. The level rise of the boosted voltage VPP is controlled by the control signal CTRL outputted from the.

Here, the charge pump 38 may be specifically configured as shown in FIG. Referring to FIG. 6, the charge pump unit 38 may include a voltage supply unit 60 that selectively supplies the power supply voltage VDD according to the state of the control signal CTRL, and a voltage in response to the pumping control signals P1, P2, G1, and G2. And a pumping unit 62 for pumping the power supply voltage VDD supplied from the supply unit 60 and outputting the boosted voltage VPP.

The voltage supply unit 60 may include a switch for selectively connecting a node to which the power supply voltage VDD is supplied and a node to which the boosted voltage VPP is output according to the state of the control signal CTRL.

Here, the switch may be configured as, for example, an NMOS transistor NM4 connected between a node supplied with the power supply voltage VDD and a node outputting the boosted voltage VPP and receiving a control signal CTRL as a gate.

The pumping unit 62 is supplied with two PMOS transistors PM1 and PM2, a node P1BOOT, and a power supply voltage VDD connected in a cross couple structure between the node where the boosted voltage VPP is output and the nodes P1BOOT and P2BOOT. The NMOS transistor NM5 connected between the nodes, the gate connected to the node G1BOOT, the node P2BOOT, and the node supplied with the power voltage VDD, and the gate connected to the node G2BOOT, and the gate connected to the node G2BOOT. Forward and reverse diode structures between two NMOS transistors NM7 and NM8 connected in a cross-coupled structure between the nodes G1BOOT and G2BOOT and the node supplied with the supply voltage VDD, and between the node G1BOOT and the node supplied with the supply voltage VDD, respectively. NMOS transistors NM9 and NM10 connected to each other, two NMOS transistors NM11 and NM12 connected in a forward and reverse diode structure, respectively, between a node G2BOOT and a node to which a power supply voltage VDD is supplied, and a pumping control signal P1 is inputted. The two capacitors C1 and C2 connected in parallel between the node and the node P1BOOT, the pumping control signal P2 is inputted and the two capacitors C3 and C4 connected in parallel between the node and the node P2BOOT, and the pumping control signal G1 is inputted. And a capacitor C5 connected between the node and the node G1BOOT, and a capacitor C6 connected between the node to which the pumping control signal G2 is input and the node G2BOOT.

In the charge pump unit 34 having the above configuration, the level change of the boosted voltage VPP according to the state of the power supply voltage VDD and the control signal CTRL will be described with reference to FIG. 7. In the initial power-up, the boosted voltage VPP increases along the power supply voltage VDD level. While the pumping control signals P1, P2, G1, and G2 are enabled, the pump is pumped to the target level 'B'.

In addition, the boosted voltage VPP is maintained at the 'B' level by the operation of the level detector 33, the oscillator 34, the puncture control signal generator 35, and the charge pump 34, and then, the power supply voltage. When the level of VDD and the boosted voltage VPP is equal to 'B', the level of the boosted voltage VPP varies depending on the state of the control signal CTRL.

That is, when the control signal CTRL is enabled at the time when the level of the power supply voltage VDD and the boosted voltage VPP is equal to 'B', the level of the boosted voltage VPP follows the level of the power supply voltage VDD as in the conventional case.

However, when the control signal CTRL is disabled when the level of the power supply voltage VDD and the boosted voltage VPP is equal to 'B', the power supply voltage VDD is not supplied to the pump unit 62 as the NMOS transistor NM4 is turned off. Therefore, the boosted voltage VPP is maintained at the 'B' level. That is, the boosted voltage VPP may be maintained at a constant level without rising along the power supply voltage VDD level while the control signal CTRL is disabled.

Therefore, when the semiconductor memory device of the present invention wants the level of the boosted voltage VPP to be maintained at the target level of 'B', the control signal through the level controller 30 when the power supply voltage VDD rises to 'B' after power-up. By disabling CTRL, the level of the boosted voltage VPP can be maintained at the target level 'B'.

As described above, when the power supply voltage VDD is higher than the target level of the boosted voltage VPP, the semiconductor memory device of the present invention blocks the power supply voltage VDD from being supplied to the pump unit 62 so that the boosted voltage VPP rises above the target voltage level. Can be prevented.

In addition, since the boosted voltage VPP can be maintained at a desired target level, there is an effect of preventing a defect from occurring in an element using the boosted voltage VPP, for example, a cell transistor.

In addition, the semiconductor memory device of the present invention may maintain the boosted voltage VPP at a level lower than the power supply voltage VDD while the control signal CTRL is disabled through the level controller 30.

Therefore, there is an effect that it is possible to perform a specific test by making the boosted voltage VPP to a level lower than the power supply voltage VDD.

According to the present invention, when the power supply voltage is higher than the target level of the boosted voltage, the supply voltage of the power supply is cut off, thereby preventing the boosted voltage from rising above the target voltage level.

In the present invention, when the level of the boosted voltage rises due to the high level of the power supply voltage level, the supply of the supply voltage is interrupted to maintain the level of the boosted voltage at the target level, so that a defect occurs in the device using the boosted voltage. There is an effect that can be prevented.

In addition, the present invention has the effect of lowering the boosted voltage to a level lower than the power supply voltage level at a predetermined time point by blocking the supply of the power supply voltage when the power supply voltage rises above the boosted voltage level after the power up.

In addition, the present invention has the effect that the test can be performed in a state in which the boosted voltage is set to a level lower than the power supply voltage by cutting off the supply of the power supply voltage at a predetermined time.

While the invention has been shown and described with reference to specific embodiments, the invention is not limited thereto, and the invention is not limited to the scope of the invention as defined by the following claims. Those skilled in the art will readily appreciate that modifications and variations can be made.

Claims (25)

A level controller which senses a level of a power supply voltage and generates a control signal according to the level of the power supply voltage; And A charge pump unit configured to generate a boosted voltage by pumping the power supply voltage during power-up, and supply of the power supply voltage is controlled by the control signal to control a level increase of the boosted voltage; Circuit. The method of claim 1, The level control unit disables the control signal when the level of the power supply voltage is higher than or equal to a predetermined level, and the charge pump unit maintains the level of the boosted voltage constant in response to the disabled control signal. Voltage generating circuit. The method of claim 1, And the level controller divides the power supply voltage according to a set ratio to determine a logic value of the control signal according to the level of the divided voltage. The method of claim 3, wherein The level control unit, A first detector configured to distribute the power voltage at a first ratio to generate a first logic signal corresponding to the level of the divided voltage; A second detector configured to distribute the power supply voltage at a second ratio to generate a second logic signal corresponding to the level of the divided voltage; And And a combiner configured to combine the first and second logic signals and output the combined control signals as the control signals. The method of claim 4, wherein The first detection unit, First and second resistance elements connected in series distributing the power supply voltage at a first ratio; And And a first logic element configured to perform one of pull-up and pull-down by the divided voltage to output the first logic signal. The method of claim 5, wherein The second detector, Third and fourth resistance elements connected in series distributing the power supply voltage at a second ratio; And And a second logic element configured to perform one of pull-up and pull-down by the divided voltage to output the second logic signal. The method of claim 6, Wherein said first and second logic elements each comprise an inverter. The method of claim 6, Any one of said first and second resistive elements and one of said third and fourth resistive elements have the same resistance value. The method of claim 4, wherein And the combining unit disables the control signal when both the first and second logic signals have a first logic value. The method of claim 1, The charge pump unit, A voltage supply unit configured to selectively supply the power voltage according to the state of the control signal; And And a pumping unit for pumping a power supply voltage supplied from the voltage supply unit and outputting the boosted voltage when the power-up is performed. The method of claim 10, And the voltage supply unit selectively switches between a node to which the power voltage is supplied and a node to which the boosted voltage is output according to a state of the control signal. The method of claim 11, And the switch comprises a MOS transistor connected between a node to which the power voltage is supplied and a node to which the boost voltage is output, and receiving the control signal as a gate. A level controller which senses a level of a power supply voltage and generates a control signal according to the level of the power supply voltage; And Compare the levels of the reference voltage and the boosted voltage during power-up and pump the power supply voltage according to the result of the comparison to generate the boosted voltage corresponding to the reference voltage level, and supply the power supply voltage according to the state of the control signal. And an internal voltage generation circuit configured to control and adjust the level of the boosted voltage. The method of claim 13, The level control unit disables the control signal when the level of the power supply voltage is greater than or equal to a predetermined level, and the internal voltage generation circuit maintains the level of the boosted voltage constant in response to the disabled control signal. A semiconductor memory device. The method of claim 13, And the level controller divides the power supply voltage according to a set ratio to determine a logic value of the control signal according to the level of the divided voltage. The method of claim 15, The level control unit, A first sensing unit dividing the power supply voltage at a first ratio to generate a first logic signal according to the level of the divided voltage; A second detector configured to divide the power supply voltage at a second ratio to generate a second logic signal according to the level of the divided voltage; And And a combiner for combining the first and second logic signals to output the control signal. The method of claim 16, The first detection unit, First and second resistance elements connected in series distributing the power supply voltage at a first ratio; And And a first logic element configured to perform one of pull-up and pull-down by the divided voltage to output the first logic signal. The method of claim 17, The second detector, Third and fourth resistance elements connected in series distributing the power supply voltage at a second ratio; And And a second logic element configured to output the second logic signal by performing one of pull-up and pull-down by the divided voltage. The method of claim 18, And the first and second logic elements each comprise an inverter. The method of claim 18, Any one of said first and second resistive elements and one of said third and fourth resistive elements has the same resistance value. The method of claim 16, And the combiner disables the control signal when both the first and second logic signals have a first logic value. The method of claim 13, The internal voltage generation circuit, A level detector for comparing a level of the reference voltage generated during the power-up with the feedback voltage of the feedback voltage and outputting a sensing signal; An oscillator for generating a periodic signal in response to the sensed signal; A pumping control signal generator configured to generate a pumping control signal in response to the periodic signal; And And a charge pump unit configured to generate the boosted voltage by pumping the power supply voltage in response to the pumping control signal, and to control a level increase of the boosted voltage by the control signal. The method of claim 22, The charge pump unit, A voltage supply unit configured to selectively supply the power voltage according to the state of the control signal; And And a pumping unit configured to pump the power voltage supplied from the voltage supply unit and output the boosted voltage in response to the pumping control signal. The method of claim 23, And the voltage supply unit selectively switches between a node to which the power voltage is supplied and a node to which the boosted voltage is output according to a state of the control signal. The method of claim 24, And the switch comprises a MOS transistor connected between a node to which the power voltage is supplied and a node to which the boost voltage is output, and receiving the control signal as a gate.

Images