KR100656426B1 - Circuit for generating internal voltage in semiconductor memory apparatus - Google Patents

Abstract

An internal voltage generating circuit of a semiconductor memory device is provided to generate a stable internal voltage by preventing an operation error generated by enabling an operation signal when the level of an initial internal voltage is high in generating the internal voltage of the semiconductor memory device. A first control part(210) cuts off the supply of an external supply voltage(VDD) to a first node connecting a first comparison part(240) and a second comparison part(250) when an operation signal indicating the operation of an internal voltage generation circuit is enabled. A second control part(220) cuts off the supply of the external supply voltage to a second node connecting the first comparison part and the second comparison part when the operation signal is enabled. A third control part(230) cuts off the supply of the external supply voltage to a third node connecting the second comparison part and a driving part(260) when the operation signal is enabled. The first comparison part transfers a signal of different level to the second comparison part by comparing a reference voltage with a divided internal voltage. The second comparison part transfers a signal of different level to the driving part by comparing a signal inputted from the first comparison part with a signal of the first node. The driving part supplies or blocks the external power supply voltage to/from a voltage distribution part(270) according to the level of a signal inputted from the second comparison part. The voltage dividing part divides an internal voltage generated by receiving the external supply voltage from the driving part according to resistance ratio and then transfers the divided voltage to the first comparison part. A delay part(280) delays the operation signal transferred to the first control part.

Description

Circuit for Generating Internal Voltage in Semiconductor Memory Apparatus

1 is a block diagram showing a configuration of a power supply circuit of a general semiconductor memory device;

2 is a block diagram showing a configuration of an internal power generation circuit of a semiconductor memory device according to the present invention;

3 is a detailed configuration diagram of an internal power generation circuit of the semiconductor memory device shown in FIG. 2;

4 is a graph illustrating a simulation result of an internal power generation circuit of the semiconductor memory device shown in FIG. 3.

<Description of the symbols for the main parts of the drawings>

10: reference voltage generation circuit 20/200: internal power generation circuit

30: internal circuit 210: first control unit

220: second control unit 230: third control unit

240: first comparator 250: second comparator

260: driver 270: voltage divider

280: delay unit

The present invention relates to an internal power generation circuit of a semiconductor memory device, and more particularly, to an internal power generation circuit of a semiconductor memory device that prevents a malfunction occurring at an initial stage when generating an internal power supply of the semiconductor memory device.

The semiconductor memory device operates by receiving an external supply voltage VDD, a ground voltage VSS, and the like from the outside. Each of the voltages supplied from the outside is converted into a voltage of a level required by each region inside the semiconductor memory device and then used. In the semiconductor memory device, peripheral circuit operating voltage (Vperi), high potential voltage (VPP), bulk voltage (VBB), core circuit operating voltage (Vcore), etc. are used according to the needs of each region inside. There is a respective internal power generation circuit to generate internal power therefrom.

The level of external supply power VDD used to generate internal power in a semiconductor memory device may vary due to various factors. However, in order for the operation inside the semiconductor memory device to be smoothly performed, a stable internal power source that is not affected by the change of the external power supply VDD must be generated.

Hereinafter, an internal power generation circuit of a semiconductor memory device according to the related art will be described with reference to FIG. 1.

1 is a block diagram showing a configuration of a power supply circuit of a general semiconductor memory device.

The power supply circuit of the semiconductor memory device may include a reference voltage generation circuit 10 that generates a reference voltage Vref from an external supply power supply VDD, an internal power supply from the external supply power supply VDD, and the reference voltage Vref. And an internal power generation circuit 20 for generating Vint, and an internal circuit 30 in which the internal power supply Vint is used.

Here, the reference voltage Vref is a voltage used only to generate the internal power supply Vint, but the internal power supply Vint may be used as various power sources supplied to various internal circuits.

In the internal power generation circuit of the semiconductor memory device of the related art, when an operation signal is input when the initial internal power is high, a malfunction occurs in which the internal power temporarily rises, thereby preventing normal internal power from being generated. Caused.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problem, and is a semiconductor that generates stable internal power by preventing a malfunction that occurs when an operation signal is enabled when the level of the initial internal power is high when the internal power of the semiconductor memory device is generated. There is a technical problem in providing an internal power generation circuit of a memory device.

The internal power generation circuit of the semiconductor memory device of the present invention for achieving the above technical problem, the first node for connecting the first comparison unit and the second comparison unit when the operation signal indicating the operation of the internal power generation circuit is enabled. A first control unit which cuts off power supply of an external supply power supply VDD to the furnace; A second control unit which cuts off power supply of the external power supply VDD to a second node connecting the first comparator and the second comparator when the operation signal is enabled; A third control unit which cuts off power supply of the external power supply VDD to a third node connecting the second comparator and the driver when the operation signal is enabled; A first comparison unit comparing the magnitude of the reference voltage with the divided internal power supply and transferring a signal having a different level to the second comparison unit according to a comparison result; A second comparator comparing the signal input from the first comparator with a signal of the first node N1 and transferring a signal having a different level to the driver according to a comparison result; A driver configured to supply or cut off the power of the external power supply VDD to a voltage divider according to a level of a signal input from the second comparator; A voltage divider for distributing the internal power generated by receiving an external supply power VDD from the driver according to a resistance ratio and transferring the internal power to the first comparator; And a delay unit configured to delay an operation signal transmitted to the first control unit for a predetermined time.

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

2 is a block diagram illustrating a configuration of an internal power generation circuit of a semiconductor memory device according to the present invention.

The internal power generation circuit 200 of the semiconductor memory device according to the embodiment of the present invention may, when the operation signal Input indicating the operation of the internal power generation circuit 200 is enabled, the first comparator 240 and the second comparator. The first control unit 210 that cuts off the power supply of the external supply power VDD to the first node N1 connecting the 250, and the first comparison unit 240 when the operation signal Input is enabled. A second control unit 220 which cuts off the power supply of the external supply power VDD to the second node N2 connecting the second comparator 250 and the second comparator 250 when the operation signal Input is enabled. The third controller 230 which cuts off the power supply to the third node N3 connecting the second comparator 250 and the driver 260, compares the reference voltage Vref with the divided internal power. The first comparator 240 and the first comparator 240 for transmitting signals of different levels to the second comparator 250 according to the comparison result. The second comparator 250 and the second comparator 250 which compare the signal input from the signal with the signal of the first node N1 and transmit a signal having a different level to the driver 260 according to the comparison result. The driver 260 is configured to supply or cut off the power of the external supply power VDD to the voltage divider 270 according to the level of the signal input from the driver, and receive the external supply power VDD from the driver 260. A voltage divider 270 having a function of distributing the internal power Vint according to a resistance ratio and transferring the internal power Vint to the first comparator 240 and a delay unit for delaying an operation signal transmitted to the first controller for a predetermined time. 280.

The operation of the internal power generation circuit 200 of the semiconductor memory device configured as described above will be described with reference to the detailed configuration of the internal power generation circuit 200 shown in FIG. 3.

3 is a detailed configuration diagram of an internal power generation circuit of the semiconductor memory device shown in FIG. 2.

The first controller 210 is configured to receive the external supply power VDD from a source terminal, an output signal of the delay unit 280 to a gate terminal, and a drain terminal connected to the first node N1. It consists of one transistor 212.

In addition, the second control unit 220 is a second transistor in which the external supply power source VDD is applied to a source terminal, the operation signal Input is input to a gate terminal, and a drain terminal is connected to the second node N2. 222.

The third control unit 230 is a third transistor in which the external supply power VDD is applied to a source terminal, the operation signal Input is input to a gate terminal, and a drain terminal is connected to the third node N3. It consists of 232.

The first comparator 240 is applied with the external supply power supply VDD to a source terminal, a gate terminal is connected to the first node N1 and a drain terminal, and the drain terminal is connected to the fifth and sixth transistors 243 and 245. The fourth transistor 241 is connected to the fourth node (N4), the external supply power (VDD) is applied to the source terminal, the signal of the fourth node (N4) is input to the gate terminal and the drain terminal The fifth transistor 243 connected to the seventh transistor 247 and the fifth node N5 connected to the second node N2, and the drain terminal thereof are connected to the fourth node N4 and connected to the gate terminal. The sixth transistor 245 is connected to the sixth node N6 to which the reference voltage Vref is applied and the source terminal is connected to the seventh and eighth transistors 247 and 249, and the drain terminal is connected to the fifth node ( N5) and a voltage divided by the voltage divider 270 is applied to a gate terminal, and a source terminal is connected to the sixth terminal. A seventh transistor 247 and a drain terminal connected to the node N6 are connected to the sixth node N6, the operation signal Input is input to a gate terminal, and a source terminal is connected to the ground voltage VSS. An eighth transistor 249.

In addition, the second comparator 250 is applied with the external supply power source VDD to a source terminal, a gate terminal is connected to the first node N1, and a drain terminal is connected to the drain terminal and the gate terminal of the tenth transistor 254. And a ninth transistor 252, a drain terminal, and a gate terminal connected to the seventh node N7 connected to the gate terminal of the eleventh transistor 256 are connected to the seventh node N7 and the ground terminal is connected to the source terminal. A tenth transistor 254, to which a voltage VSS is connected, a drain terminal thereof is connected to a fifth node N5, which is connected to a twelfth transistor and the third node N3, and a gate terminal thereof is connected to the fourth node N4. And an external supply power source VDD are applied to the eleventh transistor 256 and the source terminal connected to the ground voltage VSS, the gate terminal is connected to the second node N2, and the drain terminal is connected to the ground terminal VSS. A twelfth transistor 258 connected to the fifth node N5. It is.

The driver 260 is a thirteenth transistor 262 in which an external supply power source VDD is applied to a source terminal, a gate terminal is connected to the third node N3, and a drain terminal is connected to the voltage distributor 270. It is composed of

In addition, the voltage divider 270 is composed of a plurality of resistors and is used to apply an internal power supply Vint by receiving power from an external supply power supply VDD and according to a ratio of the plurality of resistors. ) Is input to the gate terminal of the seventh transistor 247 of the first comparator 240.

In addition, the delay unit 280 may be considered to be an example consisting of an even number of inverters for delaying the operation signal (Input) for a predetermined time to transfer to the first control unit 210.

An operation of the internal power generation circuit 200 of the semiconductor memory device configured as described above will be described below.

For convenience of operation, the external power supply (VDD) is 1.8V, the reference voltage (Vref) is 0.75V, and the resistance ratio for distributing the voltage of the voltage divider 270 is 1: 1. Assume that Vint) is divided into 1/2 to be delivered to the second comparator 250. In this case, the internal power supply Vint has a value of 1.5V. In addition, the threshold voltages of the fourth transistor 241 and the fifth transistor 243 of the first comparator 240 are the same, and the threshold voltages of the sixth transistor 245 and the seventh transistor 247 are mutually equal. Assume the same. In addition, it is assumed that the threshold voltages of the ninth transistor 252 and the twelfth transistor 258 of the second comparator 250 are also the same.

When the reference voltage Vref is applied to the internal power generation circuit 200 and the operation signal Input is disabled, the first transistor 212 and the second control unit 220 of the first control unit 210 are disabled. The second transistor 222 and the third transistor 232 of the third controller 230 are turned on and the eighth transistor 249 of the first comparator 240 is turned on. The voltage that is turned off and applied to the first to sixth nodes N1 to N6 becomes a high level. Accordingly, since the ninth transistor 252, the twelfth transistor 258, and the thirteenth transistor 262 of the driver 260 of the second comparator 250 are turned off, the internal power source is turned off. The generation circuit 200 does not operate.

However, when the reference voltage Vref is applied to the internal power generation circuit 200 and the operation signal Input is enabled, the first transistor 212 of the first controller 210 is the delay unit 280. After turn off by a predetermined time, the second and third transistors 222 and 232 are turned off immediately after enabling the operation signal. Therefore, at the beginning of the operation of the internal power generation circuit 200, the power of the external supply power VDD supplied to the second and third nodes N2 and N3 is cut off, and the eighth transistor of the first comparator 240 is cut off. The operation of the circuit starts with (249) turned on.

Assuming that the internal power supply Vint initially has a value of 1.5 V or more, a voltage of 0.75 V is input to the sixth transistor 245 of the first comparator 240 and the seventh transistor 247 is provided. The input voltage is higher than 0.75V. Thus, the sixth and seventh transistors 245 and 247 are turned on, but the driving force is greater than that of the seventh transistor 247. Since the power of the first node N1 is supplied to the fourth node N4, the voltage level of the fourth node N4 falls to the threshold voltage level of the fourth transistor 241. However, at this time, after the predetermined time delay is delayed by the delay unit 280, the operation signal Input is input to the first control unit 210, and the first transistor 212 is applied according to the input of the operation signal Input. Since the power supply of the external supply power source VDD is turned off, the power supply to the first and fourth nodes of the external supply power source VDD is maintained within the time delayed by the delay unit 280. . Therefore, the voltage level of the fourth node N4 is higher than the voltage level of the fifth node N5. Therefore, the amount of current flowing through the ninth transistor 252 of the second comparator 250 is smaller than the amount of current flowing through the twelfth transistor 258. The current flowing through the ninth transistor 252 turns on the tenth and eleventh transistors 254 and 256, and at this time, the driving force of the eleventh transistor 256 is greater than the driving force of the twelfth transistor 258. As the driving force becomes smaller, the voltage applied to the third node N3 becomes high to a high level. Accordingly, the thirteenth transistor 262 of the driver 260 is turned off and no power is supplied to the voltage divider 270 from the external supply power VDD.

Assuming that the internal power supply Vint initially has a value of less than 1.5V, the voltage transferred from the power distribution unit 270 to the seventh transistor 247 of the first comparator 240 is 0.75V. It will have a lower value. Of course, it is also assumed here that the threshold voltage of the seventh transistor 247 is lower than 0.75V.

In the initial operation of the internal power supply operation circuit 200, power supply of the external power supply VDD is continued to the fourth node N4 by a delay time provided by the delay unit 280, and the fifth node ( Since the power supply of the external supply power source VDD is cut off at N5), the voltage level of the fourth node N4 will be higher than the voltage level of the fifth node N5. However, when the delay time given by the delay unit 280 passes, the first control unit 210 cuts off the power supply of the external supply power VDD. Thereafter, a voltage of 0.75 V is input to the sixth transistor 245 of the first comparator 240 and a voltage lower than 0.75 V is input to the seventh transistor 247, thereby flowing to the sixth transistor 245. The amount of current is greater than the amount of current flowing in the seventh transistor 247. Therefore, after a predetermined time, the voltage level of the fourth node N4 becomes lower than the voltage level of the fifth node N5. Therefore, the amount of current flowing through the ninth transistor 252 of the second comparator 250 is greater than the amount of current flowing through the twelfth transistor 258. The current flowing through the ninth transistor 252 turns on the tenth and eleventh transistors 254 and 256, and at this time, the driving force of the eleventh transistor 256 is greater than the driving force of the twelfth transistor 258. As the driving force becomes larger, the voltage applied to the third node N3 is lowered to a low level. Accordingly, the thirteenth transistor 262 of the driver 260 is turned on and the external power supply VDD is supplied to the voltage divider 270 to increase the level of the internal power supply Vint.

4 is a graph illustrating a simulation result of an internal power generation circuit of the semiconductor memory device shown in FIG. 3.

The graph shows that the operation signal Input is enabled at 30 ns and the operation signal Input_Delay delayed by the delay unit 280 is enabled at 40 ns. The initial internal power supply (Vint) has a value slightly higher than 1.5V. At 30 ns when the operation signal Input is enabled, the voltage of the sixth node N6 drops to a low level because the eighth transistor 249 of the first comparator 240 is turned on. Can be. In addition, the voltage of the seventh node N7 also drops by a predetermined level as the tenth transistor 254 of the second comparator 250 is turned on. The voltage of the fifth node N5 also drops by a predetermined level. At this time, the voltage of the fourth node N4 starts to drop when the delayed operation signal Input_Delay is enabled. Therefore, as in the prior art, there is no section in which the voltage of the fifth node N5 is higher than the voltage of the fourth node N4. Accordingly, the voltage of the third node N3 did not cause a significant drop, and the internal power supply Vint maintained a value close to 1.5V.

The problem that occurs when the operation signal is enabled when the initial internal power of the internal power generation circuit of the semiconductor memory device is high can be solved by giving a predetermined delay time to the operation signal input to the first controller 240. .

As such, those skilled in the art will appreciate that the present invention can be implemented in other specific forms without changing the technical spirit or essential features thereof. Therefore, the above-described embodiments are to be understood as illustrative in all respects and not as restrictive. The scope of the present invention is shown by the following claims rather than the detailed description, and all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included in the scope of the present invention. do.

The internal power generation circuit of the semiconductor memory device of the present invention described above generates a stable internal power supply by preventing a malfunction that occurs when an operation signal is enabled when the initial internal power level is high when the internal power generation of the semiconductor memory device is generated. It works.

Claims (7)

A first control unit which cuts off the power supply of the external power supply VDD to the first node connecting the first comparator and the second comparator when an operation signal indicating an operation of the internal power generation circuit is enabled; A second control unit which cuts off power supply of the external power supply VDD to a second node connecting the first comparator and the second comparator when the operation signal is enabled; A third control unit which cuts off power supply of the external power supply VDD to a third node connecting the second comparator and the driver when the operation signal is enabled; A first comparison unit comparing the magnitude of the reference voltage with the divided internal power supply and transferring a signal having a different level to the second comparison unit according to a comparison result; A second comparator comparing the signal input from the first comparator with a signal of the first node and transferring a signal having a different level to the driver according to a comparison result; A driver configured to supply or cut off the power of the external power supply VDD to a voltage divider according to a level of a signal input from the second comparator; A voltage divider for distributing the internal power generated by receiving an external supply power VDD from the driver according to a resistance ratio and transferring the internal power to the first comparator; And A delay unit configured to delay an operation signal transmitted to the first control unit for a predetermined time; Internal power generation circuit of a semiconductor memory device comprising a. The method of claim 1, The first control unit, A PMOS transistor to which an external supply power source (VDD) is applied to a source terminal, an output signal of the delay unit is input to a gate terminal, and a drain terminal is connected to the first node; Internal power generation circuit of a semiconductor memory device comprising a. The method of claim 1, The first comparison unit, A first transistor having a source terminal applied with the external supply power source (VDD), a gate terminal connected with the first node and a drain terminal, and a drain terminal connected with a fourth node connected with the second and third transistors; A second transistor to which a source terminal (VDD) is applied, a signal of the fourth node is input to a gate terminal, and a drain terminal is connected to a fourth node connected to a fourth transistor and the second node; A third transistor having a drain terminal connected to the fourth node, the reference voltage applied to a gate terminal, and a source terminal connected to a sixth node connected to fourth and fifth transistors; A fourth transistor having a drain terminal connected to the fifth node, a voltage divided by the voltage divider applied to a gate terminal, and a source terminal connected to the sixth node; And A fifth transistor having a drain terminal connected to the sixth node, the operation signal input to a gate terminal, and a source terminal connected to a ground voltage VSS; Internal power generation circuit of a semiconductor memory device comprising a. The method of claim 3, wherein Wherein the first and second transistors are PMOS transistors, and the third, fourth and fifth transistors are NMOS transistors. The method of claim 1, The second comparison unit, The external supply power source VDD is applied to a source terminal, a gate terminal is connected to the first node, and a drain terminal is connected to a drain node of the second transistor and a fourth node connected to the gate terminal and the gate terminal of the third transistor. A first transistor; A second transistor having a drain terminal and a gate terminal connected to the fourth node, and a ground voltage VSS connected to a source terminal; A third transistor having a drain terminal connected to a fourth transistor and a fifth node connected to the third node, a gate terminal connected to the fourth node, and a source voltage connected to the ground terminal VSS; And A fourth transistor having an external supply power source (VDD) applied to a source terminal, a gate terminal connected to the second node, and a drain terminal connected to the fifth node; Internal power generation circuit of a semiconductor memory device comprising a. The method of claim 5, Wherein the first and fourth transistors are PMOS transistors and the second and third transistors are NMOS transistors. The method of claim 1, The delay unit, An internal power generation circuit of a semiconductor memory device, characterized in that consisting of a series of combinations of even-numbered inverters.

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