KR100859477B1 - Method for Forming Semiconductor Device - Google Patents

Method for Forming Semiconductor Device Download PDF

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KR100859477B1
KR100859477B1 KR1020060137309A KR20060137309A KR100859477B1 KR 100859477 B1 KR100859477 B1 KR 100859477B1 KR 1020060137309 A KR1020060137309 A KR 1020060137309A KR 20060137309 A KR20060137309 A KR 20060137309A KR 100859477 B1 KR100859477 B1 KR 100859477B1
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film
forming
metal
thickness
sin film
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KR20080062036A (en
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주성중
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동부일렉트로닉스 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명은 반도체 기판에 절연막을 형성한 후 다마신 공정을 수행하여 비아 홀 또는 트렌치를 형성하는 단계와, 상기 비아 홀 및 상기 트렌치 내부를 금속물질로 매립한 후 평탄화 하여 금속 배선을 형성하는 단계와, 상기 금속배선을 포함하는 반도체 기판 상면에 SiN막을 형성한 후 식각공정을 수행하여 SiN막 패턴을 형성하는 단계와, 상기 SiN막 패턴 상부에 층간 금속막을 형성한 후 식각공정을 수행하여 금속 패드를 형성하는 단계를 포함하는 반도체 소자 형성 방법에 관한 것이다.The present invention provides a method of forming a via hole or a trench by forming an insulating film on a semiconductor substrate and performing a damascene process, and filling the via hole and the inside of the trench with a metal material and then flattening the metal wiring to form a metal wiring. Forming an SiN film pattern by forming an SiN film on an upper surface of the semiconductor substrate including the metal wiring and performing an etching process; and forming an interlayer metal film on the SiN film pattern and performing an etching process to form a metal pad. It relates to a method for forming a semiconductor device comprising the step of forming.

금속 패드, 디싱(Dishing) Metal Pads, Dicing

Description

반도체 소자 형성 방법{Method for Forming Semiconductor Device}Method for Forming Semiconductor Device {Method for Forming Semiconductor Device}

도 1a 내지 도 1e는 종래 기술에 따른 반도체 소자 형성 방법을 설명하기 위한 단면도.1A to 1E are cross-sectional views illustrating a method of forming a semiconductor device according to the prior art.

도 2a 내지 도 2e는 본 발명에 따른 반도체 소자 형성 방법을 설명하기 위한 단면도.2A to 2E are cross-sectional views illustrating a method of forming a semiconductor device in accordance with the present invention.

*** 도면의 주요 부분에 대한 부호의 설명 ****** Explanation of symbols for the main parts of the drawing ***

200:반도체 기판 202: 절연막200: semiconductor substrate 202: insulating film

204: 베리어(Barrier)막 210: 금속배선204 barrier film 210 metal wiring

212a: 실리콘 질화막 패턴 215a: 베리어 메탈(Barrier Metal)막 패턴212a: Silicon nitride film pattern 215a: Barrier metal film pattern

216a:알루미늄막 패턴 218a: 티탄늄(Ti)막 패턴216a: Aluminum film pattern 218a: Titanium (Ti) film pattern

220a:질화티탄늄(TiN)막 패턴 224: 금속 패드220a: titanium nitride (TiN) film pattern 224: metal pad

본 발명은 반도체소자 형성 방법에 관한 것으로, 특히, 금속 패드에서 단차에 의한 디싱(Dishing)을 방지하는 반도체 소자 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a semiconductor device, and more particularly, to a method for forming a semiconductor device for preventing dishing due to a step in a metal pad.

도 1a 내지 도 1e은 종래 기술에 따른 반도체 소자 형성방법을 설명하기 위 한 단면도들이다.1A to 1E are cross-sectional views illustrating a method of forming a semiconductor device according to the prior art.

먼저, 도 1a에서 나타낸 바와 같이, 반도체 기판(100) 상면에 절연막(102)을 형성한 후 트렌치 마스크(Trench Mask)를 이용하는 식각공정을 수행하여 비아 홀 및 트렌치를 형성한다.First, as shown in FIG. 1A, after forming the insulating film 102 on the upper surface of the semiconductor substrate 100, an etching process using a trench mask is performed to form via holes and trenches.

이 후, 에싱 및 세정공정을 수행하여 트렌치 마스크를 제거하고 비아 홀 및 트렌치를 포함하는 반도체 기판(100) 전면에 금속물질을 도포하여 금속막을 형성한 후 평탄화를 수행하여 금속배선(104)을 형성한다.Subsequently, the trench mask is removed by performing an ashing and cleaning process, a metal material is formed on the entire surface of the semiconductor substrate 100 including the via hole and the trench to form a metal film, and then the planarization is performed to form the metal wiring 104. do.

도 1b에서 나타낸 바와 같이, 금속배선(104)을 포함하는 반도체 기판(100) 전면에 SiN막(108) 및 TEOS막(110)을 형성한 후 TEOS막(110) 상면에 포토 마스크(Pre Trench Via Mask)(112)을 형성한다.As shown in FIG. 1B, the SiN film 108 and the TEOS film 110 are formed on the entire surface of the semiconductor substrate 100 including the metal wiring 104, and then a photo mask is formed on the upper surface of the TEOS film 110. Mask 112 is formed.

도 1c에서 나타낸 바와 같이, 포토 마스크(112)을 이용하는 식각공정을 수행하여 금속배선(104)의 일부가 노출되도록 SiN막(108) 및 TEOS막(110)을 선택적으로 식각하여 홀을 형성한 후 에싱 및 세정공정을 수행하여 포토 마스크(112)를 제거한다. As shown in FIG. 1C, after the etching process using the photo mask 112 is performed, the SiN film 108 and the TEOS film 110 are selectively etched to expose a portion of the metal wiring 104 to form holes. The photo mask 112 is removed by performing an ashing and cleaning process.

도 1d에서 나타낸 바와 같이, 홀을 포함하는 반도체 기판(100) 전면에 베리어 메탈막(114) 및 알루미늄(Al)막(116)을 순차적으로 형성한 후 알루미늄(116)막 상면에 엠피(MP: Metal Pad) 마스크(Mask)(118)를 형성한다.As shown in FIG. 1D, the barrier metal film 114 and the aluminum (Al) film 116 are sequentially formed on the entire surface of the semiconductor substrate 100 including holes, and then MP (MP :) is formed on the top surface of the aluminum 116 film. Metal Pad) Mask 118 is formed.

도 1e에서 나타낸 바와 같이, 엠피 마스크(118)를 이용하는 식각공정을 수행하여 알루미늄막(116) 및 베리어 메탈막(114)을 선택적으로 식각하여 금속패드(114a, 116a)를 형성한 후 에싱 및 세정공정을 수행하여 엠피 마스크(118)를 제 거한다.As shown in FIG. 1E, the aluminum film 116 and the barrier metal film 114 are selectively etched by performing an etching process using the MP mask 118 to form metal pads 114a and 116a, followed by ashing and cleaning. The process removes the MPP mask 118.

그러나, 금속 패드에서 단차에 의한 디싱(Dishing)이 발생하여 금속 패드가 금속라인 역할을 못하는 문제점이 있다.However, there is a problem that the metal pad does not function as a metal line because dishing occurs due to a step in the metal pad.

본 발명은 상술한 바와 같은 종래 기술의 문제점을 해결하기 위하여 제안된 것으로, 금속 패드에서 단차에 의한 디싱(Dishing)을 방지하여 금속 패드를 금속 라인으로 사용할 수 있는 반도체 소자 형성 방법을 제공하는 데 목적이 있다.SUMMARY OF THE INVENTION The present invention has been proposed to solve the problems of the prior art as described above, and an object of the present invention is to provide a method for forming a semiconductor device which can use a metal pad as a metal line by preventing dishing due to a step in the metal pad. There is this.

전술한 목적을 달성하기 위한 본 발명의 특징은 반도체 기판에 절연막을 형성한 후 다마신 공정을 수행하여 비아 홀 및 트렌치를 형성하는 단계와, 상기 비아 홀 및 상기 트렌치 내부를 금속물질로 매립한 후 평탄화하여 금속 배선을 형성하는 단계와, 상기 금속배선을 포함하는 반도체 기판 상면에 SiN막을 형성한 후 식각공정을 수행하여 SiN막 패턴을 형성하는 단계와, 상기 SiN막 패턴 상부에 층간 금속막을 형성한 후 식각공정을 수행하여 금속 패드를 형성하는 단계를 포함하는 반도체 소자 형성 방법에 관한 것이다.According to an aspect of the present invention, a via hole and a trench are formed by performing an damascene process after forming an insulating film on a semiconductor substrate, and filling the via hole and the inside of the trench with a metal material. Forming a metal wiring by planarization, forming a SiN film on an upper surface of the semiconductor substrate including the metal wiring, and performing an etching process to form a SiN film pattern, and forming an interlayer metal film on the SiN film pattern. It relates to a method of forming a semiconductor device comprising the step of performing an etching process to form a metal pad.

본 발명에서 상기 비아 홀 및 상기 트렌치 내부에 상기 금속물질을 매립하기 전에 상기 비아 홀 및 상기 트렌치 내부에 베리어 막을 형성하는 단계를 포함하는 것을 특징으로 한다.The method may include forming a barrier film in the via hole and the trench before filling the metal material in the via hole and the trench.

본 발명에서 상기 베리어 막은 300~600Å의 두께를 갖는 TaN막 또는 50~100Å의 두께를 갖는 TiSiN막으로 형성하는 것을 특징으로 한다.In the present invention, the barrier film may be formed of a TaN film having a thickness of 300 to 600 GPa or a TiSiN film having a thickness of 50 to 100 GPa.

본 발명에서 상기 SiN막 패턴을 형성하는 단계는, 상기 반도체 기판 상면에 상기 SiN막을 형성하는 단계와, 상기 SiN막 상면에 트렌치 마스크를 형성하는 단계와, 상기 트렌치 마스크를 이용하는 식각 공정을 수행하여 상기 SiN막 패턴을 형성하는 단계를 포함하는 것을 특징으로 한다.In the present invention, the forming of the SiN film pattern may include forming the SiN film on the upper surface of the semiconductor substrate, forming a trench mask on the upper surface of the SiN film, and performing an etching process using the trench mask. It characterized by comprising the step of forming a SiN film pattern.

본 발명에서 상기 SiN막은, 650~750Å의 두께로 형성하는 것을 특징으로 한다.In the present invention, the SiN film is formed to a thickness of 650 ~ 750Å.

본 발명에서 상기 층간 금속막은, 상기 SiN막 패턴 상부에 베리어 메탈막, 알루미늄(Al)막, Ti막 및 TiN막을 순차적으로 형성하는 것을 특징으로 한다.In the present invention, the interlayer metal film is characterized in that the barrier metal film, aluminum (Al) film, Ti film and TiN film sequentially formed on the SiN film pattern.

본 발명에서 상기 베리어 메탈막, 알루미늄(Al)막, Ti막 및 TiN막의 두께는, 상기 베리어 메탈막은 100~600Å의 두께로 형성하고, 상기 알루미늄(Al)막은 7000~11000Å의 두께로 형성하며, 상기 Ti막은 50~100Å의 두께로 형성하고, 상기 TiN막은 110~220Å의 두께로 형성하는 것을 특징으로 한다.In the present invention, the barrier metal film, the aluminum (Al) film, the Ti film, and the TiN film may have a thickness of 100 to 600 kPa, and the aluminum (Al) film to have a thickness of 7000 to 11000 kPa. The Ti film is formed to a thickness of 50 ~ 100Å, the TiN film is characterized in that formed to a thickness of 110 ~ 220Å.

본 발명에서 상기 금속 패드를 형성하는 단계는, 상기 SiN막 패턴 상부에 층간 금속막을 형성하는 단계와, 상기 층간 금속막 상에 엠피(MP:Metal Pad) 마스크(mask)를 형성하는 단계와, 상기 엠피 마스크를 이용하는 식각 공정을 수행하여 상기 금속 패드를 형성하는 단계를 포함하는 것을 특징으로 한다.In the present invention, the forming of the metal pad may include forming an interlayer metal film on the SiN film pattern, forming an MP (Metal Pad) mask on the interlayer metal film, and And forming the metal pad by performing an etching process using an MPP mask.

이하에서 첨부된 도면을 참조하여 본 발명에 따른 반도체 소자 형성방법에 대해서 상세히 설명한다.Hereinafter, a method of forming a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.

도 2a 내지 2e는 본 발명에 따른 반도체 소자 형성 방법을 설명하기 위한 단면도들이다.2A through 2E are cross-sectional views illustrating a method of forming a semiconductor device in accordance with the present invention.

먼저, 도 2a에서 나타낸 바와 같이, 반도체 기판(200) 상면에 소정의 두께를 갖는 절연막(202)을 형성하고 다마신 공정 예컨대, 듀얼 다마신 공정을 수행하여 절연막(202)을 선택적으로 식각하여 비아 홀(206) 및 트렌치(208)를 형성한 후 화학 기상 증착법(CVD:chemical Vapor Deposition)를 이용하여 비아 홀(206) 및 트렌치(208) 내부에 베리어막(204)을 형성한다.First, as shown in FIG. 2A, an insulating film 202 having a predetermined thickness is formed on the upper surface of the semiconductor substrate 200, and the insulating film 202 is selectively etched by performing a damascene process, for example, a dual damascene process. After forming the holes 206 and the trenches 208, the barrier layer 204 is formed in the via holes 206 and the trenches 208 using chemical vapor deposition (CVD).

여기서, 베리어막(204)은 예컨대, 300~600Å의 두께를 갖는 질화티탄늄(TaN)막 또는 50~100Å의 두께를 갖는 실리사이드(TiSiN)막으로 형성할 수 있다.Here, the barrier film 204 may be formed of, for example, a titanium nitride (TaN) film having a thickness of 300 to 600 GPa or a silicide (TiSiN) film having a thickness of 50 to 100 GPa.

도 2b에서 나타낸 바와 같이, 비아 홀(206) 및 트렌치(208)를 포함하는 반도체 기판(200) 상면에 구리(Cu)와 같은 금속물질을 도포하여 금속막을 형성하고 금속막에 대해 평탄화를 수행하여 금속배선(210)을 형성한 후 소정 두께 예컨대, 650~750Å의 두께를 갖는 실리콘 질화막(SiN)(212)을 형성한다.As shown in FIG. 2B, a metal material such as copper (Cu) is coated on the upper surface of the semiconductor substrate 200 including the via hole 206 and the trench 208 to form a metal film, and the metal film is planarized. After the metal wiring 210 is formed, a silicon nitride film (SiN) 212 having a predetermined thickness, for example, a thickness of 650 to 750 Å is formed.

도 2c에서 나타낸 바와 같이, 실리콘 질화막(212) 상면에 트렌치 마스크(Trench Mask)(214)를 형성한 후 트렌치 마스크(214)를 이용하는 식각공정을 수행하여 금속배선(210)의 일부가 노출되도록 실리콘 질화막(212)을 선택적으로 식각하여 실리콘 질화막 패턴(212a)을 형성한다.As illustrated in FIG. 2C, a trench mask 214 is formed on the upper surface of the silicon nitride film 212, and then an etching process using the trench mask 214 is performed to expose a portion of the metal wiring 210. The nitride film 212 is selectively etched to form a silicon nitride film pattern 212a.

도 2d에서 나타낸 바와 같아. 세정 및 에싱 공정을 수행하여 트렌치 마스크(214)를 제거하고 실리콘 질화막 패턴(212a)을 포함하는 반도체 기판(200) 전면에 베리어 메탈막(215), 알루미늄(Al)막(216), Ti막(218) 및 TiN막(220)을 순차적으로 형성한 후 엠피 마스크(MP Mask)(222)를 형성한다.As shown in Figure 2d. The barrier mask 214 is removed by the cleaning and ashing process, and the barrier metal film 215, the aluminum (Al) film 216, and the Ti film (the TiO) are formed on the entire surface of the semiconductor substrate 200 including the silicon nitride film pattern 212a. 218 and the TiN film 220 are sequentially formed, and then an MP mask 222 is formed.

여기서, 베리어 메탈막(215)은 100~600Å의 두께로 형성하고, 알루미늄(Al) 막(216)은 7000~11000Å의 두께로 형성하며, Ti막(218)은 50~100Å의 두께로 형성하고, TiN막(220)은 110~220Å의 두께로 형성한다.Here, the barrier metal film 215 is formed to a thickness of 100 ~ 600Å, the aluminum (Al) film 216 is formed to a thickness of 7000 ~ 11000Å, the Ti film 218 is formed to a thickness of 50 ~ 100Å , TiN film 220 is formed to a thickness of 110 ~ 220Å.

도 2e에서 나타낸 바와 같이, 엠피 마스크(222)를 이용하는 식각공정을 수행하여 TiN막(220), Ti막(218), 알루미늄막(216) 및 베리어 메탈막(215)을 선택적으로 식각하여 금속 패드(224)을 형성한다.As shown in FIG. 2E, the TiN film 220, the Ti film 218, the aluminum film 216, and the barrier metal film 215 may be selectively etched by performing an etching process using an MPP mask 222 to form a metal pad. Form 224.

이상과 같이 본 발명은 비록 한정된 실시 예와 도면에 의해 설명되었으나, 본 발명은 상기의 실시 예에 한정되는 것이 아니며, 본 발명이 속하는 분야에서 통상의 지식을 가진 자라면, 이러한 기재로부터 다양한 수정 및 변형이 가능하다.As described above, although the present invention has been described with reference to the limited embodiments and the drawings, the present invention is not limited to the above embodiments, and those skilled in the art to which the present invention pertains can make various modifications and Modifications are possible.

그러므로, 본 발명의 범위는 설명된 실시 예에 국한되어 정해져서는 아니되며, 후술하는 특허청구범위뿐만 아니라 이 특허 청구범위와 균등한 것들에 의해 정해져야 한다.Therefore, the scope of the present invention should not be limited to the described embodiments, but should be determined not only by the claims below but also by the equivalents of the claims.

이상에서 설명한 바와 같이, 본 발명에 따른 반도체소자 형성방법에서 금속 패드의 단차를 방지함으로써, 디싱(Dishing)을 방지하고 금속 패드를 금속 라인으로 사용할 수 있는 효과가 있다.As described above, by preventing the step of the metal pad in the method of forming a semiconductor device according to the present invention, it is possible to prevent dishing and to use the metal pad as a metal line.

Claims (8)

반도체 기판에 절연막을 형성한 후 다마신 공정을 수행하여 비아 홀 및 트렌치를 형성하는 단계와,Forming a via hole and a trench by forming an insulating film on the semiconductor substrate and performing a damascene process; 상기 비아 홀 및 상기 트렌치 내부에 베리어 막을 형성하는 단계와,Forming a barrier film in the via hole and the trench; 상기 베리어 막이 형성된 비아 홀 및 상기 트렌치 내부를 금속물질로 매립한 후 평탄화하여 금속 배선을 형성하는 단계와,Filling the via hole and the inside of the trench with a metal material and then planarizing the via hole on which the barrier film is formed to form a metal wiring; 상기 금속배선을 포함하는 반도체 기판 상면에 SiN막을 형성하고, 상기 SiN막에 대해 식각 공정을 수행하여 SiN막 패턴을 형성하는 단계와,Forming a SiN film on an upper surface of the semiconductor substrate including the metal wiring, and performing an etching process on the SiN film to form a SiN film pattern; 상기 SiN막 패턴이 형성된 반도체 기판상에 층간 금속막을 형성하고, 상기 층간 금속막에 대해 식각 공정을 수행하여 금속 패드를 형성하는 단계를 포함하는 것을 특징으로 하는 반도체 소자 형성 방법.Forming an interlayer metal film on the semiconductor substrate on which the SiN film pattern is formed, and performing an etching process on the interlayer metal film to form a metal pad. 삭제delete 제1항에 있어서,The method of claim 1, 상기 베리어 막은The barrier membrane 300~600Å의 두께를 갖는 TaN막 또는 50~100Å의 두께를 갖는 TiSiN막으로 형성하는 것을 특징으로 하는 반도체 소자 형성 방법.A semiconductor device forming method comprising: a TaN film having a thickness of 300 to 600 kPa or a TiSiN film having a thickness of 50 to 100 kPa. 제1항에 있어서,The method of claim 1, 상기 SiN막 패턴을 형성하는 단계는,Forming the SiN film pattern, 상기 반도체 기판 상면에 상기 SiN막을 형성하는 단계와,Forming the SiN film on an upper surface of the semiconductor substrate; 상기 SiN막 상면에 트렌치 마스크를 형성하는 단계와,Forming a trench mask on an upper surface of the SiN film; 상기 트렌치 마스크를 이용하는 식각 공정을 수행하여 상기 SiN막 패턴을 형성하는 단계와,Performing an etching process using the trench mask to form the SiN film pattern; 상기 SiN막 패턴 상에 잔류하는 트렌치 마스크를 제거하는 단계를 포함하는 것을 특징으로 하는 반도체 소자 형성방법.Removing the trench mask remaining on the SiN film pattern. 제1 항 또는 제4 항에 있어서,The method according to claim 1 or 4, 상기 SiN막은,The SiN film, 650~750Å의 두께로 형성하는 것을 특징으로 하는 반도체 소자 형성 방법.It is formed in the thickness of 650-750 GPa, The semiconductor element formation method characterized by the above-mentioned. 제1항에 있어서,The method of claim 1, 상기 층간 금속막은,The interlayer metal film, 상기 SiN막 패턴 상부에 베리어 메탈막, 알루미늄(Al)막, Ti막 및 TiN막을 순차적으로 형성하는 것을 특징으로 하는 반도체 소자 형성방법.And forming a barrier metal film, an aluminum (Al) film, a Ti film, and a TiN film sequentially on the SiN film pattern. 제6항에 있어서,The method of claim 6, 상기 베리어 메탈막은 100~600Å의 두께로 형성하고, The barrier metal film is formed to a thickness of 100 ~ 600Å, 상기 알루미늄(Al)막은 7000~11000Å의 두께로 형성하며,The aluminum (Al) film is formed to a thickness of 7000 ~ 11000Å, 상기 Ti막은 50~100Å의 두께로 형성하고,The Ti film is formed to a thickness of 50 ~ 100Å, 상기 TiN막은 110~220Å의 두께로 형성하는 것을 특징으로 하는 반도체 소자 형성 방법.The TiN film is a semiconductor device forming method, characterized in that formed to a thickness of 110 ~ 220Å. 제1항에 있어서,The method of claim 1, 상기 금속 패드를 형성하는 단계는,Forming the metal pad, 상기 SiN막 패턴 상부에 층간 금속막을 형성하는 단계와,Forming an interlayer metal film on the SiN film pattern; 상기 층간 금속막 상에 엠피 마스크(MP Mask)를 형성하는 단계와,Forming an MP mask on the interlayer metal film; 상기 엠피 마스크를 이용하는 식각 공정을 수행하여 상기 금속 패드를 형성하는 단계를 포함하는 것을 특징으로 하는 반도체 소자 형성방법.And forming the metal pad by performing an etching process using the MPP mask.
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KR20020032400A (en) * 2000-10-26 2002-05-03 마츠시타 덴끼 산교 가부시키가이샤 Semiconductor device and method for fabricating semiconductor device
JP2004022579A (en) 2002-06-12 2004-01-22 Toshiba Corp Semiconductor device and its manufacturing method
KR20050054066A (en) * 2003-12-03 2005-06-10 삼성전자주식회사 Method of of forming interconnection lines in a semiconductor memory device

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20020032400A (en) * 2000-10-26 2002-05-03 마츠시타 덴끼 산교 가부시키가이샤 Semiconductor device and method for fabricating semiconductor device
JP2004022579A (en) 2002-06-12 2004-01-22 Toshiba Corp Semiconductor device and its manufacturing method
KR20050054066A (en) * 2003-12-03 2005-06-10 삼성전자주식회사 Method of of forming interconnection lines in a semiconductor memory device

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