KR100857700B1 - Thin film transistor for flat panel display and method for fabricating the same - Google Patents

Thin film transistor for flat panel display and method for fabricating the same Download PDF

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Publication number
KR100857700B1
KR100857700B1 KR1020070033842A KR20070033842A KR100857700B1 KR 100857700 B1 KR100857700 B1 KR 100857700B1 KR 1020070033842 A KR1020070033842 A KR 1020070033842A KR 20070033842 A KR20070033842 A KR 20070033842A KR 100857700 B1 KR100857700 B1 KR 100857700B1
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South Korea
Prior art keywords
thin film
film transistor
flat panel
doping
semiconductor layer
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KR1020070033842A
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Korean (ko)
Inventor
김종윤
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삼성에스디아이 주식회사
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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136259—Repairing; Defects
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3215—Doping the layers
    • H01L21/32155—Doping polycristalline - or amorphous silicon layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel

Abstract

A thin film transistor for a flat panel display according to an embodiment of the present invention includes a substrate on which an insulating film is deposited and a semiconductor layer formed on the insulating film, wherein at least one doped region is formed and a connection region connecting the doped regions is formed. The doped region is doped with an N-type or P-type, and the connection region is intrinsic.

Description

Thin film transistor for flat panel display and method for manufacturing the same {Thin Film Transistor for flat panel display and method for fabricating the same}

1A and 1B are plan views of a thin film transistor for a flat panel display according to the prior art.

2A and 2B are plan views of a thin film transistor for a flat panel display having a short circuit according to the prior art.

3A and 3B are plan views of a thin film transistor and a doping mask for a flat panel display according to an exemplary embodiment of the present invention.

4 is a plan view of a thin film transistor for a flat panel display according to another exemplary embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

100 semiconductor layer 200 U-shaped doped region

400, 700: Doping mask 500: L-shaped doping area

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor, and in the case of forming a doped region, a space between the doped regions is narrowed so that some doped regions can be connected. Even when such a connection occurs, normal on / off switching A thin film transistor for a flat panel display capable of switching and a method of manufacturing the same.

Thin film transistors are turned on and off in flat panel displays such as Active Matrix Organic Light Emitting Diodes (AMOLEDs) or Active Matrix Liquid Crystal Displays (AMLCDs). It is widely used as a switching device. As the material of the thin film transistor, polycrystalline silicon thin film and amorphous silicon thin film are mainly used. Recently, the crystallization method using laser is widely used, and the current driving ability is excellent and fast. There is a growing interest in polycrystalline silicon thin films having operating speeds.

The polycrystalline silicon thin film has a high mobility compared to amorphous silicon, and can be formed by integrating a driving circuit on a substrate, and high resolution can be realized compared to a flat panel display using amorphous silicon. It is being used for high quality flat panel displays such as AMOLED and AMLCD.

1A and 1B are plan views of a thin film transistor for a flat panel display according to the prior art.

Referring to FIG. 1A, a thin film transistor for a flat panel display according to the related art includes a semiconductor layer 10 and a U-shaped doped region 20.

Amorphous silicon or polycrystalline silicon is used for the semiconductor layer 10. The semiconductor layer 10 is usually formed of a layer having a constant width and length, and the U-shaped doped region 20 is formed through impurity doping.

A contact hole is formed in each distal end of the U-shaped doped region 20, and source and drain electrodes are formed in each contact hole. The active layer corresponding between the source and drain electrodes becomes the channel region of the thin film transistor. The U-shaped doped region 20 performs an on / off switching function together with a gate electrode formed on the semiconductor layer 10.

Referring to FIG. 1B, a thin film transistor for a flat panel display according to the related art includes a semiconductor layer 10 and an L-shaped doped region 40.

As described above, amorphous semiconductor or polycrystalline silicon is used for the semiconductor layer 10. The semiconductor layer 10 is typically formed of a layer having a constant width and length, and the L-shaped doped region 40 is formed through the impurity doping. The L-shaped doped regions 40 act as a pair to perform a function of a capacitor that stores a constant charge.

2A and 2B are plan views of a thin film transistor for a flat panel display having a short circuit according to the prior art.

In a general semiconductor process, a series of processes for transferring a pattern designed on a mask onto a substrate on which a thin film to be processed is formed is called photolithography. The photolithography process is a process of applying photoresist (PR) to the substrate surface with a uniform thickness, a process of aligning and exposing the mask and the substrate on which the pattern is formed, and developing the photoresist. To form a PR pattern. PR reacts with light. In contrast to positive PR that dissolves upon receiving light, there is a negative PR that hardens upon receiving light. Hereinafter, the PR will be described based on positive PR.

In the photolithography process, PR is first applied to the substrate surface with a uniform thickness. Subsequently, when the mask is aligned on the substrate and UV rays are emitted, light cannot pass through the portion where the mask is chromium, and light passes through the part where the mask is not. PR sting light is dissolved, and PR not stinging remains hard and remains on the wafer. Then, a pattern designed on the mask is realized on the substrate by selectively removing the PR of the exposed and unexposed regions that reacted with ultraviolet rays using a developer.

Currently, display products have been advanced in order to provide high resolution images, and thus it is very difficult to ensure good PR pattern uniformity after development.

Therefore, after development, the connection region 30 is generated and short-circuited between the terminal portions of the U-shaped doped region 20 where the contact hole of the U-shaped doped region 20 is formed as shown in FIG. A connection area 50 may be generated between the 40 and may be shorted.

In such a short circuit, the current always flows without passing through the thin film transistor so that the thin film transistor cannot perform the on / off switching function, or the capacitor cannot charge the charge. As a result, lighting failures such as bright spots, dark spots, and clustering defects occur in the short-circuited region, and thus, pixels of the flat panel display do not operate properly.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and when a short circuit occurs in the doped region, the doping mask is used to cover all regions except the doped region requiring doping. The purpose of the present invention is to prevent the lighting failure of the display by maintaining the functions of the thin film transistor and the capacitor normally.

The objects of the present invention are not limited to the above-mentioned objects, and other objects that are not mentioned will be clearly understood by those skilled in the art from the following description.

A thin film transistor for a flat panel display for achieving the above object includes a substrate on which an insulating film is deposited and a semiconductor layer disposed on the insulating film, wherein a doped region is formed and a connection region connecting the doped regions is formed. The doped region is doped with an N-type or P-type, and the connecting region is intrinsic.

In addition, a method of manufacturing a thin film transistor for a flat panel display includes depositing an insulating film on a substrate, forming a semiconductor layer having at least one doped region, and using a doping mask to cover all regions except the doped region. Doping an N-type or P-type impurity into the.

Hereinafter, with reference to the drawings will be described a preferred embodiment of the present invention.

3A and 3B are plan views of a thin film transistor and a doping mask for a flat panel display according to an exemplary embodiment of the present invention.

The thin film transistor for flat panel display according to the exemplary embodiment of the present invention includes a semiconductor layer 100 and a doped region.

The semiconductor layer 100 is about several hundred nm typical SiO 2 on the substrate. Or SiN x on an insulating film deposited with an insulating film. The insulating film prevents impurities contained in the glass substrate from contaminating the semiconductor layer 100 at a later process of manufacturing the thin film transistor.

Amorphous silicon or polycrystalline polysilicon is used for the semiconductor layer 100. Amorphous silicon is similar to crystalline silicon in terms of coordination number, bond angle, and bond length, but there are dangling-bonds, so there is regularity in the short range, but large atomic size ( long range) refers to silicon with no regularity.

Due to such an orderless structure of amorphous silicon, numerous defect states are formed in the amorphous silicon in the forbidden gap of the energy band gap, which cannot exist in crystalline silicon. The electro-optical properties of amorphous silicon are sensitively dependent on the energy distribution of the defect state in the forbidden region, and by controlling the density of defects, the semiconductor characteristics can be used as a switch element.

Since amorphous silicon is easy to fabricate a device and has low device characteristics but uniform properties, the semiconductor layer 100 is formed using amorphous silicon in a large flat panel display.

Compared to amorphous silicon, polycrystalline silicon has high mobility and device characteristics that amorphous silicon cannot have, and thus, there is an advantage in that a driving circuit can be embedded and a high resolution image can be provided.

In order to form the semiconductor layer 100 from polycrystalline silicon, first, amorphous silicon is deposited on a substrate on which an insulating film is deposited. Thereafter, an excimer laser or the like is irradiated to crystallize amorphous silicon into polycrystalline silicon.

The doped region is usually formed by doping impurities into the semiconductor layer 100 formed of a layer having a constant width and length. The shape of the substrate may be variously formed according to each substrate design, and may be formed of the U-shaped doped region 200 and the L-shaped doped region 500.

When the semiconductor layer 100 is P-type, the doped region is doped with N-type impurities. When the semiconductor layer 100 is N-type, the doped region is doped with P-type impurities. The case where the N-type impurities are doped is called NMOS. The case of doping with a type impurity is called PMOS.

A contact hole is formed at each distal end of the U-shaped doped region 200 shown in FIG. 3A, and source and drain electrodes are formed in each contact hole. The active layer corresponding between the source and drain electrodes becomes the channel region of the thin film transistor. . The U-shaped doped region 200 performs an on / off switching function together with a gate electrode formed on the semiconductor layer 100.

In addition, the L-shaped doped region 500 illustrated in FIG. 3B functions as a pair to perform a function of a capacitor that stores a constant charge.

The doped region is formed by doping impurities on the pattern formed on the substrate after the aforementioned development process is completed.

In general, in doping a doping region, doping is performed using a PR that is not yet dissolved on the pattern as a mask, a doping using a gate electrode as a mask, or a separate doping mask. .

However, the pattern forming operation in the photolithography process may not always be performed perfectly, so that the pattern may be formed in the portion where the pattern should not be formed. After the doping process is performed, the dopant is doped to such a pattern, and the doping is performed not only to the originally intended doping region but also to a connection region connecting the doping regions not originally intended for doping. As the doping is performed to the connection region, current flows in the thin film transistor so that the on / off switching function cannot be performed, and current flows in the capacitor.

In order to solve this problem, the following doping masks have been devised.

The doping mask according to the exemplary embodiment of the present invention covers all of the regions except the doping region requiring doping with the doping mask. When the doping process is performed using such a doping mask, even when a pattern is formed incorrectly, doping is not performed in the connection region, and the connection region is maintained in an intrinsic state, and thus no carrier exists. There is little current flow in the region. Therefore, it is not expressed as a defect.

FIG. 3A illustrates a case in which a U-shaped doped region 200 is formed in the semiconductor layer 100, and thus a pattern is formed incorrectly so that a connection region 300 connecting both ends of the U-shaped doped region 200 is formed. Doing.

In this case, when the doping is performed as in the related art, the doping is performed to the connection region 300. As a result, the source electrode and the drain electrode of the thin film transistor are short-circuited, and thus the on / off switching is not performed.

However, when the doping is performed using the doping mask 400 according to the exemplary embodiment of the present invention, since the doping is not performed in the connection region 300, the thin film transistor functions normally even though it is shorted.

FIG. 3B illustrates a case in which the L-shaped doped region 500 is formed in the semiconductor layer 100, and a connection region 600 is formed in which a pattern is formed incorrectly to connect both ends of the L-shaped doped region 500. Doing.

 At this time, if doping is performed as in the related art, doping is performed to the connection region 600, and as a result, current flows through the connection region 600, and thus no charge is charged in the capacitor.

However, when the doping is performed using the doping mask 700 according to the exemplary embodiment of the present invention, since the doping is not performed in the connection region 600, the capacitor functions normally even though it is shorted.

4 is a plan view of a thin film transistor for a flat panel display according to another exemplary embodiment of the present invention.

A thin film transistor for a flat panel display according to another embodiment of the present invention includes a semiconductor layer 100 and a V-shaped doped region 800.

Since the semiconductor layer 100 is the same as described above, a description thereof will be omitted here.

Unlike the U-shaped doped region 200 described above, the V-shaped doped region 800 has a wider gap than the U-shaped doped region 200 than the U-shaped doped region 200.

In this way, even when the pattern is not normally formed in the photolithography step, the gap between the both ends is wide, thereby preventing short circuit.

Hereinafter, a method of manufacturing a thin film transistor according to an embodiment of the present invention will be described with reference to FIGS. 3A, 3B, and 4.

First, an insulating film is deposited on a substrate. Thereafter, amorphous silicon is deposited on the substrate on which the insulating film is deposited by plasma chemical vapor deposition or low temperature chemical vapor deposition to pattern the semiconductor layer 100. Here, the semiconductor layer 100 and the insulating film are as described in the description of FIGS. 3A and 3B.

When the semiconductor layer 100 is formed of polycrystalline silicon, crystallized amorphous silicon deposited through plasma chemical vapor deposition or low temperature chemical vapor deposition on the substrate on which the insulating film is deposited is subjected to annealing with a laser or heat to crystallize the semiconductor. Pattern layer 100.

Thereafter, a gate insulating layer is deposited on the semiconductor layer 100, and metal thin films such as Mo and MoW to be used as the gate electrode are successively deposited to form a gate electrode.

As the gate insulating layer, a material such as SiN x or SiO 2 is usually used as a layer for insulating the gate electrode from the semiconductor layer 100. The gate insulating layer is formed on the semiconductor layer 100, and a gate electrode is formed on the gate insulating layer. The gate electrode is intended to supply a voltage, and Mo or MoW is used a lot.

Next, impurities are doped into the doped region of the semiconductor layer 100. When the semiconductor layer 100 is P-type, the doped region is doped with N-type impurities. When the semiconductor layer 100 is N-type, the doped region is doped with P-type impurities. The case where the N-type impurities are doped is called NMOS. The case of doping with a type impurity is called PMOS.

When the doping region is doped with impurities, all the regions except the doping region requiring doping are covered with the doping mask using a doping mask according to an embodiment of the present invention. Such a doping mask is as described above.

Thereafter, an interlayer insulating layer is deposited on the entire region of the thin film transistor intermediate structure, contact holes are formed to expose one section of the source and drain regions, and metal and wires are deposited to form source and drain electrodes to complete the thin film transistor. do.

As described above, according to the present invention, when a short circuit occurs in the doped region, the doping mask is used to cover all of the regions except for the doped region requiring doping. The function of the capacitor can be maintained normally to prevent the display from failing.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (9)

A substrate on which an insulating film is deposited; And A thin film transistor for a flat panel display, comprising: a semiconductor layer disposed on the insulating layer, the semiconductor layer having one or more doped regions formed thereon and a connection region connecting the doped regions. The doped region is doped with N type or P type, The connection region is an intrinsic state, the thin film transistor for flat panel display The method of claim 1, The insulating film is SiO 2 Or thin film transistors for flat panel displays with SiN x The method of claim 1, The semiconductor layer is a thin film transistor for a flat panel display formed of amorphous silicon or polycrystalline silicon delete delete delete Depositing an insulating film on the substrate; Forming a semiconductor layer having one or more doping present; And Doping an N-type or P-type impurity in the doped region by using a doping mask covering all regions except the doped region. The method of claim 7, wherein The insulating film is SiO 2 Or manufacturing method of thin film transistor for SiN x flat panel display The method of claim 7, wherein The semiconductor layer is a method of manufacturing a thin film transistor for a flat panel display formed of amorphous silicon or polycrystalline silicon
KR1020070033842A 2007-04-05 2007-04-05 Thin film transistor for flat panel display and method for fabricating the same KR100857700B1 (en)

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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09298305A (en) * 1996-05-08 1997-11-18 Semiconductor Energy Lab Co Ltd Thin film transistor and liq. crystal display having such thin film transistor
KR20000014518A (en) * 1998-08-21 2000-03-15 윤종용 Thin film transistor and method for fabricating the same

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09298305A (en) * 1996-05-08 1997-11-18 Semiconductor Energy Lab Co Ltd Thin film transistor and liq. crystal display having such thin film transistor
KR20000014518A (en) * 1998-08-21 2000-03-15 윤종용 Thin film transistor and method for fabricating the same

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