KR100856550B1 - System for manufacturing thin film transistor array - Google Patents

Abstract

A thin film transistor array manufacturing system is provided to reduce a process time by etching an active layer and an ohmic contact layer in a pattern region with an in-situ self dry-etch manner. A load lock chamber(400) supports a substrate transferred from a cassette loading unit. A transfer chamber(402) is installed adjacently to the load lock chamber and includes a transferring space for the substrate transferred from the transfer chamber. One or more capacitively coupled plasma processing apparatus(404) is installed adjacently to the transfer chamber in order to etch a semiconductor layer in an in-situ self dry-etch process while a source electrode, a drain electrode, and a channel part are formed on a substrate including a stacked structure of a gate electrode, a gate insulating layer, the semiconductor layer, and a conductive layer. An inductively coupled plasma processing apparatus(406) strips fully a photoresist used in the in-situ self dry-etch process under an O2 condition.

Description

System for manufacturing thin film transistor array

1A to 1C illustrate a thin film transistor patterning process of a liquid crystal display using a conventional five mask.

2A to 2C are diagrams illustrating a thin film transistor patterning process of a liquid crystal display using a conventional four mask.

3 illustrates a thin film transistor array manufacturing system according to the prior art.

Figure 4 is a plan view of a thin film transistor array manufacturing system according to an embodiment of the present invention.

5 is a perspective view of a thin film transistor array manufacturing system according to an embodiment of the present invention.

6 is a cross-sectional view of a capacitively coupled plasma processing apparatus according to the present invention.

7 is a cross-sectional view of an inductively coupled plasma processing apparatus according to the present invention.

8A to 8D illustrate a thin film transistor patterning process of a liquid crystal display using 4 masks according to the present invention.

9A to 9D are cross-sectional views taken along the line AA ′ of FIGS. 8A to 8D.

The present invention relates to a thin film transistor array manufacturing system, and more particularly, to a system for manufacturing a thin film transistor array of a liquid crystal display device by a four mask process.

In the liquid crystal display (LCD), the manufacturing process of the thin film transistor and the thin film transistor array is one of very important process, which greatly affects the yield as well as the performance of the device.

In general, a process of manufacturing a thin film transistor of a liquid crystal display includes forming a gate electrode, a source / drain electrode, a passivation layer (protective layer), and a pixel layer using a predetermined number of masks.

Typical thin film transistor array manufacturing is performed using a 5 mask process or a 4 mask process.

In the conventional five mask process, a process of forming a gate on a glass substrate using a gate mask, a process of forming an active layer using an active mask, a process of forming source / drain and channel portions using a source / drain mask, and passivation forming a passivation layer (protective layer) using a passivation mask and forming a pixel electrode using a pixel mask.

1A to 1C illustrate a thin film transistor patterning process of a liquid crystal display using a conventional five mask.

Referring to a process of generating a gate and a source / drain in the conventional five mask process, first, the gate electrode 102 is formed on the glass substrate 100 as shown in FIG. 1A through the gate mask.

Thereafter, the gate insulating layer 104, the active layer 106, and the ohmic contact layer 107 are deposited. The gate insulating layer 104, the active layer 106, and the ohmic contact layer 108 are patterned through the active mask as shown in FIG. 1B.

After the patterning, the conductive layer 109 is stacked by sputtering, and the source electrode 112, the drain electrode 114, and the channel portion 110 are formed through the source / drain mask as shown in FIG. 1C.

A four mask process without an active mask has been proposed in place of such a five mask process.

2A to 2C illustrate a thin film transistor patterning process of a liquid crystal display using a conventional four mask.

In the conventional four mask process, the gate electrode 102 is first formed on the glass substrate 100 as shown in FIG. 2A through the gate mask.

Thereafter, the gate insulating layer 104, the active layer 106, the ohmic contact layer 108, and the conductive layer 109 for source / drain formation are stacked.

Next, as shown in FIG. 2B, the gate insulating layer 104, the active layer 106, the ohmic contact layer 108, and the conductive layer 109 are patterned through the source / drain mask. 109 is wet-etched first in a form in which the source and the drain are not separated, and the active layer 106 and the ohmic contact layer 108 are etched through a separate process.

Next, the channel region is opened through photoresist ashing, and the conductive layer 109 and the ohmic contact layer 108 of the channel region are etched to etch the channel portion 110, the source electrode 112, and the drain electrode 114. ).

After the channel portion 110 is formed, the pot resist for source / drain patterning is wet stripped.

At this time, in the conventional four mask process, the dry etching process for forming the channel portion 110 may be performed in the thin film transistor manufacturing system shown in FIG.

FIG. 3 illustrates a dry etching cluster for patterning an electrode and the like, wherein a thin film transistor array manufacturing system according to the prior art includes a load lock chamber 300, a transfer chamber 302, and first to third capacitively coupled plasma chambers. It consists of 304.

The substrate on which the conductive layer 109 is wet etched is transferred to the first to third capacitively coupled plasma chamber 304 through the load lock chamber 300 and the transfer chamber 302, and the first to third capacitively coupled type. The plasma chamber 304 performs dry etching for forming channel portions on the transferred substrate.

However, according to the conventional four mask process, since the conductive layer 109 is wet etched, there is a problem in that the accuracy of the pattern size due to the isotropy of the wet etch is inferior.

In addition, since the etching of the active layer 106 and the ohmic contact layer 108 and the etching for forming channel portions are performed in separate processes in the first to third capacitively coupled plasma chambers 304, there is an inefficient problem. In some cases, the process for opening the channel part after etching of the active layer is performed by wet etching, which causes an inefficient process.

In addition, the conventional four mask process uses hot water rinsing to suppress the occurrence of Al corrosion constituting the conductive layer 109, which not only increases the manufacturing process cost but also moves the substrate from the vacuum equipment to the atmosphere. Therefore, there was a problem of lowering mass productivity of the manufacturing process.

In the present invention, to solve the problems of the prior art as described above, it is proposed a thin film transistor array manufacturing system capable of precise control of the pattern size.

Another object of the present invention is to provide a thin film transistor array manufacturing system that can reduce the etching-related equipment.

Another object of the present invention is to provide a thin film transistor array manufacturing system that can increase the productivity by removing the work in the atmosphere.

Another object of the present invention is to provide a thin film transistor array manufacturing system capable of reducing the number of processes in manufacturing a thin film transistor array.

In order to achieve the above object, a thin film transistor array manufacturing system of a liquid crystal display device, comprising: a load lock chamber for mounting a substrate transferred from a cassette loading portion; A transfer chamber installed adjacent to the load lock chamber and providing a transfer space of a substrate provided from the load lock chamber; And in situ self-drying the semiconductor layer while being formed adjacent to the transfer chamber and forming a source electrode, a drain electrode, and a channel portion on a substrate having a structure in which a gate electrode, a gate insulating film, a semiconductor layer, and a conductive layer are sequentially stacked. A thin film transistor array manufacturing system comprising at least one capacitively coupled plasma processing device for etching.

As the invention allows for various changes and numerous embodiments, particular embodiments will be illustrated in the drawings and described in detail in the written description. However, this is not intended to limit the present invention to specific embodiments, it should be understood to include all modifications, equivalents, and substitutes included in the spirit and scope of the present invention. In describing the drawings, similar reference numerals are used for similar elements.

Terms such as first, second, A, and B may be used to describe various components, but the components should not be limited by the terms. The terms are used only for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be referred to as the second component, and similarly, the second component may also be referred to as the first component. The term and / or includes a combination of a plurality of related items or any item of a plurality of related items.

When a component is referred to as being "connected" or "connected" to another component, it may be directly connected to or connected to that other component, but it may be understood that other components may be present in between. Should be. On the other hand, when a component is said to be "directly connected" or "directly connected" to another component, it should be understood that there is no other component in between.

The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting of the present invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In this application, the terms "comprise" or "have" are intended to indicate that there is a feature, number, step, operation, component, part, or combination thereof described in the specification, and one or more other features. It is to be understood that the present invention does not exclude the possibility of the presence or the addition of numbers, steps, operations, components, components, or a combination thereof.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art. Terms such as those defined in the commonly used dictionaries should be construed as having meanings consistent with the meanings in the context of the related art, and, unless expressly defined in this application, are construed in ideal or excessively formal meanings. It doesn't work.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the following description of the present invention, the same reference numerals will be used for the same means regardless of the reference numerals in order to facilitate the overall understanding.

4 is a plan view of a thin film transistor array manufacturing system according to a preferred embodiment of the present invention, Figure 5 is a perspective view of a thin film transistor array manufacturing system according to a preferred embodiment of the present invention.

As shown in Figs. 4 to 5, the thin film transistor array manufacturing system according to the present invention includes a load lock chamber 400, a transfer chamber 402 and one or more capacitively coupled plasma processing apparatus 404 and inductively coupled plasma. May include a processing device 406.

The load lock chamber 400 is installed at one side of the transfer chamber 402 to intercept the entry and exit of the substrate to be etched.

A cassette loading unit (not shown) is disposed at one side of the load lock chamber 400, and a cassette on which a plurality of substrates are mounted is mounted on the cassette loading unit.

The predetermined transfer robot reciprocates between the cassette and the load lock chamber 400 to transfer the substrate mounted on the cassette to the load lock chamber 400.

Meanwhile, the transfer chamber 402 is coupled to the load lock chamber 400 and the plurality of processing apparatuses 404 and 406 to transfer the substrate transferred to the load lock chamber 400 to the plurality of processing apparatuses.

Although not shown in the drawings, a transfer robot may be provided in the transfer chamber 402, and the transfer robot may perform the transfer process.

Meanwhile, according to an exemplary embodiment of the present invention, the capacitively coupled plasma processing apparatus 404 and the inductively coupled plasma processing apparatus 406 may be simultaneously provided in a single dry etching cluster.

Capacitively Coupled Plasma (CCP) processing apparatus 404 and Inductively Coupled Plasma (ICP) processing apparatus 406 are divided according to the method of applying RF power. RF power is applied to the parallel plate electrodes facing each other to generate a plasma using an RF electric field formed vertically between the electrodes, and the ICP 406 generates the plasma using an induction electric field induced by an RF antenna. This is how you do it.

6 is a cross-sectional view of the capacitively coupled plasma processing apparatus according to the present invention.

As shown in FIG. 6, the capacitively coupled plasma processing apparatus according to the present invention includes an upper electrode 604 connected to a chamber 600 made of anodized aluminum and an RF power source 602 for plasma generation. It includes.

Although not shown in the drawings, the plasma generating RF power source 602 is connected to the upper electrode 604 via an impedance matching unit for preventing power reflection.

The upper electrode 604 may be composed of an assembly including a base electrode, a baffle electrode, and a shower head.

The lower electrode 608 to which the bias generation RF power supply 606 is connected is disposed opposite the upper electrode 604.

The glass substrate 610 is disposed on an upper surface of the lower electrode 608.

Here, the lower electrode 608 includes an electrostatic chuck electrically connected to a DC power supply and turned on / off by a switch, so that the substrate 610 can be adsorbed and held.

Meanwhile, a gas supply means 612 is connected to one side of the upper electrode 604, and the gas supply means 612 supplies a processing gas for etching the substrate placed inside the chamber 600.

As will be described in detail below, the gas supply means 610 according to the present invention sequentially supplies Cl 2 / SF 6, Cl 2 / BCl 3, O 2 / SF 6 and CHF 3 / O 2 to form a source / drain and channel portion.

When the processing gas is supplied to the chamber 600 and RF power is applied, plasma is formed inside the chamber 600 to perform dry etching.

The pumping unit 614 provided at one side of the chamber 600 maintains the inside of the chamber 600 in a vacuum, and discharges the gas remaining in the chamber after the dry etching process as described above.

The capacitively coupled plasma processing apparatus according to the present invention may be a DFCCP RiE (Dual Frequency Capacitively Coupled Plasma Reactive ion Etching) processing apparatus in which the frequency of the plasma generation RF is 27.12 MHz and the frequency of the bias generation RF is 3.2 MHz. It is not limited to this.

7 is a cross-sectional view of an inductively coupled plasma processing apparatus according to the present invention.

The inductively coupled plasma processing apparatus 406 applied to the present invention includes a chamber 700, an RF antenna 710 connected to a plasma generation RF power source 702, and an upper plate for injecting processing gas into the chamber ( 704, a lower electrode 708 connected to the bias generation RF power source 706, a gas supply means 712, and a pumping unit 714.

The inductively coupled plasma processing apparatus 406 includes an RF antenna 710 connected to an RF power source 702 for plasma generation, and generates plasma using an induction electric field induced by the RF antenna 710.

Here, the frequency of the RF applied to the RF antenna is 13.56MHz, the bias frequency RF frequency may be 3.39MHz, but is not limited thereto.

In addition, the inductively coupled plasma processing apparatus 406 may be an HDP ICP RiE (High Density Plasma Inductively Coupled Plasma Reactive ion Etching) apparatus.

According to the present invention, the gas supply means 712 supplies O2 for full stripping the photoresist (photosensitive film) used for the in situ self etching according to the present invention, and in some cases, CHF 3 / O 2 can be supplied to prevent corrosion of the aluminum to be composed.

After the predetermined process is completed, the pumping unit 714 discharges residual gas inside the chamber 700.

8 to 9 will be described in detail the operation of the thin film transistor array manufacturing system according to the present invention.

8A to 8D are views illustrating a thin film transistor patterning process of a liquid crystal display using 4 masks according to the present invention, and FIGS. 9A to 9D are cross-sectional views taken along line AA ′ of FIGS. 8A to 8D. .

The present invention can be applied to the four mask process, and as shown in FIGS. 8A to 9A, the gate electrode 802 is first formed on the substrate 800 through the gate mast.

The substrate 800 may include a transparent insulating substrate such as soda lime glass applied to the liquid crystal display.

In addition, the gate electrode 802 may be formed as a double layer of upper and lower portions of molybdenum / aluminum (Mo / Al) or molybdenum / alminerine (Mo / AlNd).

Next, as shown in FIG. 8B, a laminated structure of the gate insulating film 804, the semiconductor layer 806, and the conductive layer 808 is formed.

Here, the gate insulating layer 804 may be made of silicon nitride (SiNx), and may be preferably formed to have a thickness of 4000 kPa.

The semiconductor layer 806 may include an active layer 900 and an ohmic contact layer 902.

The active layer 900 is for channel formation of the thin film transistor and may be made of intrinsic amorphous Si (i-a-Si).

The active layer 900 may be formed to have a thickness of 1000 to 3000 GPa, preferably 2000 GPa using plasma-enhanced chemical vapor deposition (PECVD).

An electric field is applied to the active layer 900 through the gate insulating film 804 according to the control signal applied to the gate electrode 802, and the active layer 900 on the gate electrode 802 forms a channel according to the control signal. The thin film transistor performs an on / off operation.

The ohmic contact layer 902 is for forming an ohmic contact between the source / drain region of the active layer 900 and the conductive layer 808. For example, doped amorphous silicon (n + a-Si) may be formed. It may be formed to a thickness of 200 kPa to 1,000 kPa, and preferably may be formed to a thickness of about 500 kPa.

The conductive layer 808 is for forming a source / drain electrode. For example, the conductive layer 808 may be formed of a multilayer in which the upper and lower layers are molybdenum / aluminum / molybdenum (Mo / Al / Mo). The conductive layer 808 may be formed by sputtering with an upper Mo of 500 kV to 1500 kPa, a middle Al of 3000 kV to 6000 kPa, and a lower Mo of 200 kV to 1000 kPa.

Thereafter, source and drain electrodes are formed using a source / drain mask.

According to an exemplary embodiment of the present invention, a substrate sequentially stacked on the gate electrode 802, the gate insulating layer 804, the semiconductor layer 806, and the conductive layer 808 may include a load lock chamber 400 and a transfer chamber ( 402 is transferred into the chamber of the capacitively coupled plasma processing apparatus 404.

The capacitively coupled plasma processing apparatus 404 preferentially patterns only the conductive layer 808 using the first photoresist layer 904 through dry etching as shown in FIGS. 8C and 9B. Through this patterning, the lower layer is exposed. In this case, the conductive layer 808 is not separated into a source electrode and a drain electrode.

Here, the first photoresist layer 904 is formed to have a relatively thin portion where the channel portion is formed, which may be implemented by using a slit-like or lattice-shaped exposure mask or a portion of the exposure mask 905 having a semi-transparent portion. . In addition, any method can be used as long as the amount of light can be varied for each part.

Hereinafter, a process performed by the capacitively coupled plasma processing apparatus and the inductively coupled plasma processing apparatus for forming the source / drain electrodes and the channel portion will be described.

(1) first step

When the upper / middle / lower layer of the conductive layer 808 is formed of Mo / Al / Mo, the gas supply means 712 of the capacitively coupled plasma processing apparatus 404 according to the present invention is formed inside the chamber 700. Feed Cl2 / SF2.

After that, the plasma generation RF power source and the bias generation RF power source are 27.12 MHz (6 kWatt), 3.2 MHz (12 kWatt), and the pressure inside the chamber 700 is maintained at 30 mTorr. Etch it.

At this time, the etchant Cl2 / SF2 may be supplied under conditions of about 7000 sccm (Standard Cubic Centimeter per Minute) and 1000 sccccm, respectively.

(2) second process

On the other hand, to dry-etch the middle and lower Al and Mo (Bottom-Mo), the pumping unit 614 removes the upper Mo and discharges the remaining residual gas to the outside of the chamber.

The gas supply means 612 then supplies Cl 2 / BCl 3 into the chamber 700, preferably supplying etchant Cl 2 / BCl 3 at about 2000 sccm, respectively.

In this case, the plasma generation RF power supply and the bias generation RF power supply may be maintained at 27.12 MHz (6 kWatt), 3.2 MHz (12 kWatt), and a pressure of 10 mTorr, respectively.

Meanwhile, although the etching of the conductive layer 808 has been described as being dry, the present invention is not limited thereto and may be included in the scope of the present invention even when the conductive layer 808 is wet etched.

(3) third process

Subsequently, the capacitively coupled plasma processing apparatus 404 processes the first photoresist film 904 by photoresist pull-back ashing to form a second photoresist film 906, as shown in FIG. 9C. . As a result, the channel region 910 of the conductive layer 808 is exposed.

Here, the photoresist ashing is performed by the pumping unit 614 to discharge residual gas after the dry etching of the middle and lower Al and Mo (Bottom-Mo), and the gas supply unit 612 supplies about 1000 sccm of O2 and 300 sccm of SF6. Can be started by.

In this case, the plasma generation RF power supply and the bias generation RF power supply may be maintained at 27.12 MHz (6 kWatt), 3.2 MHz (12 kWatt), and a pressure of 30 mTorr.

(4) fourth process

After the channel region 910 is exposed, the capacitively coupled plasma processing apparatus 404 separates the conductive layer 808 into the source electrode 812 and the drain electrode 814 using the second photosensitive film 906. At the same time, the active layer 900 and the ohmic contact layer 902 of the pattern region 908, which are not covered by the conductive layer 808, are removed, and the active layer 900 of the channel region 910 is exposed.

That is, the capacitively coupled plasma processing apparatus 404 according to the present invention removes the conductive layer 808 and the ohmic contact layer 902 of the channel region 910 by dry etching, and at this time, the pattern region 908. The active layer 900 and the ohmic contact layer 902 may be simultaneously removed by in-situ self etching.

In the capacitively coupled plasma processing apparatus 404 according to the present invention, the etching of the upper Mo of the conductive layer 808 for forming the channel portion 910 is performed under the same conditions as the above-described first process (27.12 MHz (6 kWatt), 3.2). Dual frequency of 12 MHz (12 kWatt), 30 mTorr pressure and about 7000 sccm of Cl2 and 1000 sccm of SF6 etchant feed).

At this time, the in situ self etching of the active layer 900 and the ohmic contact layer 902 in the pattern region 908 simultaneously with the dry etching of the conductive layer 808 is performed under the same condition as removing the upper Mo layer.

(5) fifth process

The etching of Al / Bottom-Mo, which is the middle and lower layers of the conductive layer 808, is performed in the capacitively coupled plasma processing apparatus 404 at 27.12 MHz (6 kWatt) and 3.2 MHz (12 kWatt). It is performed under dual frequency, 10 mTorr pressure and about 2000 sccm Cl2 and 2000 sccm BCl3 conditions.

According to the present invention, in forming the source / drain electrodes and the channel portion, the etching of the active layer / omic contact layer is etched in-situ at the same time as the etching of the channel region, thereby simplifying the process and reducing defects.

In addition, according to the present invention, since all of the above etching processes are made of dry etching having anisotropy, accurate control of the pattern size is possible, which is an accurate pattern such as a full HD TV or a quad HD TV. It can be preferably applied to manufacturing processes in which size control is required.

(6) 6th process

According to the present invention, a post anti-corrosion treatment for preventing Al corrosion of the conductive layer is performed after the etching process. The post-treatment process according to the present invention can be performed in the capacitively coupled plasma processing apparatus 404 under 27.12 MHz (6 kWatt), 3.2 MHz (12 kWatt) dual frequency, 30 mTorr pressure and about 500 sccm CHF3 and 5000 sccm O2 conditions. .

Conventionally, in order to prevent Al corrosion, hot water rinsing should be performed in air by extracting from vacuum equipment, but the post-treatment process according to the present invention is exposed to air because it proceeds in situ after the dry etching process. The problem does not occur.

On the other hand, the post-treatment process may be performed in the inductively coupled plasma processing apparatus 406 according to the present invention. In this case, the gas supply means 712 of the inductively coupled plasma processing apparatus 406 is a processing gas, CHF3. Supply 300scccm O2 to 3000scccm. In this case, the frequency of the plasma generation RF and the bias generation RF may be 13.56 MHz (20 kWatt), 3.39 MHz (5 kWatt), and the pressure inside the chamber may be 10 mTorr.

(7) 7th process

After the post-treatment process is completed, the substrate is transferred to the inductively coupled plasma processing apparatus 406 through the transfer chamber 402, and the inductively coupled plasma processing apparatus 406 is formed of Al by Cl groups remaining in the second photosensitive film 906. In order to prevent corrosion of the second photoresist layer 906 is stripped using O2 plasma.

In order to remove the second photoresist layer 906, the inductively coupled plasma processing apparatus 406 sets the plasma generation RF and the bias generation RF to 13.56 MHz (20 kWatt), 3.39 MHz (5 kWatt), and the pressure inside the chamber to 10 mTorr. Keep it. At this time, the gas supply means 712 supplies O 2 at 3000 sccm.

According to the present invention, since the removal of the second photosensitive film 906 is also performed under vacuum conditions, mass productivity can be guaranteed and manufacturing costs can be reduced.

Preferred embodiments of the present invention described above are disclosed for purposes of illustration, and those skilled in the art will be able to make various modifications, changes, and additions within the spirit and scope of the present invention. Additions should be considered to be within the scope of the following claims.

As described above, according to the present invention, the active layer and the ohmic contact layer present in the pattern region during the source / drain electrode and the channel portion are etched in-situ and self-etched to shorten the process.

In addition, according to the present invention, the etching process for forming the source / drain electrodes and the ashing process for the source / drain patterning may be performed in a dry etching apparatus, thereby increasing productivity.

Claims (11)

In the thin film transistor array manufacturing system of the liquid crystal display device, A load lock chamber for mounting a substrate transferred from the cassette loading portion; A transfer chamber installed adjacent to the load lock chamber and providing a transfer space of a substrate provided from the load lock chamber; The semiconductor layer is in situ self-etched while being formed adjacent to the transfer chamber and forming the source electrode, the drain electrode, and the channel portion on a substrate formed by sequentially stacking a gate electrode, a gate insulating film, a semiconductor layer, and a conductive layer. One or more capacitively coupled plasma processing apparatus; And And a thin film transistor array manufacturing system further comprising an inductively coupled plasma processing apparatus for full stripping the photoresist used in the in-situ dry etching under O 2 conditions. delete The method of claim 1, The capacitively coupled plasma processing apparatus, An upper electrode to which an RF power supply for plasma generation is electrically connected; A lower electrode disposed opposite the upper electrode, to which a bias generation RF power supply is electrically connected, wherein the substrate is placed on an upper surface of the lower electrode; Gas supply means for supplying a first processing gas for dry etching the conductive layer on the substrate placed in the lower electrode into an electrode pattern in which a source electrode and a drain electrode are not separated; And A thin film transistor array manufacturing system comprising a pumping part for discharging a gas after a dry etching process. The method of claim 3, The gas supply means supplies Cl 2 / SF 6 to etch a molybdenum top-Mo of the conductive layer positioned in the channel portion, and the lower aluminum upper layer and molybdenum of the conductive layer positioned in the channel portion. A thin film transistor array manufacturing system for sequentially supplying Cl2 / BCl3 to etch a bottom-Mo. The method of claim 4, wherein And the gas supply means supplies O 2 / SF 6 to pull back ashing the first photoresist film used for the dry etching of the conductive layer. The method of claim 5, The gas supply means includes Cl 2 / SF 6 for etching a molybdenum top-Mo of the conductive layer positioned in the channel portion after the pullback ashing process, and an aluminum intermediate layer of the conductive layer positioned in the channel portion. And a Cl2 / BCl3 for etching the molybdenum sub-layer and a Cl2 / SF6 for etching the semiconductor layer. The method of claim 6, The etching of the conductive layer located in the channel portion is a thin film transistor array manufacturing system using the second photosensitive film opened the channel portion through the pull back ashing process as an etching mask. The method of claim 7, wherein The gas supply means is a thin film transistor array manufacturing system for supplying CHF3 / O2 for the post-treatment process to prevent aluminum corrosion. The method of claim 8, The post-treatment process is a thin film transistor array manufacturing system performed in the inductively coupled plasma processing apparatus. The method of claim 1, The capacitively coupled plasma processing apparatus is a thin film transistor array manufacturing system including a dual frequency capacitively coupled plasma (DFCCP) reactive ion etching (RIE) chamber. The method of claim 1, The inductively coupled plasma processing apparatus includes a HDP ICP High Density Plasma Inductive Coupled Plasma Reactive ion Etching (RIE) chamber.

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