KR100849410B1 - Manufacturing method of capacitor embedded pcb - Google Patents

Abstract

A method for manufacturing a capacitor embedded PCB(Printed Circuit Board) is provided to improve precision of a capacitor by forming an inner electrode and an outer electrode of the capacitor by an additive method. A method for manufacturing a capacitor embedded PCB includes the steps of: manufacturing a capacitor substrate with an inner electrode on one surface of a dielectric layer(S21); aligning a semi-cured insulating layer on one surface of a core layer and aligning the capacitor substrate on the semi-cured insulating layer so that the inner electrode faces the semi-cured insulating layer(S22); and collectively stacking the core layer, the semi-cured insulating layer, and the capacitor substrate(S23). An outer electrode is formed on the other surface of the dielectric layer in the step of manufacturing the capacitor substrate.

Description

Manufacturing method of capacitor embedded PCB {Manufacturing method of capacitor embedded PCB}

The present invention relates to a printed circuit board incorporating a capacitor.

BACKGROUND In recent years, various needs of consumers are increasing in electronic products including portable electronic devices. In particular, multifunctionality, small size, light weight, high speed, low price, increased mobility, real-time contact with the Internet through wireless, and the desire for sophisticated design of consumers put great burdens on making excellent products for developers, designers, and manufacturers. .

This fierce competition leads to competitors launching new models every day, which in turn adds to the burden on those involved. As the functions of the products are diversified, the passive components are relatively increased in preparation for the increase in the number of active components, thereby increasing the volume of the portable terminal.

In general, a large number of active and passive components are mounted on the surface of a circuit board in an electronic device, and a large number of passive components are mounted on a surface in order to facilitate signal transmission between active components in the form of discrete chip capacitors. It is mounted. Embedded printed circuit boards have been developed by many related companies for high-density packaging of electronic systems. Types of passive components embedded in the board include resistors, capacitors, and coils. The size and shape of the embedded components include conventional passive components, thin passive components, film-like film elements made by printing or sputtering, and plating. Plating type and the like. However, the separate passive parts have a limit in meeting the trend of lighter and shorter electronic components, and have a disadvantage in that the cost is increased along with problems in terms of space utilization.

Among passive components embedded in a substrate, many attempts have been made to embed a capacitor of a thick film type (15-25 μm) into a substrate, and many patents have been published for the method and form thereof. In particular, attempts have been made to make the characteristics and forms of electronic systems light and small. There are methods using roll coating, sputtering, sheet lamination, and the like to embed a film-type capacitor into a substrate, but sheet lamination is effective in reducing thickness tolerance and cost.

1 is a manufacturing process diagram of a capacitor-embedded printed circuit board by the sheet lamination method according to the prior art.

As shown in FIG. 1A, internal electrodes 12a and 12b are formed on both surfaces of the core layer 11. In step (b), the coating inks 13a and 13b undergo a planarization process. Subsequently, in step (c), the pair of copper-clad laminates 14a and 14b in which the dielectric layers 142a and 142b and the copper foil layers 141a and 141b are stacked are coated in the dielectric layers 142a and 142b in the coating ink 13a and 13b. Lay towards. In step (d), the copper foil layers 141a and 141b are removed to form the external electrodes 15a and 15b.

In the conventional capacitor-embedded printed circuit board of FIG. 1, when the surfaces of the coating inks 13a and 13b are curved, portions of the dielectric layers 142a and 142b fill the curved portions of the dielectric layers 142a and 142b. The thickness may not be constant, which soon affected the reliability of the capacitor.

In addition, there are a number of techniques for implementing an embedded capacitor. Among them, the decoupling capacitor for stabilizing the power supply does not require a sensitive value for capacitance tolerance. However, in the case of a capacitor for RF matching, the capacitance of the capacitance and the capacitance itself must have a very high tolerance. Recently, there has been increasing interest in a method of implementing embedded capacitors using RCC type capacitor laminates having a relatively good thickness control. An additional process is needed to make the surface on which the raw materials are stacked flat. Structural problems of RCC type embedded capacitor materials, despite the additional process of flattening the laminated surface, a large variation in the thickness of the dielectric layer of the embedded capacitor raw material occurs with respect to the Cu pattern thickness or the resin thickness of the laminated surface, even in the laminated surface. This leads to poor reliability such as delamination. In addition, the tenting method applied to the electrode formation of the capacitor has a limit in reducing the capacitance variation of the entire embedded capacitor due to a large variation in the embedded capacitor electrode due to etching.

An object of the present invention is to provide a method of manufacturing a printed circuit board in which a capacitor can be embedded while maintaining a constant thickness of the dielectric layer.

According to an aspect of the present invention, manufacturing a capacitor substrate having an internal electrode formed on one surface of a dielectric layer, arranging a semi-cured insulating layer on one surface of a core layer, the internal electrode is semi-cured insulation on the semi-cured insulating layer A method of manufacturing a capacitor-embedded printed circuit board is provided, comprising: arranging the capacitor substrate to face in a layer direction, and collectively laminating the core layer, the semi-cured insulating layer, and the capacitor substrate.

The manufacturing of the capacitor substrate may further include forming an external electrode on the other surface of the dielectric layer.

After the batch lamination, the method may further include forming an external electrode on the other surface of the dielectric layer.

According to another aspect of the present invention, a method of manufacturing a pair of capacitor substrates having internal electrodes formed on one surface of a dielectric layer, arranging a semi-cured insulating layer on both surfaces of a core layer, and the internal electrodes on the respective semi-cured insulating layers Arranging the capacitor substrate to face toward the semi-cured insulating layer, and the method of manufacturing a capacitor-embedded printed circuit board comprising the step of laminating the core layer, the semi-cured insulating layer and the capacitor substrate. do.

The manufacturing of the pair of capacitor substrates may further include forming an external electrode on each other surface of the pair of capacitor substrates.

In addition, after the batch lamination, the method may further include forming an external electrode on the other surface of the dielectric layer.

As with the above-mentioned means for solving the above problems, the present invention does not form the internal electrode in the existing core layer, but rather in forming the internal electrode in the core layer by "forming in the dielectric" before laminating the internal / external electrodes in the core layer. Various problems have been eliminated, and the use of a cured insulating layer has the advantage of minimizing the dielectric thickness variation that occurs during core layer deposition.

By manufacturing a printed circuit board in which a capacitor is embedded without loss of a dielectric layer, it is possible to reliably implement a predetermined capacitor capacity. In addition, the accuracy of the capacitor was increased by forming the internal electrode and the external electrode of the capacitor in an additive manner. In addition, the process cost is reduced by omitting the conventional coating ink coating process.

The present invention solves the inherent problems of these RCC type embedded capacitor raw materials, eliminating the flat-coating process for additional laminated surfaces, and also improving the dielectric thickness variation of the embedded capacitor raw materials, The delamination of was solved. Formation of the embedded capacitor electrode was also possible by introducing an additive method, rather than the conventional etching method, to reduce the electrode deviation, thereby reducing the overall capacitance variation of the embedded capacitor (EC).

Hereinafter, an embodiment of a capacitor-embedded printed circuit board according to the present invention will be described in more detail with reference to the accompanying drawings. In describing the present invention with reference to the accompanying drawings, the same or corresponding components may be used. The same reference numerals will be given, and redundant description thereof will be omitted.

2 is a flowchart of a method of manufacturing a capacitor-embedded printed circuit board according to a first embodiment of the present invention, and FIG. 3 is a manufacturing process diagram of a capacitor-embedded printed circuit board according to a first embodiment of the present invention. Referring to FIG. 3, a first capacitor substrate 31, a first dielectric layer 311, a first copper foil 312, a first dry film 313, a first external pattern 314a, and a first internal pattern 314b ), A first external electrode 315a, a first internal electrode 315b, a second capacitor substrate 32, a second dielectric layer 321, a second copper foil 322, a second dry film 323, a second The outer pattern 324a, the second inner pattern 324b, the second outer electrode 325a, the second inner electrode 325b, the core layer 33, the semi-hardened insulating layer 34, the capacitor 35, Capacitor embedded printed circuit board 30 is shown.

S21 is a step of manufacturing a pair of capacitor substrate having an internal electrode formed on one surface of the dielectric layer.

The pair of capacitor substrates of this embodiment are the first capacitor substrate 31 and the second capacitor substrate 32. The first and second capacitor substrates 31 and 32 may be completely mirror-like and have the same shape, but may have different positions at which electrodes or patterns are formed.

The first and second capacitor substrates 31 and 32 and manufacturing processes thereof may be performed as in FIGS. 3A to 3C. The second capacitor substrate 32 may also be manufactured in the same manner as the first capacitor substrate 31. Therefore, it demonstrates centering on the 1st capacitor board | substrate 31. FIG.

In the first capacitor substrate 31, a first dry film 313 is stacked on a copper foil laminated plate having the first copper foil 312 laminated on both surfaces of the first dielectric layer 311 as shown in (a), and a circuit pattern is formed. In consideration of the portion, a portion of the first dry film 313 is removed. The first dielectric layer 311 may be formed of a material such as a ceramic having a suitable dielectric constant as a portion to be a dielectric film of the capacitor later. In this way, the first dry film 313 is laminated on the copper-clad laminate in which the first copper foils 312 are laminated on both surfaces of the first dielectric layer 311, and the exposure and development processes are performed in consideration of the circuit pattern and the portion where the electrodes of the capacitor are to be formed. If the mounting surface (a) is a member of the cross-sectional view. The thickness of the first copper foil 312 is formed thin as a few um. Copper foil can also be etched and formed thinly.

The first dielectric layer 311 may be in a cured state or may be in a semi-cured state. In the cured state, the thickness of the first dielectric layer 311 may be maintained unchanged even after the process is performed, thereby producing a reliable capacitor. On the other hand, the first dielectric layer 311 in a semi-cured state has the advantage of good bending property to prevent cracking occurring during the process.

When the plating is performed in an additive manner as in step (b), the first internal pattern 314b, the first external pattern 314a, the first internal electrode 315b, and the first external electrode 315a are plated. do. Electroplating is generally used for plating, and copper (Cu) is generally used as a metal to be plated.

Thereafter, when the first dry film 313 is removed and soft etching is performed as shown in (c), a portion of the first copper foil 312 is removed to complete the first capacitor substrate 31.

Step S12 is a step of aligning a pair of semi-cured insulating layer on both sides of the core layer, and aligning the capacitor substrate so that the inner electrode toward each semi-cured insulating layer in the direction of the semi-cured insulating layer.

This step is described with reference to Fig. 3D. The semi-hardened insulating layer 34 is symmetrically arranged on both sides of the core layer 33, and a pair of capacitor substrates 31 and 32 are disposed outside.

In particular, the first and second capacitor substrates 31 and 32 are aligned such that the first and second internal electrodes 315b and 325b face the semi-cured insulating layer 34.

The core layer 33 is a layer which gives rigidity to the capacitor-embedded printed circuit board 30, and prepreg is generally used. Prepreg is a combined structure of glass fiber and resin.

The semi-hardened insulating layer 34 is a resin as a main component, so that the core layer 33 and the first and second capacitor substrates 31 and 32 are bonded during the lamination process.

S13 is a step of laminating the core layer, the semi-hardened insulating layer, and the capacitor substrate. Batch lamination refers to the process of laminating by giving a uniform force up and down using a mechanical press. At this time, it is common to apply heat in order to facilitate lamination.

Proceeding to step S13, a capacitor-embedded printed circuit board 30 as shown in FIG. 3 (e) may be manufactured. At this time, since the first and second external electrodes 315a and 325a are already formed in step S11, it is not necessary to form additionally after step S13.

The capacitor embedded printed circuit board 30 on which the capacitor 35 is formed is made by the above-described process in this embodiment. In this case, the first and second dielectric layers 311 and 321 of each capacitor 35 are not deformed during the manufacturing process, thereby ensuring reliability.

On the other hand, the process after step S13 follows the manufacturing process of a general printed circuit board.

4 is a manufacturing process diagram of a capacitor-embedded printed circuit board according to the second embodiment. Referring to FIG. 4, a first capacitor substrate 41, a first dielectric layer 411, a first copper foil 412, a first dry film 413a and 413b, a first external pattern 414a, and a first internal pattern 414b, the first external electrode 415a, the first internal electrode 415b, the second capacitor substrate 42, the second dielectric layer 421, the second copper foil 422, and the second dry films 423a and 423b. ), The second external pattern 424a, the second internal pattern 424b, the second external electrode 425a, the second internal electrode 425b, the core layer 43, the semi-hardened insulating layer 44, and the capacitor ( 45, a capacitor-embedded printed circuit board 40 is shown. The core layer 43, the first dielectric layer 411, and the semi-cured insulating layer 44 may be made of the same or similar material as described in the embodiment of FIG. 3.

4A and 4C illustrate a process of manufacturing a pair of capacitor substrates 41 and 42 having internal electrodes 415b and 425b formed therein, respectively. The first capacitor substrate 41 and the second capacitor substrate 42 have the same manufacturing process. Therefore, in this embodiment, the manufacturing process of the first capacitor substrate 41 will be representatively described.

In the manufacturing process of the first capacitor substrate 41, first, a copper foil laminate in which the first copper foil 412 is laminated on both surfaces of the first dielectric layer 411 is prepared as in (a), and the first copper foil 412 is provided with a first The dry films 413a and 413b are laminated. The first dry films 413a and 413b are photosensitive materials. A portion of the first dry film 413b is removed by an exposure and development process in consideration of a portion where the first internal electrode 415b is to be formed. After the plating in an additive manner, the first internal electrode 415b and the first internal pattern 414b are formed as shown in FIG. 4C.

Thereafter, when the first dry films 413a and 413b are removed, the first capacitor substrate 41 as shown in FIG. 4C is completed.

4D illustrates a step of aligning the core layer 43, the semi-cured insulating layer 44, and the first and second capacitor substrates 41 and 42. As shown in FIG. 4D, the semi-hardened insulating layer 44 and the first and second capacitor substrates 41 and 42 are symmetrically aligned with the core layer 43 at the center. In this case, the first and second internal electrodes 415b and 425b of the first and second capacitor substrates 41 and 42 face the semi-cured insulating layer 44.

4E illustrates a step of collectively stacking the core layer 43, the semi-cured insulating layer 44, and the first and second capacitor substrates 41 and 42. When mechanical presses and heat are applied, the core layer 43 and the first and second capacitor substrates 41 and 42 are laminated by the semi-cured insulating layer 44. At this time, since the semi-hardened insulating layer 44 is a soft material, it is easily deformed during lamination. Accordingly, the first and second dielectric layers 411 and 421 embedded in the first and second capacitor substrates 41 and 42, respectively, are not deformed and the lamination process is performed. Afterwards, as shown in FIG. 4F, when the first and second external electrodes 415a and 425a are formed and the capacitor 45 is formed, the capacitor 45 may be a reliable capacitor 45.

4F illustrates a process of forming the first and second external electrodes 415a and 425a. First and second external electrodes 415a and 425a are formed in the first and second copper foils 412 and 422 not removed in FIG. When the present process is completed, the capacitor 45 is made.

In the embodiment of FIG. 3, the external electrode and the internal electrode are formed at one time, but in the present embodiment, the first and second internal electrodes 415b and 425b in the processes of (a) to (c) in the embodiment of FIG. 4. ) And the first and second external electrodes 415a and 425a are formed in the process (f) of FIG. 4. As such, the reason why the external electrode and the internal electrode are not formed at one time is that the first and second copper foils 412 and 422 shown in FIG. The substrate 41 and the second capacitor substrate 42 are respectively supported.

When the role of the frame is finished, in the step (f), the first and second external electrodes 415a and 425a are formed to complete the capacitor-embedded printed circuit board 40.

5 is a manufacturing flowchart of a capacitor-embedded printed circuit board according to a third embodiment of the present invention, and FIG. 6 is a manufacturing process diagram of a capacitor-embedded printed circuit board according to a third embodiment of the present invention. Referring to FIG. 6, a capacitor substrate 51, a dielectric layer 511, a copper foil 512, a dry film 513, an outer pattern 514a, an inner pattern 514b, an outer electrode 515a, and an inner electrode 515b. ), A core layer 53, a semi-hardened insulating layer 54, a capacitor 55, and a capacitor-embedded printed circuit board 40 are shown.

S51 is a step of manufacturing a capacitor substrate 50 having an internal electrode formed on one surface of the dielectric layer 511, and the process (c) of FIG. 6A corresponds thereto.

A capacitor substrate 51 having an external electrode 515a and an internal electrode 515b is manufactured through the process of FIGS. 6A through 6C.

First, a copper-clad laminate in which copper foils 512 are laminated on both surfaces of the dielectric layer 511 is prepared, and the outer pattern 514a, the inner pattern 514b, the outer electrode 515a, and the inner electrode 515b are formed in an additive manner. Form. In the present embodiment, the external pattern 514a and the external electrode 515a are simultaneously formed when the internal pattern 514b and the internal electrode 515b are formed. However, the external pattern 514a and the external electrode 515a may be formed after the internal pattern 514b and the internal electrode 515b are formed.

S52 aligns the semi-cured insulating layer 54 on one surface of the core layer 53, and the capacitor substrate 51 so that the internal electrode 515b faces the semi-cured insulating layer 54 in the semi-cured insulating layer 54. ).

6 (d) shows a form in which the core layer 53, the semi-cured insulating layer 54, and the capacitor substrate 51 are sequentially arranged. The semi-hardened insulating layer 54 is mainly composed of resin and has a lower hardness than the dielectric layer 511. The prepreg is generally used for the core layer 53.

S53 is a step of collectively laminating the core layer 53, the semi-hardened insulating layer 54, and the capacitor substrate 51. As a result of the batch lamination, a capacitor-embedded printed circuit board 50 as shown in Fig. 6E was manufactured. Capacitor embedded printed circuit board 50 has a capacitor 55 built-in.

In the case of embedding the capacitor 55 in the embodiment of FIG. 6, no deformation of the dielectric layer 511 occurs. This is because the semi-hardened insulating layer 54 is lower in hardness than the dielectric layer 511, and thus naturally deformed during the batch lamination process to serve as an adhesive layer.

7 is a manufacturing process diagram of a capacitor-embedded printed circuit board according to a fourth embodiment of the present invention. Referring to FIG. 7, a capacitor substrate 71, a core layer 72, a semi-cured insulating layer 73, and a capacitor embedded printed circuit board 70 are illustrated.

In the present embodiment, a plurality of semi-cured insulating layers 73 and capacitor substrates 71 are alternately arranged around the core layer 72 and collectively stacked, whereby a capacitor-embedded printed circuit having a plurality of capacitors 75 is built in. The process of manufacturing the board | substrate 70 is illustrated.

Although the preferred embodiments of the present invention have been described above, those skilled in the art may variously modify and modify the present invention without departing from the spirit and scope of the present invention as set forth in the claims below. It will be appreciated that it can be changed.

1 is a manufacturing process diagram of a capacitor-embedded printed circuit board by a sheet lamination method according to the prior art.

2 is a flow chart of a manufacturing method of a capacitor-embedded printed circuit board according to a first embodiment of the present invention.

3 is a manufacturing process diagram of a capacitor-embedded printed circuit board according to the first embodiment of the present invention.

4 is a manufacturing process diagram of a capacitor-embedded printed circuit board according to a second embodiment.

5 is a manufacturing flowchart of a capacitor-embedded printed circuit board according to a third embodiment of the present invention.

6 is a manufacturing process diagram of a capacitor-embedded printed circuit board according to a third embodiment of the present invention.

7 is a manufacturing process diagram of a capacitor-embedded printed circuit board according to a fourth embodiment of the present invention.

<Description of the symbols for the main parts of the drawings>

31: first capacitor substrate 311: first dielectric layer

312: 1st copper foil 313: 1st dry film

314a: first external pattern 314b first internal pattern

315a: first external electrode 315b: first internal electrode

32: second capacitor substrate 321: second dielectric layer

322: 2nd copper foil 323: 2nd dry film

324a: second outer pattern 324b: second inner pattern

325a: second external electrode 325b: second internal electrode

33: core layer 34: semi-hardened insulating layer

35: Capacitor 30: Capacitor-embedded printed circuit board

Claims (6)

Manufacturing a capacitor substrate having internal electrodes formed on one surface of the dielectric layer; Arranging a semi-cured insulating layer on one surface of the core layer, and aligning the capacitor substrate with the inner electrode toward the semi-cured insulating layer in the semi-cured insulating layer; And laminating the core layer, the semi-cured insulating layer, and the capacitor substrate. The method of claim 1, In the manufacturing of the capacitor substrate, Forming an external electrode on the other surface of the dielectric layer further comprising a capacitor embedded printed circuit board. The method of claim 1, After the batch lamination, Forming an external electrode on the other surface of the dielectric layer further comprising a capacitor embedded printed circuit board. Manufacturing a pair of capacitor substrates having internal electrodes formed on one surface of the dielectric layer; Aligning the semi-cured insulating layers on both surfaces of the core layer, and aligning the capacitor substrate with the internal electrodes facing the semi-cured insulating layers in the respective semi-cured insulating layers; And And laminating the core layer, the semi-cured insulating layer, and the capacitor substrate. The method of claim 4, wherein The manufacturing of the pair of capacitor substrates may include And forming an external electrode on each other surface of the pair of capacitor substrates. The method of claim 4, wherein After the batch lamination, And forming an external electrode on the other surface of the dielectric layer.

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