KR100848612B1 - Stak-up reading memory with stak-up read joint metal pcb, stak-up read joint metal pcb for stak-up reading memory and method of manufacturing the same - Google Patents

Abstract

A stack-up reading memory with a stack-up read joint metal PCB(Printed Circuit Board), a stack-up read joint metal PCB for the stack-up reading memory, and a method for manufacturing the same are provided to facilitate transmission of data through the metal PCB with high signal transmission between connection pins of each of memories. A stack-up read joint metal PCB for a stack-up reading memory includes a memory PCBs(10) coupled between a plurality of stacked memories. The memory PCB is composed of a copper foil with a through hole(11) and includes a plurality of pin connection terminals(12) and insulating films(13). The pin connection terminals are in contact with a plurality of pins of the memory. The insulating film insulates between the pin connection terminals. A pin of an upper memory and a pin of a lower memory are electrically connected by the pin connection terminal.

Description

STAB-UP READING MEMORY WITH STAK-UP READ JOINT METAL PCB, STAK-UP READ JOINT METAL PCB FOR STAK-UP READING MEMORY AND METHOD OF MANUFACTURING THE SAME}

1 is a side view of a multilayer memory according to an embodiment of the present invention.

FIG. 2 is a plan view of a memory PC according to FIG. 1.

Figures 3a to 11d is a schematic illustration of the manufacturing process of the memory PC in accordance with an embodiment of the present invention.

12 is a block diagram of a manufacturing method of a memory PC according to an embodiment of the present invention.

<Description of the symbols for the main parts of the drawings>

1: Multi-layer memory 2: Memory

3: pin

10: memory PC ratio 12: pin connection terminal

13: insulating film

The present invention relates to a memory, and more particularly, memory pins of upper and lower sides are electrically connected to each other by pin connection terminals of memory PCs coupled between a plurality of stacked memories. A memory PC ratio for a multilayer memory capable of forming

In general, the memory is mounted on a computer device so that the main processor of the computer device can temporarily store and read data during a calculation operation. It is divided into read-only memory and memory capable of reading and writing. In particular, the capacity of this memory is also associated with the processing power of the computer device.

Modern computer devices are increasingly equipped with internal components to enable superior performance, so that the space that can be installed in the computer device is relatively decreasing. On the other hand, the capacity of the memory must be further increased for high performance processing, but the memory installation space becomes narrower, and thus the overall performance of the computer cannot be improved.

To this end, a high-performance micro integrated circuit is intended to reduce the memory configuration. However, this requires a huge development cost and a research cost, and on the other hand, there is a problem in that it is not easy to develop a memory having an excellent capability.

The present invention for overcoming the above problems is to provide a multi-layered memory in which the memory is stacked in multiple layers to occupy less space but to provide a large capacity memory.

In addition, it is an object to facilitate data transfer by providing a memory PC ratio with good signal transfer between the connection pins of each memory for stacked memories.

Furthermore, the purpose of the present invention is to maintain the stable use of the multilayer memory by filling the insulating film of the memory PC with TGFR resin so as to have excellent insulation, structural stability or heat resistance.

Memory PC ratio for a multilayer memory according to the present invention for achieving the above object is provided with a memory PC ratio (10) coupled between a plurality of stacked memory (2), the memory PC ratio (10) is a through hole inside An insulating film 13 formed of a copper foil on which the 11 is formed and insulated between the plurality of pin connecting terminals 12 to which the plurality of pins 3 of the memory 2 contact, and the pin connecting terminals 12 respectively. ) Is formed, and the pin 3a of the upper memory 2a and the pin 3b of the lower memory 2b are electrically connected to the memory PC ratio 10 by the pin connection terminal 12. It is done.

Accordingly, the insulating layer 13 may be formed of a resin material, and may be formed by filling with TGFR (Track Gap Filled Resin).

In addition, the multilayer memory including the memory PC according to the present invention is provided with a multilayer memory (1) by stacking a plurality of memories (2), including a memory PC (10) between each of the memory (2), The memory PC 10 is formed of a copper foil having a through hole 11 formed therein, and a plurality of pin connection terminals 12 to which a plurality of pins 3 of each of the memories 2 contact each other, and each of the pin connections. An insulating film 13 is formed to insulate between the terminals 12, and the plurality of memories 2 are electrically connected to each other by the pin connecting terminals 12 of the memory PC 10. It is characterized in that it is provided to be connected.

In addition, at least one of an outer circumferential member and an inner circumferential member may be further provided to surround the outer circumference and the inner circumference of the pin connection terminal 12 and the insulating layer 13, and the through hole 11 is the memory. It may be formed in the number of the required number of one or a plurality inside the PC 10.

Furthermore, the manufacturing method of the memory PC for the multilayer memory according to the present invention,

A base material preparing step (S01) of preparing a base material by preparing a support hole 101 for support in a copper plate 10 'of a base plate type copper plate;

The shape of the memory PC 10 according to the position of the memory pin 2 and the shape of the memory 2 for coating and stacking an etching resist 102 on both surfaces of the base plate 10 ′, which is the base material. And a resist pattern forming step (S02) of forming a pattern at a position where the insulating film 13 is formed;

An etching step (S03) of etching the copper plate (10 ') on which an etching resist pattern is formed to pierce the pattern portion (131);

A resist stripping step (S04) of removing the etching resist 102 from the copper plate on which the pattern portion 131 is perforated;

A pattern portion filling step (S05) of filling the perforated pattern portion 131 of the copper plate 10 'with an insulating resin 132 (resin) to form an insulating film 13;

A copper plate polishing step (S06) of removing the resin 132 'protruding from both sides of the copper plate 10' in a state in which the resin 132 is filled in the pattern of the copper plate 10 ';

The insulating layer 133 is applied to both surfaces of the insulating layer 13 of the copper plate 10 'to form a solder mask layer to form an insulating layer 13, and the solder mask of the copper plate 10' is formed. The conductive metal plating layer 122 is formed on the upper surface of the connecting portion 121, which is copper foil, to form the pin connecting terminal 12, which is a conductive metal terminal, and includes an insulating film 13 and the pin connecting terminal 12. 10 ') and the soldering masking step (S07) for manufacturing the memory PC ratio 10 is characterized in that it is provided.

Hereinafter, with reference to the accompanying drawings will be described in detail.

1 is a side view of a multilayer memory according to an embodiment of the present invention, FIG. 2 is a plan view of a memory PC ratio according to FIG. 1, and FIGS. 3A to 11D are memory PC ratios according to an embodiment of the present invention. Figure 12 is a schematic illustration of the manufacturing process of, Figure 12 shows a block diagram for a method of manufacturing a memory PC according to an embodiment of the present invention, respectively.

3B is a cross-sectional view of the portion “A-A '” of FIG. 3A, FIG. 4B is an enlarged view of the portion “B” of FIG. 4A, and FIGS. 4C and 4D are the “B1-B1 ′” of FIG. 4B. Sectional drawing about a part and "B2-B2 '" part.

5B is an enlarged view of portion “C” of FIG. 5A, and FIGS. 5C and 5D are cross-sectional views of portions “C1-C1 ′” and “C2-C2 ′” of FIG. 5B. 6B is an enlarged view of portion “D” of FIG. 6A, and FIGS. 6C and 6D are cross-sectional views of portions “D1-D1 ′” and “D2-D2 ′” of FIG. 6B. FIG. 7B is an enlarged view of portion “E” of FIG. 7A, and FIGS. 7C and 7D are cross-sectional views of portions “E1-E1 ′” and “E2-E2 ′” of FIG. 7B. 8B is an enlarged view of portion “F” of FIG. 8A, and FIGS. 8C and 8D are cross-sectional views of portions “F1-F1 ′” and “F2-F2 ′” of FIG. 8B. FIG. 9B is an enlarged view of portion “G” of FIG. 9A, and FIGS. 9C and 9D are cross-sectional views of portions “G1-G1 ′” and “G2-G2 ′” of FIG. 9B. FIG. 10B is an enlarged view of portion “H” of FIG. 10A, and FIGS. 10C and 10D are cross-sectional views of portions “H1-H1 ′” and “H2-H2 ′” of FIG. 10B. And FIG. 11B is an enlarged view of portion “I” of FIG. 11A.

That is, the memory PC ratio 10 of the present invention multilayer memory 1 includes a memory PC ratio 10 coupled between a plurality of stacked memories 2 as shown in FIGS. 1 to 12.

Accordingly, the memory PC 10 is formed of a copper foil having a through hole 11 formed therein, and a plurality of pin connection terminals 12 contacting a plurality of pins 3 of the memory 2, respectively. The insulating film 13 which insulates between the pin connection terminals 12 was formed. In the accompanying drawings, which illustrate one embodiment, two through holes 11 are illustrated. However, in the case of a square-shaped memory, a single through hole may be formed, and a plurality of through holes 11 may be needed. It is also possible to manufacture in the form provided.

Thus, the pin 3a of the upper memory 2a and the pin 3b of the lower memory 2b are electrically connected to the memory PC ratio 10 by the pin connection terminal 12.

Accordingly, as shown in the side view of FIG. 1, the multilayer memory 1 is provided by stacking a plurality of memories 2, and has a structure in which a memory PC ratio 10 is provided between the memories 2. In other words, various implementations can be realized by configuring the memory PC ratio 10 so as to configure the multilayer memory 1 but electrically connecting the connection pins 3 of the plurality of memories 2 to each other. Thus, the present invention exemplifies the manufacture of the memory PC ratio 10 in the form of a thin metal plate using the copper plate (10 '), so that the memory PC ratio (10) as the pin connection terminal 12 and the insulating film 13 Illustrated as configured.

The memory 2 of the multilayer memory 1 according to the present invention may use a known memory.

In particular, since the memory 2 is configured in a multi-layer, the terminal pins 3 of each memory 2 are stacked and coupled in a state of being electrically connected to each other. It is controlled by the control of the data processor. This configuration generally requires a method of storing and reading data in memory.

As an example, when a computer device wants to store data in a specific memory or read stored data, the memory of each layer divided into layers is assigned a corresponding address number, When the control signal is received, the corresponding memory stores or reads data. To this end, the board or computer device of the multilayer memory may be configured to distinguish the assigned address for each layer of the memory of the multilayer memory. Also, the assigned address of the memory and the memory address transmitted from the controller may be assigned to each memory. Comparable readings may be provided.

This configuration is to provide an embodiment according to the embodiment of the present invention, in addition to the present invention can be realized by using the input and output method of generally known data.

In the present invention, the shapes of the multilayer memory 1 and the memory PC 10 having a plurality of memories 2 are illustrated and described in a rectangular shape, but the present invention is not limited thereto. It is too natural that the form can be realized in various forms known in general.

In the memory PC 10 according to the present invention, the insulating film 13 to insulate each pin connection terminal 12 from each other may be made of a resin material having a low electrical conductivity. In particular, in the transmission of sensitively operated data, electrical isolation from other connection terminals is important for the stability of signal transmission, and the electrical conductivity should be made of a material close to "0". Of course, the material of the insulating film 13 may be provided with a generally known non-conductor.

Therefore, it is preferable to use TGFR (Track Gap Filled Resin) used in the "method of manufacturing a PCB using TGFR" invented by the applicant of the present invention. This is because the memory PC ratio 10 of the present invention, which is formed in a thin film form, is so thin that the insulating film 13 provided between the connection terminals must maintain a stable shape as described above.

Therefore, the TGFR resin developed by the applicant of the present invention is suitable as the insulating film 13 of the memory PC ratio 10 because it has excellent adhesive strength and electrical stability as well as thermal stability.

One example of the composition of the TGFR resin is DGEBPA (DiGlycidyl Ether of BisPhenol A; CAS No. 25068-38-6) 18 to 23 parts by weight, Modified with Cyclo-Epoxy 3 to 7 parts by weight, DBDO (Decabromo diphenyl oxide) 27 to 33 parts by weight, 3 to 7 parts by weight of Antimony Trioxide, 30 to 35 parts by weight of Aluminum Hydrate, and 3 to 7 parts by weight of dicyandiamide.

In another example, the TGFR resin may be composed of a synthetic material including 10 parts by weight of Modified with Cyclo-Epoxy, 50 parts by weight of Aluminum Hydrate, 30 parts by weight of Mineral Water, and 10 parts by weight of other flame retardants and curing agents and pigments.

In addition, the insulating films 13 and the pin connection terminals 12 are wrapped around the outer circumference as necessary to further strengthen the coupling state between the insulating films 13 and the pin connection terminals 12. An outer circumferential member may be provided. The configuration of the outer peripheral member is preferably provided with an insulating resin material, and has an elastic force, so that the insulating film 13 and the pin connection terminals 12 are not disturbed by the outer peripheral member to maintain a stable shape. It may be provided.

In addition, the inner circumferential member may be provided to surround the insulating layer 13 and the pin connection terminal 12 along the edge of the through hole 11. The inner circumferential member is also preferably provided with a resin material having an elastic force, whereby the plurality of insulating films 13 and the pin connection terminal 12 can maintain a stable form without being separated from each other.

In addition, the outer circumferential member and the inner circumferential member may be manufactured so as to form only one or both.

In addition, the memory PC ratio 10 has been exemplified as being composed of a copper plate, and is not limited thereto. If the electrical conductivity is good, a generally known one may be used.

The manufacturing process of the memory PC ratio 10 according to the present invention provided as described above may be manufactured using an etching method using a copper plate as shown in FIGS. 3A to 12.

Looking at the embodiment, as shown in Figures 3a and 3b, first prepares the base material by drilling the support hole 101 for the support in a thin plate-shaped copper plate (10 ') of the base material (preparation step (S01) ).

Etching resist 102 is coated on both surfaces of the base plate 10 ′ prepared as described above, and the shape of the memory 2 and the memory pins 3 to be stacked as shown in FIGS. 4A to 4D. The resist pattern forming step (S02) of forming a pattern in the shape of the memory PC ratio 10 according to the position and the position where the insulating film 13 is formed is performed.

At this time, the shape of the formed pattern is as shown in Figure 4b after the insulating film 13 of the completed memory PC ratio 10 is located, it is a shape forming a long groove in the plane.

Then, the copper plate 10 'on which the etching resist pattern is formed is corroded, and the etching step S03 of drilling the pattern portion 131 as shown in FIGS. 5A to 5D is performed.

Thereafter, the etching resist 102 is removed from the copper plate on which the pattern portion 131 is perforated (resist stripping step S04, see FIGS. 6A to 6D).

As described above, in the state in which the pattern portion 131 is perforated on the copper plate 10 ', the insulating portion 132 (resin) is filled in the perforated pattern portion 131 as shown in FIGS. 7A to 7D. 13) (the pattern portion filling step (S05)). At this time, the insulating resin to be filled is preferably provided with a TGFR resin.

In the state where the resin 132 is filled in the pattern of the copper plate 10 ', the resin 132 filled on both sides of the copper plate 10' protrudes, so that the resin protrudes as shown in FIGS. 8A to 8D. 132 'is removed (copper polishing step S06).

Then, an insulating layer 133 is applied to both surfaces of the insulating layer 13 of the copper plate 10 'to form a solder mask layer as shown in FIGS. 9A to 9D to form the insulating layer 13. To proceed the solder masking step (S07). The solder mask layer according to the solder masking step is formed only on the insulating film 13. Thus, the connection pins 3 of the respective memories 2 are provided to be electrically insulated from each other.

In addition, the solder masking step is a pin connecting terminal which is a conductive metal terminal by forming a conductive metal plating layer 122 as the upper surface of the connecting portion 121 which is a copper foil other than the solder mask of the copper plate 10 ', as shown in FIGS. 10C and 10D. (12) is formed. Then, as shown in Figure 10a to 10d, both sides of the memory PC ratio 10 is to form an even surface. That is, the surface which becomes the pin connection terminal 12 and the insulating film 13 which are in the state connected with the connection pin 3 of the memory 2 is formed.

Thus, the copper plate 10 'divided into the insulating film 13 and the pin connection terminal 12 is cut into a size suitable for the shape of the memory 2. That is, as shown in FIGS. 11A to 11D, each of the memory PCs 10 is cut to include the insulating layer 13 and the pin connection terminal 12, and the shape of the memory PCs 10 is formed by drilling the inside of the memory PCs 10. To form. Thus, after cutting out first along the outer cut line 103, the cut along the inner cut line 104 to manufacture a memory PC ratio (10).

In addition, as described above, by performing the additional process of forming either one of the outer peripheral member or the inner peripheral member or at the same time, if necessary, to make the bonding state of the insulating film 13 and the pin connection terminal 12 more robust It is also preferable.

Thereafter, the memory PCs 10 manufactured as described above are positioned between the stacked memories 2, and the pin connection terminals 12 of the memory PCs 10 are connected to the pins 3 for connection of the respective memorys 2, respectively. The multilayer memory 1 is manufactured by stacking the same according to positions.

1 illustrates that the connection terminal 5 connected to the outside of the multilayer memory 1 is connected to the bottom of the pin connection terminal 12a of the lowest memory PC ratio 10a. It may be provided as a separate contact terminal provided to be connected to the PC (10). The connection terminal 5 is mounted on a board of a multi-layer memory (not shown) or a memory input / output unit of a computer device.

Therefore, since a plurality of memories can be configured in a stacked state for one connection terminal, there is an advantage in that a large capacity memory can be provided without occupying a lot of space in a computer device.

The embodiments of the present invention have been described in detail above, but since the embodiments have been described so that those skilled in the art to which the present invention pertains can easily carry out the present invention, The technical spirit of the present invention should not be interpreted limitedly.

The present invention provided as described above has an effect of providing a memory of a large capacity by providing a multi-layer memory in which the memory is stacked in a multi-layer, taking up less space.

In particular, there is an effect of facilitating the transfer of data by providing a memory PC ratio with a good signal transfer between the connection pins of each memory for stacked memories.

Furthermore, the insulating film of the memory PC is filled with TGFR resin to have excellent insulation, structural stability, heat resistance, and the like, thereby making it possible to stably use the multilayer memory.

Claims (8)

While having a memory PC ratio (10) coupled between a plurality of stacked memory (2), The memory PC 10 is formed of a copper foil having a through hole 11 formed therein, and a plurality of pin connection terminals 12 to which a plurality of pins 3 of the memory 2 contact each other, and each of the pin connections. An insulating film 13 is formed to insulate between the terminals 12, The pin 3a of the upper memory 2a and the pin 3b of the lower memory 2b are electrically connected to each other by the pin connection terminal 12 with respect to the memory PC 10. Memory PC. The method of claim 1, The insulating film 13 is provided with a resin material, the memory PC for multilayer memory, characterized in that formed by filling with TGFR (Track Gap Filled Resin). The method of claim 1, And at least one of an outer circumferential member and an inner circumferential member so as to surround the outer circumference and the inner circumference of the pin connection terminal 12 and the insulating film 13. The method of claim 1, The through hole (11) is a memory PC for the multilayer memory, characterized in that the memory PC (10) is formed in one or a plurality of shapes inward. A plurality of memories (2) are stacked to have a multi-layer memory (1), Between each of the memory 2 is provided including a memory PC ratio 10, The memory PC 10 is formed of a copper foil having a through hole 11 formed therein, and a plurality of pin connecting terminals 12 to which a plurality of pins 3 of each of the memories 2 contact each other, and each of the pins. An insulating film 13 is formed to insulate between the connection terminals 12, The plurality of memories (2) is a multi-layer memory including a memory PC, characterized in that each terminal pin (3) is provided to be electrically connected to each other by the pin connection terminal (12) of the memory PC (10). A base material preparing step (S01) of preparing a base material by preparing a support hole 101 for support in a copper plate 10 'of a base plate type copper plate; The shape of the memory PC 10 according to the position of the memory pin 2 and the shape of the memory 2 for coating and stacking an etching resist 102 on both surfaces of the base plate 10 ′, which is the base material. And a resist pattern forming step (S02) of forming a pattern at a position where the insulating film 13 is formed; An etching step (S03) of corroding the copper plate (10 ') on which an etching resist pattern is formed to pierce the pattern portion (131); A resist stripping step (S04) of removing the etching resist 102 from the copper plate on which the pattern portion 131 is perforated; A pattern portion filling step (S05) of filling the perforated pattern portion 131 of the copper plate 10 'with an insulating resin 132 (resin) to form an insulating film 13; A copper plate polishing step (S06) of removing the resin 132 'protruding from both sides of the copper plate 10' in a state in which the resin 132 is filled in the pattern of the copper plate 10 '; The insulating layer 133 is applied to both surfaces of the insulating layer 13 of the copper plate 10 'to form a solder mask layer to form an insulating layer 13, and the solder mask of the copper plate 10' is formed. The conductive metal plating layer 122 is formed on the upper surface of the connecting portion 121, which is copper foil, to form the pin connecting terminal 12, which is a conductive metal terminal, and includes an insulating film 13 and the pin connecting terminal 12. 10 '), and a soldering masking step (S07) for manufacturing a memory PC ratio (10) by cutting the memory PC for a multilayer memory. The method of claim 6, wherein the memory PC ratio is A method of manufacturing a memory PC for a multilayer memory, characterized in that it is manufactured to have at least one through hole (11). The method of claim 6, At least one portion of the inner and outer circumferences of the formed pinned terminal 12 and the insulating film 13 is surrounded by an insulating material so that the edges of the pinned terminal 12 and the insulating film 13 are firmly coupled. A method of manufacturing a memory PC for a multilayer memory, characterized by further comprising forming an inner peripheral member and an outer peripheral member.

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