KR100844984B1 - Semiconductor device and method for manufacturing the same with recess gate of t shape - Google Patents

Semiconductor device and method for manufacturing the same with recess gate of t shape Download PDF

Info

Publication number
KR100844984B1
KR100844984B1 KR1020050096603A KR20050096603A KR100844984B1 KR 100844984 B1 KR100844984 B1 KR 100844984B1 KR 1020050096603 A KR1020050096603 A KR 1020050096603A KR 20050096603 A KR20050096603 A KR 20050096603A KR 100844984 B1 KR100844984 B1 KR 100844984B1
Authority
KR
South Korea
Prior art keywords
semiconductor device
recess
forming
manufacturing
depth
Prior art date
Application number
KR1020050096603A
Other languages
Korean (ko)
Other versions
KR20070040982A (en
Inventor
김석기
유재선
Original Assignee
주식회사 하이닉스반도체
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 주식회사 하이닉스반도체 filed Critical 주식회사 하이닉스반도체
Priority to KR1020050096603A priority Critical patent/KR100844984B1/en
Publication of KR20070040982A publication Critical patent/KR20070040982A/en
Application granted granted Critical
Publication of KR100844984B1 publication Critical patent/KR100844984B1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1037—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure and non-planar channel
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
    • H01L29/66621—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation using etching to form a recess at the gate location

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

본 발명은 리세스의 깊이를 유지하면서 채널길이를 증가시키는 반도체 소자의 제조방법을 제공하기 위한 것으로, 본 발명은 반도체 기판내에 소정 깊이를 갖고, 상부영역의 폭이 하부영역의 폭보다 큰 리세스패턴을 형성하는 단계, 상기 리세스패턴 상에 게이트패턴을 형성하는 단계, 상기 게이트절연막 상의 상기 리세스패턴에 일부가 매립되고 나머지는 반도체기판의 표면 위로 돌출되는 리세스게이트를 형성하는 단계를 포함하고, 상술한 본 발명은 채널길이 증가 및 이온주입 농도 감소로 소자의 리프레시 특성이 크게 개선되고, 반도체 소자의 고 집적화, 수율 향상, 생산 단가 하락을 가능하게 하는 효과가 있다.The present invention is to provide a method for manufacturing a semiconductor device that increases the channel length while maintaining the depth of the recess, the present invention is a recess having a predetermined depth in the semiconductor substrate, the width of the upper region is larger than the width of the lower region Forming a pattern, forming a gate pattern on the recess pattern, and forming a recess gate partially embedded in the recess pattern on the gate insulating layer and protruding from the surface of the semiconductor substrate. In addition, the present invention described above has the effect of greatly improving the refresh characteristics of the device by increasing the channel length and decreasing the ion implantation concentration, enabling high integration of the semiconductor device, improved yield, and reduced production cost.

리세스게이트, 채널길이, 리프레시특성 Recess gate, channel length, refresh characteristics

Description

티형상의 리세스채널을 갖는 반도체 소자 및 그 제조방법{SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME WITH RECESS GATE OF T SHAPE}A semiconductor device having a tee-shaped recess channel and a method of manufacturing the same {SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME WITH RECESS GATE OF T SHAPE}

도 1a 및 도 1b는 종래기술에 따른 반도체 소자의 제조방법을 설명하기 위한 공정단면도,1A and 1B are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art;

도 2a 내지 도 2f는 본 발명의 바람직한 실시예에 따른 반도체 소자의 제조방법을 설명하기 위한 공정단면도,2A through 2F are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

도 3 및 도 4는 종래기술과 본 발명의 반도체 소자를 비교하기 위한 구조도.3 and 4 are structural diagrams for comparing the semiconductor device of the prior art and the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

21 : 반도체 기판 22 : 산화막21 semiconductor substrate 22 oxide film

23 : 하드마스크 24 : 감광막23: hard mask 24: photosensitive film

25a : 상부영역 26 : 하부영역25a: upper region 26: lower region

27 : 게이트절연막 28 : 게이트패턴27: gate insulating film 28: gate pattern

본 발명은 반도체 소자 및 그의 제조방법에 관한 것으로, 특히 티형상의 리세스채널을 갖는 반도체 소자 및 그의 제조방법에 관한 것이다.TECHNICAL FIELD The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a semiconductor device having a tee-shaped recess channel and a method for manufacturing the same.

반도체 소자의 고집적화에 따라 기존의 게이트배선 형성방법은 게이트를 평탄한 활성영역위에 형성하는 방법으로 패턴크기의 축소화에 의해 게이트 채널길이(Channel Length)가 점점 작아지고, 이온주입농도 증가에 따라 전계(Electric Filed)증가에 기인한 누설전류(Junction Leakage)에 의해 소자의 리프레쉬(Refresh)특성을 확보하기가 어렵다.According to the high integration of semiconductor devices, the conventional gate wiring forming method is to form a gate on a flat active region. As the pattern size is reduced, the gate channel length becomes smaller and the electric field increases as the ion implantation concentration increases. It is difficult to secure the refresh characteristics of the device due to the leakage current due to the increased filed.

이를 개선하기 위해 리세스게이트 공정이 대안으로 적용되고 있다. 상기 리세스게이트 공정을 적용하면 채널길이 증가 및 이온주입농도 감소가 가능하여 소자의 리프래시 특성이 크게 개선된다.To improve this, the recess gate process is applied as an alternative. By applying the recess gate process, the channel length and the ion implantation concentration can be reduced, thereby greatly improving the relash characteristics of the device.

도 1a 및 도 1b는 종래기술에 따른 반도체 소자의 제조방법을 설명하기 위한 공정단면도이다.1A and 1B are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art.

도 1a를 참조하면, 반도체 기판(11) 상에 리세스예정지역이 오픈된 마스크패턴(12)을 형성한다. 이때, 마스크패턴(12)은 패드산화막(12a), 하드마스크 폴리실리콘막(12b) 및 감광막(12c)로 형성된다.Referring to FIG. 1A, a mask pattern 12 having a recessed region to be opened is formed on a semiconductor substrate 11. At this time, the mask pattern 12 is formed of a pad oxide film 12a, a hard mask polysilicon film 12b, and a photosensitive film 12c.

도 1b를 참조하면, 상기 마스크패턴(12)을 식각배리어로 상기 리세스예정지역의 반도체 기판(11)을 식각하여 리세스(13)를 형성한다.Referring to FIG. 1B, the recess 13 is formed by etching the semiconductor substrate 11 in the region to be recessed using the mask pattern 12 as an etching barrier.

상기한 종래기술은 'Ｕ'자 형의 리세스패턴을 형성하는데 리프레시 특성 향상을 위해서는 채널길이를 더 늘려야 한다. 채널 형성을 위한 이온주입 및 리세스 식각 한계로 리세스의 식각깊이를 계속 늘릴 수 없어 채널길이를 늘리는데 한계가 있다.The conventional technique forms a recess pattern having a 'Ｕ' shape, but the channel length should be further increased to improve the refresh characteristics. Due to ion implantation and recess etching limit for channel formation, there is a limit to increase the channel length because the depth of etching of the recess cannot be continuously increased.

본 발명은 상기한 종래기술의 문제점을 해결하기 위해 제안된 것으로, 리세스의 깊이를 유지하면서 채널길이를 증가시키는 반도체 소자의 제조방법을 제공하는데 목적이 있다.The present invention has been proposed to solve the above problems of the prior art, and an object of the present invention is to provide a method for manufacturing a semiconductor device which increases the channel length while maintaining the depth of the recess.

상기 목적을 달성하기 위한 본 발명의 반도체 소자의 제조방법은 반도체 기판내에 소정 깊이를 갖고, 상부영역의 폭이 하부영역의 폭보다 큰 리세스패턴을 형성하는 단계, 상기 리세스패턴 상에 게이트패턴을 형성하는 단계, 상기 게이트절연막 상의 상기 리세스패턴에 일부가 매립되고 나머지는 반도체기판의 표면 위로 돌출되는 리세스게이트를 형성하는 단계를 포함한다.A method of manufacturing a semiconductor device of the present invention for achieving the above object is to form a recess pattern having a predetermined depth in a semiconductor substrate, the width of the upper region is larger than the width of the lower region, the gate pattern on the recess pattern And forming a recess gate partially embedded in the recess pattern on the gate insulating layer and protruding over the surface of the semiconductor substrate.

이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부된 도면을 참조하여 설명하기로 한다.DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

도 2a 내지 도 2f는 본 발명의 바람직한 실시예에 따른 반도체 소자의 제조 방법을 설명하기 위한 단면도이다.2A to 2F are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a preferred embodiment of the present invention.

도 2a에 도시된 바와 같이, 상기 반도체 기판(21) 상에 리세스예정지역이 오픈된 식각배리어패턴(100)을 형성한다. 이때, 식각배리어패턴은 산화막(22), 하드마스크(23) 및 감광막(24)의 순서로 적층하여 형성한다. 상기 하드마스크(23)는 폴리실리콘, SiN, SiON 또는 Amorphous Carbon 중에서 어느 하나를 사용하여 형성할 수 있다.As shown in FIG. 2A, an etch barrier pattern 100 having a recessed region to be opened is formed on the semiconductor substrate 21. In this case, the etching barrier pattern is formed by stacking the oxide film 22, the hard mask 23, and the photosensitive film 24 in order. The hard mask 23 may be formed using any one of polysilicon, SiN, SiON, or Amorphous Carbon.

도 2b에 도시된 바와 같이, 식각배리어패턴(100) 중 감광막(24)의 오픈영역의 폭을 확장(도면부호 'Ｗ')한 후, O2, N2 또는 CO 가스 중에서 어느 하나를 사용한 플라즈마로 식각공정을 실시할 수 있다. 따라서, 하드마스크(23)의 일부가 드러난다. As shown in FIG. 2B, after the width of the open region of the photoresist layer 24 in the etching barrier pattern 100 is extended (reference numeral 'Ｗ'), plasma using any one of O 2 , N 2, or CO gas is used. The etching process can be carried out by Thus, part of the hard mask 23 is revealed.

도 2c에 도시된 바와 같이, 감광막(24)을 식각배리어로 상기 반도체 기판(21)을 식각하여 홈(25)을 형성한다. 이때, 상기 홈을 형성하는 식각공정은 산화막(22)과의 선택비가 높게 실시하되, ICP, DPS, ECR 또는 MERIE 중에서 어느 한 타입의 장비에서 실시한다. 또한, Cl2, O2, HBr 및 Ar 가스를 혼합하여 실시하되 Cl2, HBr 및 Ar을 10∼100sccm의 유량, O2를 1∼20sccm의 유량, 바텀 파워를 50Ｗ∼400Ｗ, 압력을 5∼50mT의 조건으로 1200Å∼1500Å의 깊이가 되도록 식각공정을 실시한다. 따라서, 상기 반도체 기판(21)이 식각되는 것과 동시에 상기 감광막(24)의 확장으로 노출된 상기 하드마스크(23)가 식각되어 상기 산화막(22)이 노출된다. As shown in FIG. 2C, the semiconductor substrate 21 is etched using the photoresist film 24 as an etching barrier to form the groove 25. In this case, the etching process for forming the groove is performed with a high selectivity with respect to the oxide film 22, but is carried out in any one type of equipment of ICP, DPS, ECR or MERIE. In addition, Cl 2 , O 2 , HBr and Ar gas are mixed to perform, but the flow rate of Cl 2 , HBr and Ar is 10 to 100 sccm, the flow rate of O 2 is 1 to 20 sccm, the bottom power is 50 kPa to 400 kPa and the pressure is 5 to 5. The etching process is performed to a depth of 1200 mW to 1500 mW under a condition of 50 mT. Accordingly, the hard mask 23 exposed by the expansion of the photoresist layer 24 is simultaneously etched while the semiconductor substrate 21 is etched to expose the oxide layer 22.

도 2d에 도시된 바와 같이, 상기 감광막(24)과 상기 홈(25) 형성 후 노출된 산화막(22)을 제거하여 홈의 어깨부분을 노출시킨다. As shown in FIG. 2D, the shoulder of the groove is exposed by removing the exposed oxide film 22 after the photosensitive film 24 and the groove 25 are formed.

도 2e에 도시된 바와 같이, 상기 산화막(22) 및 하드마스크(23)를 식각배리어로 반도체 기판(21)을 식각한다. 이때, 상기 반도체 기판(21)의 식각으로 홈(25)의 어깨부분이 확장 식각되어 리세스패턴의 상부영역(25a)이 형성되고, 상기 홈(25)의 바닥부분이 식각되어 리세스패턴의 하부영역(26)이 형성된다. 상기 하부영역(26)은 1200Å∼1500Å의 깊이로 식각하여 총 리세스패턴의 깊이는 2400Å∼3000Å의 깊이가 될 수 있다. 따라서, 리세스패턴(25a,26)은 상부영역(25a)과 하부영역(26)으로 구성되는 'Ｔ'형상이 된다. 여기서, 상부영역(25a)은 하부영역(26)에 비해 폭이 2배 더 넓다.As illustrated in FIG. 2E, the semiconductor substrate 21 is etched using the oxide film 22 and the hard mask 23 as an etching barrier. At this time, the shoulder portion of the groove 25 is etched by the etching of the semiconductor substrate 21 to form an upper region 25a of the recess pattern, and the bottom portion of the groove 25 is etched to form the recess pattern. Lower region 26 is formed. The lower region 26 may be etched to a depth of 1200 Å to 1500 Å so that the total recess pattern may have a depth of 2400 Å to 3000 Å. Accordingly, the recess patterns 25a and 26 have a 'T' shape formed of the upper region 25a and the lower region 26. Here, the upper region 25a is twice as wide as the lower region 26.

도 2f에 도시된 바와 같이, 상기 리세스패턴(25a,26)을 포함하는 반도체 기판(21) 상에 게이트절연막(27)을 형성한다. 이후에, 상기 게이트절연막(27)상의 상기 리세스패턴(25a,26)에 일부가 매립되고 나머지는 반도체기판의 표면 위로 돌출되는 리세스게이트(28)를 형성한다. 상기 리세스게이트(28)는 게이트 배선막(28a), 게이트메탈(28b) 및 게이트 하드마스크 질화막(28c)으로 형성된다. As shown in FIG. 2F, a gate insulating layer 27 is formed on the semiconductor substrate 21 including the recess patterns 25a and 26. Subsequently, a portion of the recess patterns 25a and 26 on the gate insulating layer 27 are buried, and a recess gate 28 protruding from the surface of the semiconductor substrate is formed. The recess gate 28 is formed of a gate wiring film 28a, a gate metal 28b, and a gate hard mask nitride film 28c.

도 3 및 도 4는 종래기술과 본 발명의 반도체 소자를 비교하기 위한 구조도 이다. 3 and 4 are structural diagrams for comparing the prior art and the semiconductor device of the present invention.

도 3은 종래기술에 따른 반도체 소자의 구조도이고, 도 4는 본 발명의 바람직한 실시예에 따른 반도체 소자의 구조도이다.3 is a structural diagram of a semiconductor device according to the prior art, and FIG. 4 is a structural diagram of a semiconductor device according to a preferred embodiment of the present invention.

도 3 및 도 4를 참조하면, 본 발명의 리세스 깊이(d2)는 종래 'Ｕ'자형의 리 세스 깊이(d1)와 같고, 본 발명의 리세스채널(CH2)은 종래 'Ｕ'자형의 리세스채널(CH1)보다 더 길다. 즉, 같은 깊이로 더 많은 채널길이를 확보할 수 있다.3 and 4, the recess depth (d 2) of the present invention is equal to the recess depth (d 1) of the conventional 'U' shaped, recessed channel (CH 2) a conventional 'U of the present invention It is longer than the recessed channel CH 1 . That is, more channel lengths can be secured with the same depth.

상기한 본 발명은, 하부영역보다 폭이 큰 상부영역을 갖는 리세스패턴을 형성하여 종래의 리세스게이트와 같은 깊이를 유지하면서 채널길이를 증가시키는 장점이 있다.The present invention has the advantage of increasing the channel length while maintaining the same depth as the conventional recess gate by forming a recess pattern having an upper region wider than the lower region.

본 발명의 기술 사상은 상기 바람직한 실시예들에 따라 구체적으로 기록되었으나, 상기한 실시예는 그 설명을 위한 것이며, 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical spirit of the present invention has been specifically recorded in accordance with the above-described preferred embodiments, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

상술한 본 발명에 의한 반도체 소자의 제조방법은 채널길이 증가 및 이온주입 농도 감소로 소자의 리프레시 특성이 크게 개선되고, 반도체 소자의 고 집적화, 수율 향상, 생산 단가 하락을 가능하게 하는 효과가 있다.The method for manufacturing a semiconductor device according to the present invention described above has the effect of greatly improving the refresh characteristics of the device by increasing the channel length and decreasing the ion implantation concentration, and enabling high integration of the semiconductor device, improved yield, and reduced production cost.

Claims (14)

반도체 기판;Semiconductor substrates; 상기 반도체 기판내에 소정 깊이를 갖고 형성되며, 상부영역의 폭이 하부영역의 폭보다 큰 리세스패턴;A recess pattern formed in the semiconductor substrate with a predetermined depth and having a width of an upper region greater than a width of a lower region; 상기 리세스패턴 상의 게이트절연막; 및A gate insulating film on the recess pattern; And 상기 게이트절연막 상의 상기 리세스패턴을 매립하면서 상기 반도체기판의 표면 위로 돌출되는 형상의 리세스게이트Recess gates protruding on the surface of the semiconductor substrate while filling the recess patterns on the gate insulating layer 를 포함하는 반도체 소자.Semiconductor device comprising a. 제 1항에 있어서,The method of claim 1, 상기 리세스패턴은 Ｔ 모양인 것을 특징으로 하는 반도체 소자.The recess pattern is a semiconductor device, characterized in that the T-shape. 제 1항에 있어서,The method of claim 1, 상기 상부영역의 폭이 하부영역의 폭보다 2배인 것을 특징으로 하는 반도체 소자.And the width of the upper region is twice the width of the lower region. 제 1항에 있어서,The method of claim 1, 상기 상부영역의 깊이는 하부영역의 깊이와 같은 것을 특징으로 하는 반도체 소자.And the depth of the upper region is equal to the depth of the lower region. 제 1항에 있어서,The method of claim 1, 상기 리세스패턴은 상부영역이 1200Å∼1500Å, 하부영역이 1200Å∼1500Å의 깊이로 형성되어, 상부영역 및 하부영역이 적층된 총 리세스패턴의 깊이는 2400Å∼3000Å인 것을 특징으로 하는 반도체 소자.The recess pattern is a semiconductor device, characterized in that the upper region is formed to a depth of 1200Å to 1500Å, the lower region is 1200Å to 1500Å, and the depth of the total recess pattern in which the upper region and the lower region are stacked is 2400Å to 3000Å. 반도체 기판내에 소정 깊이를 갖고, 상부영역의 폭이 하부영역의 폭보다 큰 리세스패턴을 형성하는 단계;Forming a recess pattern having a predetermined depth in the semiconductor substrate and having a width of the upper region greater than that of the lower region; 상기 리세스패턴 상에 게이트절연막을 형성하는 단계; 및Forming a gate insulating film on the recess pattern; And 상기 게이트절연막 상의 상기 리세스패턴을 매립하면서 상기 반도체기판의 표면 위로 돌출되는 리세스게이트를 형성하는 단계Forming a recess gate which protrudes over the surface of the semiconductor substrate while filling the recess pattern on the gate insulating layer; 를 포함하는 반도체 소자의 제조방법.Method of manufacturing a semiconductor device comprising a. 제 6항에 있어서,The method of claim 6, 상기 리세스패턴을 형성하는 단계는,Forming the recess pattern, 반도체 기판상에 리세스예정지역이 오픈된 산화막, 하드마스크 및 감광막의 순서로 적층된 식각배리어 패턴을 형성하는 단계;Forming an etch barrier pattern stacked on the semiconductor substrate in an order of an oxide film, a hard mask, and a photoresist having an opening to be recessed; 상기 감광막의 오픈영역의 폭을 확장하는 단계;Extending the width of the open area of the photoresist film; 상기 폭이 확장된 감광막을 식각배리어로 반도체 기판을 식각하여 홈을 형성하는 단계;Forming a groove by etching the semiconductor substrate using the photosensitive film having an extended width as an etching barrier; 상기 감광막 및 홈의 어깨부분에 드러난 산화막을 선택적으로 제거하는 단계; 및Selectively removing the oxide film on the shoulder of the photosensitive film and the groove; And 상기 하드마스크 및 산화막을 식각배리어로 홈의 측벽을 식각하여 상기 리세스패턴의 상부영역을 형성하고, 동시에 상기 홈의 바닥부분를 식각하여 하부영역을 형성하는 단계; 및Etching the sidewalls of the grooves using the hard mask and the oxide layer as an etch barrier to form an upper region of the recess pattern, and simultaneously forming a lower region by etching the bottom portion of the groove; And 를 포함하는 반도체 소자의 제조방법.Method of manufacturing a semiconductor device comprising a. 제 7항에 있어서,The method of claim 7, wherein 상기 감광막의 오픈영역의 확장은 플라즈마식각으로 진행하는 것을 특징으로 하는 반도체 소자의 제조방법.The method of manufacturing a semiconductor device, characterized in that the expansion of the open region of the photoresist film is performed by plasma etching. 제 8항에 있어서,The method of claim 8, 상기 식각공정은,The etching process, O2, N2 또는 CO 가스 중에서 어느 하나를 사용한 플라즈마로 실시하는 것을 특징으로 하는 반도체 소자의 제조방법.A method for manufacturing a semiconductor device, characterized by performing plasma using any one of O 2 , N 2 or CO gas. 제 7항에 있어서,The method of claim 7, wherein 상기 홈을 형성하는 단계에서,In the step of forming the groove, 상기 반도체 기판의 식각은 상기 산화막과의 선택비가 높게 실시하는 것을 특징으로 하는 반도체 소자의 제조방법.The etching of the semiconductor substrate is a manufacturing method of a semiconductor device, characterized in that the selectivity with the oxide film is high. 제 10항에 있어서,The method of claim 10, 상기 홈을 형성하는 단계에서,In the step of forming the groove, 상기 식각공정은 ICP, DPS, ECR 또는 MERIE 중에서 어느 한 타입의 장비로 실시하되 Cl2, O2, HBr 및 Ar 가스를 혼합하여 실시하는 것을 특징으로 하는 반도체 소자의 제조방법.The etching process is performed by any one type of equipment of ICP, DPS, ECR or MERIE, the manufacturing method of a semiconductor device, characterized in that carried out by mixing Cl 2 , O 2 , HBr and Ar gas. 제 11항에 있어서,The method of claim 11, 상기 홈을 형성하는 단계에서,In the step of forming the groove, 상기 식각공정은 Cl2, HBr 및 Ar을 10∼100sccm의 유량, O2를 1∼20sccm의 유량, 바텀 파워를 50Ｗ∼400Ｗ, 압력을 5∼50mT로 실시하는 것을 특징으로 하는 반도체 소자의 제조방법.The etching process is a method for manufacturing a semiconductor device, characterized in that the flow of Cl 2 , HBr and Ar 10 to 100 sccm, O 2 1 to 20 sccm, bottom power 50 kPa to 400 kPa, pressure 5 to 50 mT . 제 6항 내지 제 12항 중 어느 한 항에 있어서,The method according to any one of claims 6 to 12, 상기 상부영역은 1200Å∼1500Å, 상기 하부영역은 1200Å∼1500Å의 깊이로 형성하여, 상기 리세스패턴은 2400Å∼3000Å의 깊이가 되도록 형성하는 것을 특징으로 하는 반도체 소자의 제조방법.Wherein the upper region is formed at a depth of 1200 GPa to 1500 GPa and the lower region is at a depth of 1200 GPa to 1500 GPa, and the recess pattern is formed to have a depth of 2400 GPa to 3000 GPa. 제 7항에 있어서,The method of claim 7, wherein 상기 하드마스크는 폴리실리콘, SiON 또는 SiN 중에서 어느 하나로 형성하는 것을 특징으로 하는 반도체 소자의 제조방법.The hard mask is a semiconductor device manufacturing method, characterized in that formed of any one of polysilicon, SiON or SiN.
KR1020050096603A 2005-10-13 2005-10-13 Semiconductor device and method for manufacturing the same with recess gate of t shape KR100844984B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020050096603A KR100844984B1 (en) 2005-10-13 2005-10-13 Semiconductor device and method for manufacturing the same with recess gate of t shape

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020050096603A KR100844984B1 (en) 2005-10-13 2005-10-13 Semiconductor device and method for manufacturing the same with recess gate of t shape

Publications (2)

Publication Number Publication Date
KR20070040982A KR20070040982A (en) 2007-04-18
KR100844984B1 true KR100844984B1 (en) 2008-07-09

Family

ID=38176513

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020050096603A KR100844984B1 (en) 2005-10-13 2005-10-13 Semiconductor device and method for manufacturing the same with recess gate of t shape

Country Status (1)

Country Link
KR (1) KR100844984B1 (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20050024868A (en) * 2003-09-05 2005-03-11 삼성전자주식회사 Method for fabricating recess type transistor and transistor structure therefor

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20050024868A (en) * 2003-09-05 2005-03-11 삼성전자주식회사 Method for fabricating recess type transistor and transistor structure therefor

Also Published As

Publication number Publication date
KR20070040982A (en) 2007-04-18

Similar Documents

Publication Publication Date Title
KR101113794B1 (en) Method for fabricating semiconductor integrated circuit device
KR100744068B1 (en) Method for fabricating transistor of semiconductor device
KR100707803B1 (en) Method for fabricating the same of semiconductor device with recess gate
KR100700332B1 (en) Method for fabricating the same of semiconductor device with recess gate of flask shape
KR100744658B1 (en) Method for fabricating the same of semiconductor device with recess gate of flask shape
KR100628378B1 (en) Method for fabricating the same of semiconductor device with recess gate
KR100691011B1 (en) Method of manufacturing semiconductor device
US7575974B2 (en) Method for fabricating semiconductor device including recess gate
KR100844984B1 (en) Semiconductor device and method for manufacturing the same with recess gate of t shape
KR100844930B1 (en) Method for fabricating the same of semiconductor device with recess gate of flask shape
US20090035916A1 (en) Method for manufacturing semiconductor device having fin gate
KR20070003136A (en) Semiconductor device with recess gate and method for manufacturing the same
KR100799133B1 (en) Method for manufacturing recess gate in semiconductor device
KR100825023B1 (en) Method for fabriaciting semiconductor device with recess gate
KR100960932B1 (en) Method of manufacturing semiconductor device
KR100792355B1 (en) Method for manufacturing the semiconductor device with top round recess-gate pattern
KR100838398B1 (en) Method for fabricating recess gate in semiconductor device
KR100939112B1 (en) Transistor having multi-plane channel and method for forming the same
KR20070087329A (en) Method for fabricating the same of semiconductor device with recess gate of flask shape
KR100672771B1 (en) Method for manufacturing semiconductor device
KR20060113270A (en) Method for manufacturing semiconductor device using recess process
KR20090035146A (en) Method of manufacturing a memory device
KR20060113265A (en) Method for manufacturing semiconductor device using recess gate process
KR20060087876A (en) Method for manufacturing semiconductor device with recess gate
KR20060035329A (en) Method for forming gate of semiconductor device

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E902 Notification of reason for refusal
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
LAPS Lapse due to unpaid annual fee