KR100835280B1 - Semiconductor integrated circuit devices having upper pattern aligning lower pattern with the lower pattern being molded by semiconductor substrate and methods of forming the same - Google Patents

Abstract

A semiconductor integrated circuit device having an upper pattern aligned with a lower pattern to be molded on a semiconductor substrate and a method for forming the same are provided to connect the upper pattern and the lower pattern with each other by using an active region and/or an isolation layer. A semiconductor substrate(3) includes an active region(6). An upper pattern(56) is formed on a predetermined region of the semiconductor substrate. The upper pattern is protruded from an upper surface of the active region and is extended toward a lower part of the active region. A lower pattern(36) is positioned under the upper surface of the active region. The lower pattern includes a buried plug(29) connected to the upper pattern through a predetermined region of the semiconductor substrate, and a buried capping pattern(34) protruded from the upper surface of the active region in order to surround the upper pattern. The upper patterns have different lengths on the buried plug.

Description

Semiconductor Integrated Circuit Devices Having Upper Pattern Aligning Lower Pattern With The Lower Pattern Being Molded By Semiconductor Substrate And Methods Of Forming The Same }

1 is a layout view showing a semiconductor integrated circuit device according to the present invention.

FIG. 2 is a cross-sectional view illustrating a semiconductor integrated circuit device taken along cut lines II ′, II-II ′, and III-III ′ of FIG. 1.

3 to 7 are cross-sectional views illustrating a method of forming a semiconductor integrated circuit device, each taken along cut lines I-I ', II-II' and III-III 'of FIG.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor integrated circuit devices and methods of forming the same, and more particularly, to semiconductor integrated circuit devices and methods of forming the same, having an upper pattern aligned with a lower pattern molded into a semiconductor substrate.

Typically, semiconductor integrated circuit devices have individual elements disposed on a semiconductor substrate and wiring patterns that electrically connect the elements. The wiring patterns may be located at the same level or at different levels on the semiconductor substrate to facilitate electrical operation of individual devices. To this end, the wiring patterns may be directly in contact with each other or may be located around individual elements with a design rule applied to a semiconductor integrated circuit device.

However, the wiring patterns may not directly contact each other when a selected one of the patterns is molded into the semiconductor substrate. This is because the semiconductor substrate has an active region and a device isolation film. That is, when the selected one wiring pattern is disposed in the device isolation layer and / or the active region, the rest of the wiring patterns should be aligned with the selected one wiring pattern, the device isolation layer and / or the active region at the same time. Therefore, the wiring patterns may contact the semiconductor substrate through the active region and / or the device isolation layer to reduce electrical characteristics of individual devices.

The wiring patterns (= gate electrode and wiring) are disclosed by Taku Umebayashi in US Patent No. 7,087,956. According to US Patent No. 7,087,956, a semiconductor substrate having a DRAM region and a logic region is prepared. Gate electrodes are disposed on the semiconductor substrate in the logic region. In addition, other gate electrodes are disposed on the semiconductor substrate in the DRAM region. An interlayer insulating film is disposed on the semiconductor substrate to cover the gate electrodes. Extraction electrodes penetrating the interlayer insulating film and contacting the gate electrodes are disposed.

However, the gate electrodes are disposed in the active region and / or the device isolation layer in the DRAM region. In detail, one of the gate electrodes of the DRAM region is formed over the active region and the device isolation layer, and the other of the gate electrodes of the DRAM region is formed in the active region. At this time, one of the gate electrodes of the DRAM region corresponds to the selected extraction electrode. The selected extraction electrode is formed on one of the gate electrodes of the DRAM region in consideration of an alignment margin between the active region, the device isolation layer, and one of the gate electrodes of the DRAM region. Accordingly, the selected extraction electrode may connect one of the gate electrodes of the DRAM region to the semiconductor substrate through the active region and / or the device isolation layer when the semiconductor manufacturing environment is poor.

SUMMARY OF THE INVENTION The present invention provides a semiconductor integrated circuit device having an upper pattern which arranges an active region and / or a device isolation layer on a semiconductor substrate and molds the lower pattern into the active region and / or the device isolation layer and aligns the pattern. There is.

Another object of the present invention is to provide a method of forming a semiconductor integrated circuit device capable of simply contacting an upper pattern with a lower pattern surrounded by an active region and / or an isolation layer in a semiconductor substrate.

In order to realize the above technical problems, the present invention provides semiconductor integrated circuit devices having a top pattern aligned with a bottom pattern molded into a semiconductor substrate, and methods of forming the same.

These semiconductor integrated circuit devices include a semiconductor substrate having an active region. An upper pattern is disposed in a predetermined region of the semiconductor substrate. The upper pattern protrudes upward from the top of the active area and extends downward from the top of the active area. A lower pattern is disposed below the top surface of the active region. The lower pattern has a buried plug in contact with the upper pattern through a predetermined region of the semiconductor substrate, and a buried capping pattern protruding from an upper surface of the active region so as to be disposed on the buried plug to surround the upper pattern. The upper pattern is formed to have different widths on the buried plug.

The semiconductor integrated circuit devices include a semiconductor substrate having an isolation layer. An upper pattern is disposed in a predetermined region of the semiconductor substrate. The upper pattern protrudes upward from the upper surface of the device isolation layer and extends downward from the upper surface of the device isolation layer. A lower pattern is disposed below the upper surface of the device isolation layer. The lower pattern may include a buried plug that is surrounded by an upper pattern to contact the upper pattern through a predetermined region of the semiconductor substrate, and a buried capping pattern that protrudes from an upper surface of the device isolation layer so as to be positioned on the buried plug to surround the upper pattern. The upper pattern is formed to have the same width on the buried plug.

The semiconductor integrated circuit devices include a semiconductor substrate having an active region and a device isolation film. The device isolation layer is formed to surround the active region. First and second upper patterns are respectively disposed in predetermined regions of the semiconductor substrate. The first upper pattern each protrudes upward from the top of the active region and extends downward from the top of the active region. The second upper pattern protrudes upward from an upper surface of the device isolation layer and extends downward from an upper surface of the device isolation layer. A first lower pattern is positioned below the top surface of the active region. The first lower pattern protrudes from an upper surface of the active region to be positioned on the first buried plug to contact the first upper pattern through one of predetermined regions of the semiconductor substrate, and to surround the first upper pattern. To have a first buried capping pattern. A second lower pattern is disposed below the upper surface of the device isolation layer. The second lower pattern may be surrounded by a second upper pattern through the remaining area of the semiconductor substrate to contact the second upper pattern, and the second isolation pattern may be disposed on the second plug to surround the second upper pattern. And a second buried capping pattern protruding from the top surface. The first upper pattern is formed to have different widths on the first buried plug. The second upper pattern is formed to have the same width on the second buried plug.

The forming methods include preparing a semiconductor substrate having an active region. A trench is formed in the active region. A lower pattern is formed in the trench. The bottom pattern has a buried plug and a buried capping pattern stacked in turn and the buried capping pattern is formed to protrude from an upper surface of an active region defining a trench. An interlayer insulating film is formed on the active region to cover the lower pattern. Connection holes are formed in the interlayer insulating film. The connection hole is formed to expose the buried plug and the active area around the buried plug. An upper pattern is formed to fill the connection hole.

The forming methods include preparing a semiconductor substrate having an element isolation film. A trench is formed in the device isolation layer. A lower pattern is formed in the trench. The lower pattern has a buried plug and a buried capping pattern that are sequentially stacked, and the buried capping pattern is formed to protrude from an upper surface of the device isolation layer defining a trench. An interlayer insulating film is formed on the device isolation layer to cover the lower pattern. Connection holes are formed in the interlayer insulating film. The connection hole is formed to expose the buried plug and the device isolation layer around and under the buried plug. An upper pattern is formed to fill the connection hole.

The forming methods include preparing a semiconductor substrate having an active region and a device isolation film. The device isolation layer is formed to surround the active region. First and second trenches are formed in the active region and the device isolation layer, respectively. First and second lower patterns are formed in the first and second trenches, respectively. The first and second lower patterns each have a first buried plug and a first buried capping pattern stacked in turn, and a second buried plug and a second buried capping pattern stacked in turn. The first and second buried capping patterns are formed to protrude from upper surfaces of the active region and the device isolation layer, respectively. An interlayer insulating layer is formed on the active region and the device isolation layer to cover the first and second lower patterns. First and second connection holes are formed in the interlayer insulating film. The first connection hole is formed to expose the first buried plug and the active region around the first buried plug. The second connection hole is formed to expose the second buried plug and the device isolation layer around and under the second buried plug. First and second upper patterns may be formed to fill the first and second connection holes, respectively.

Now, semiconductor integrated circuit devices having an upper pattern aligned with a lower pattern molded into a semiconductor substrate of the present invention will be described in more detail with reference to the accompanying reference drawings.

1 is a layout view showing a semiconductor integrated circuit device according to the present invention, and FIG. 2 is a cross-sectional view showing the semiconductor integrated circuit device taken along cut lines I-I ', II-II' and III-III 'of FIG. .

1 and 2, a semiconductor integrated circuit device 60 according to the present invention includes a semiconductor substrate 3 having an isolation layer 9 and an active region 6. The active region 6 may be formed in the semiconductor substrate 3 to be surrounded by the device isolation layer 9. Buried plugs 29 are disposed in predetermined regions of the semiconductor substrate 3, respectively, as shown by cutting line I-I '. One of the buried plugs 29 may be formed to be molded into the device isolation layer 9 and the active region 6. The remaining plugs 29 may be formed to be molded into the device isolation layer 9. The device isolation layer 9 may be an insulating layer. The buried plugs 29 may be a conductive material. The buried plugs 29 may be gates. The buried plugs 29 may be individual elements and / or circuit wiring other than gates well known to those skilled in the art.

Buried capping patterns 34 are disposed on the buried plugs 29 as shown in cut lines II-II 'and III-III', respectively. The buried capping patterns 34 may be formed to protrude upward from the top surfaces S1 and S2 of the active region 6 and the device isolation layer 9 past the active region 6 and the device isolation layer 9. . The buried capping patterns 34 may be an insulating material. The buried capping patterns 34 together with the buried plugs 29 form the lower patterns 36. Impurity diffusion regions 45 positioned around a selected one of the lower patterns 36 and overlapping the selected one buried plug 29 may be formed in the active region 6 as shown by the cut line I-I '. Form. The impurity diffusion regions 45 may be formed to have a different conductivity from that of the semiconductor substrate 3.

Referring again to FIGS. 1 and 2, upper patterns 56 are disposed on the lower patterns 36 as shown in cut lines I-I ', II-II' and III-III ', respectively. One of the upper patterns 56 may be arranged as seen in cut lines I-I 'and II-II' to align with the active region 6. That is, one of the upper patterns 56 may be formed to extend below the upper surface S1 of the active region 6 and to contact the buried plug 29 past the buried capping pattern 34. In addition, one of the upper patterns 56 may be formed to protrude from the upper surface S1 of the active region 6. In this case, one of the upper patterns 56 may be formed to have different widths on the buried plug 29.

The rest of the upper patterns 56 may be disposed as shown in the cut lines I-I 'and III-III' to align with the device isolation layer 9. That is, the rest of the upper patterns 56 may be formed to extend below the upper surface S2 of the device isolation layer 9 and to contact the buried plug 29 through the buried capping pattern 34. The rest of the upper patterns 56 may be formed in the device isolation layer 9 as shown in the cut line I ′ I ′ to surround the buried plug 29. To this end, the remaining of the upper pattern 56 may be formed as shown in the cut line III-III 'to protrude below the buried plug 29. In addition, the rest of the upper patterns 56 may be formed to protrude from the upper surface S2 of the device isolation layer 9. The rest of the upper patterns 56 may be formed to have the same width on the buried plug 29.

Each of the upper patterns 56 may be at least one conductive material. The upper patterns 56 may be circuit wirings other than the bit line patterns and / or bit line patterns that are well known to those skilled in the art. A wiring insulating film is interposed between the upper pattern 56 and the active region 6 and between the lower pattern 36 and the active region 6 as shown in the cut lines I-I 'and II-II'. The wiring insulating layer 27 may be formed of different insulating layers 13 and 25 between the active region 6 and the upper pattern 56 and between the active region 6 and the lower pattern 36, respectively.

Next, methods of forming a semiconductor integrated circuit device having an upper pattern aligned with a lower pattern molded into a semiconductor substrate of the present invention will be described with reference to the remaining drawings.

3 to 7 are cross-sectional views illustrating a method of forming a semiconductor integrated circuit device, each taken along cut lines I-I ', II-II' and III-III 'of FIG.

1 and 3, the active region 6 and the device isolation film 9 are formed in the semiconductor substrate 3 as shown in the cut lines I-I ', II-II' and III-III '. . The device isolation layer 9 may be formed on the semiconductor substrate 3 to define the active region 6. A pad lower layer 13 is formed on the semiconductor substrate 3 as shown in cut lines I-I 'and II-II'. The pad lower layer 13 may be formed in the active region 6 using the device isolation layer 9 as a mask. The pad lower layer 13 may be formed using an insulating material.

The pad lower layer 13 may be silicon oxide. The pad underlayer 13 may be a material in which metal atoms and / or nonmetal atoms are inserted into the lattice of silicon oxide. The pad middle layer 16 is formed on the pad underlayer 13 as shown in cut lines I-I ', II-II' and III-III '. The pad middle layer 16 may be formed over the active region 6 and the device isolation layer 9. The pad middle layer 16 may be a conductive material.

1 and 4, a pad upper layer 19 is formed on the pad middle layer 16. The pad upper layer 19 may be formed to have an etching rate different from that of the pad middle layer 16 and the pad lower layer 13. The pad upper layer 19 may be silicon nitride. A photoresist film is formed on the pad upper layer 19. The photoresist film may be formed using a semiconductor photo process well known to those skilled in the art. The photoresist film may be formed to have openings positioned in the active region 6 and the device isolation layer 9 to expose the pad upper layer 19.

Subsequently, using the photoresist film as an etching mask, the upper pad 19, the middle pad 16, the lower pad 13, the isolation layer 9 and the active region 6 are etched to form a trench 23. ) Are formed as shown in cut line I-I '. At this time, one of the trenches 23 has a predetermined depth from the upper surface S1 of the active region 6 past the pad upper layer 19, the pad middle layer 16, and the pad lower layer 13. Can be formed. The other of the trenches 23 may be formed to have a predetermined depth from the upper surface S2 of the device isolation layer 9 after passing through the pad upper layer 19, the pad middle layer 16, and the pad lower layer 13. have. After the trenches 23 are formed, the photoresist film is removed from the semiconductor substrate 3.

Using the pad upper layer 19, the pad middle layer 16, and the pad lower layer 13 as a mask, a buried insulating film 25 is formed in the active regions 6 on the cutting lines I-I 'and II-II'. Form as shown. That is, the buried insulating layer 25 may be formed only in the trench 23 of the active region 6. The buried insulating layer 25 may be silicon oxide. The buried insulating layer 25 may be a material in which metal atoms and / or nonmetal atoms are inserted into a lattice of silicon oxide. The buried insulating film 25 and the pad lower layer 13 form a wiring insulating layer 26. The wiring insulating film 26 may be formed using the same material.

Alternatively, the wiring insulating layer 26 may be formed using different materials. A buried film 27 is formed on the pad upper layer 19 so as to fill the trenches 23 as shown in cut lines I-I ', II-II' and III-III '. The buried film 27 may be formed using a conductive material having an etching rate different from that of the pad middle layer 16. The buried film 27 may be formed using titanium nitride (TiN).

1 and 5, the buried layer 27 is entirely etched using the pad upper layer 19, the pad middle layer 16, and the pad lower layer 13 as an etching buffer layer to form a trench 23. The buried plugs 29 which partially fill the pads) are respectively formed as shown in the cut lines I-I ', II-II' and III-III '. The buried plugs 29 may be formed under the upper surfaces S1 and S2 of the active region 6 and the device isolation layer 9. A buried capping layer 32 is formed on the pad upper layer 19 to cover the buried plugs 29 to fill the trenches 23. The buried capping layer 32 may be formed using an insulating layer having the same etching rate as that of the pad upper layer 19.

1 and 6, the buried capping layer 32 and the pad upper layer 19 are etched to expose the pad middle layer 16. The pad middle film 16 is removed from the semiconductor substrate 3. Through this, the buried capping patterns 34 may be formed on the buried plugs 29 as shown in cut lines I-I ', II-II' and III-III ', respectively. In this case, the buried capping patterns 34 may be formed to protrude from the top surfaces S1 and S2 of the active region 6 and the device isolation layer 9. One of the buried capping patterns 34 may be formed to be surrounded by the wiring insulating layer 26 in the active region 6. The remaining of the buried capping patterns 34 may be formed to be surrounded by the device isolation layer 9. The buried capping patterns 34 form lower patterns 36 together with the buried plugs 29.

Meanwhile, one of the lower patterns 36 may be formed to cross the active region 6 and the device isolation layer 9 as shown in FIG. 1. The rest of the lower patterns 36 may be formed to cross the device isolation layer 9 as shown in FIG. 1. Using the lower patterns 36 and the isolation layer 9 as a mask, impurity diffusion regions 45 are formed in the active region 6 as shown in the cut line I-I '. The impurity diffusion regions 45 may be formed around the lower pattern 36 positioned in the active region 6 to overlap the buried plug 29. The impurity diffusion regions 45 may be formed to have a different conductivity from that of the semiconductor substrate 3. A planarization insulating film 52 is formed on the pad lower film 13 and the device isolation film 9 so as to cover the lower patterns 36 as shown in the cut lines I-I ', II-II' and III-III '. . The planarization insulating layer 52 may be formed using an insulating layer having the same etching rate as the pad lower layer 13. The planarization insulating layer 52 may be formed using an insulating layer having an etching rate different from that of the pad lower layer 13.

1 and 7, a photoresist film is formed on the planarization insulating film 52. The photoresist film may be formed to have openings positioned in the active region 6 and the device isolation film 9, respectively, and exposing the planarization insulating film 52. The planarization insulating layer 52, the device isolation layer 9, and the buried capping pattern 34 are etched by using the photoresist layer as an etching mask, the wiring insulating layer 26, and the buried plug 29 as an etching buffer layer. 54) are formed as shown in cut lines I-I ', II-II' and III-III '. One of the connection holes 54 may be formed to align with the active region 6. One of the connection holes 54 may be formed as shown in the cut lines I-I 'and II-II' to expose the wiring insulating film 26 and the buried plug 29. The remaining ones of the connection holes 54 may be formed in the device isolation layer 9. The remaining of the connection holes 54 may be formed as shown in cut lines I-I 'and III-III' to expose the device isolation layer 9 around and below the buried plug 29.

After the connection holes 54 are formed, the photoresist film is removed from the semiconductor substrate 3. Subsequently, an electrode film (not shown) is formed on the planarization insulating film 52 to fill the connection holes 54. The electrode film may be formed using at least one conductive material. Photoresist patterns are formed on the electrode layer. The photoresist patterns may be formed using semiconductor photo processes well known to those skilled in the art. The photoresist patterns may be formed to align with the connection holes 54, respectively. Using the photoresist patterns as an etch mask, the electrode film is etched to expose the planarization insulating film 52 so that the upper patterns 56 are formed as shown in cut lines I-I ', II-II' and III-III '. do. After the upper patterns 56 are formed, the photoresist patterns are removed from the semiconductor substrate 3.

Meanwhile, one of the upper patterns 56 may be formed in the active region 6 and contact the buried plug 29 past the buried capping pattern 34. The remaining of the upper patterns 56 may be formed on the device isolation layer 9 and may contact the buried plug 29 through the buried capping pattern 34. In this case, the remaining of the upper patterns 56 may be formed to surround the buried plug 29 to protrude from the buried plug 29 toward the semiconductor substrate 3. The upper patterns 56 may be circuit lines other than the bit line pattern or the bit line pattern. The upper patterns 56 may form the semiconductor integrated circuit device 60 together with the lower patterns 36.

As described above, the present invention provides semiconductor integrated circuit devices having a top pattern aligned with a bottom pattern molded into a semiconductor substrate, and methods of forming the same. In this way, the present invention can simply contact the lower pattern and the upper pattern with each other through the active region and / or device isolation layer of the semiconductor substrate compared to the prior art.

Claims (36)

A semiconductor substrate having an active region; An upper pattern disposed in a predetermined region of the semiconductor substrate, the upper pattern protruding upward from an upper surface of the active region and extending downwardly from an upper surface of the active region; A buried plug positioned below the upper surface of the active region and contacting the upper pattern through the predetermined region of the semiconductor substrate, and buried protruding from the upper surface of the active region so as to be positioned on the buried plug to surround the upper pattern; Including a lower pattern consisting of a capping pattern, And the upper pattern has different widths on the buried plug. The method of claim 1, The upper pattern includes a bit line pattern, And the upper pattern has at least one conductive material. The method of claim 2, A wiring insulating layer interposed between the active region and the upper pattern and between the active region and the lower pattern; And Further comprising impurity diffusion regions in the active region positioned in the periphery of the lower pattern to overlap the buried plug, The buried plug and the buried capping pattern may each be a conductive material and an insulating material, and the wiring insulating layer may be formed of different materials between the active region and the upper pattern, and between the active region and the lower pattern, respectively. And the lower pattern is a gate pattern. The method of claim 2, A wiring insulating layer between the active region and the upper pattern and between the active region and the lower pattern; And Further comprising impurity diffusion regions in the active region positioned in the periphery of the lower pattern to overlap the buried plug, The buried plug and the buried capping pattern may each be a conductive material and an insulating material, and the wiring insulating layer may be formed of the same material between the active region and the upper pattern, and between the active region and the lower pattern. A semiconductor integrated circuit device characterized by being a gate pattern. A semiconductor substrate having a device isolation film; An upper pattern disposed in a predetermined region of the semiconductor substrate, the upper pattern protruding upward from an upper surface of the device isolation film and extending downward from an upper surface of the device isolation film; A buried plug positioned below the upper surface of the device isolation layer and surrounded by the upper pattern through the predetermined region of the semiconductor substrate to contact the upper pattern, and disposed on the buried plug to surround the upper pattern Including a lower pattern consisting of a buried capping pattern protruding from the upper surface of the, And the upper pattern has the same width on the buried plug. The method of claim 5, wherein The upper pattern includes a bit line pattern, And the upper pattern has at least one conductive material. The method of claim 6, And wherein the buried plug and the buried capping pattern are conductive and insulating materials, respectively, and the lower pattern is a selected gate pattern. A semiconductor substrate having an active region and a device isolation film surrounding the region Respectively disposed in predetermined regions of the semiconductor substrate, each of which protrudes upwards from an upper surface of the active region and extends downwardly from an upper surface of the active region, and projects upwardly from an upper surface of the device isolation layer; First and second upper patterns extending downward from an upper surface of the device isolation layer; A first buried plug positioned below an upper surface of the active region and in contact with the first upper pattern through one of the predetermined regions of the semiconductor substrate, and positioned on the first buried plug to form the first upper pattern; A first lower pattern comprising a first buried capping pattern protruding from an upper surface of the active region to surround the first lower pattern; And A second buried plug positioned below the upper surface of the device isolation layer and surrounded by the second upper pattern through the remaining area of the semiconductor substrate to be in contact with the second upper pattern; A second lower pattern including a second buried capping pattern protruding from an upper surface of the device isolation layer so as to surround an upper pattern; And the first upper pattern has different widths on the first buried plug and the second upper pattern has the same width on the second buried plug. The method of claim 8, Each of the first and second upper patterns includes a bit line pattern, And wherein each of the first and second upper patterns has at least one conductive material. The method of claim 9, A wiring insulating layer interposed between the active region and the first upper pattern and between the active region and the first lower pattern; And Impurity diffusion regions are further included in the active region to be positioned around the first lower pattern to overlap the first buried plug. The first buried plug and the first buried capping pattern may each be a conductive material and an insulating material, and the wiring insulating layer may be different between the active region and the first upper pattern, and between the active region and the first lower pattern. And each of the first lower patterns is a gate pattern. The method of claim 9, A wiring insulating layer interposed between the active region and the first upper pattern and between the active region and the first lower pattern; And The semiconductor device further includes impurity diffusion regions positioned in the periphery of the first lower pattern to overlap the first buried plug. Each of the first buried plug and the first buried capping pattern is a conductive material and an insulating material, and the wiring insulating layer is the same material between the active region and the first upper pattern, and between the active region and the first lower pattern. And wherein the first lower pattern is a gate pattern. The method of claim 9, And wherein the second buried plug and the second buried capping pattern are conductive materials and insulating materials, respectively, and the second lower pattern is a gate pattern. Preparing a semiconductor substrate having an active region, Forming a trench in the active region, A lower pattern is formed in the trench, the lower pattern has a buried plug and a buried capping pattern stacked in turn and the buried capping pattern is formed to protrude from an upper surface of an active region defining the trench, An interlayer insulating film is formed on the active region to cover the lower pattern; A connection hole is formed in the interlayer insulating film, the connection hole is formed to expose the buried plug and the active region around the buried plug, and And forming an upper pattern filling the connection hole. The method of claim 13, Forming the upper pattern, An electrode film is formed on the interlayer insulating film so as to fill the connection hole; A photoresist pattern is formed on the electrode layer, wherein the photoresist pattern is formed to correspond to the upper pattern. Etching the electrode film using the photoresist pattern as an etching mask to expose the interlayer insulating film, and Forming a semiconductor integrated circuit device comprising removing the photoresist pattern from the semiconductor substrate The method of claim 14, And the electrode film is at least one conductive material and the upper pattern is a bit line pattern. The method of claim 15, Forming the connection hole, A photoresist film is formed on the interlayer insulating film, the photoresist film is formed to have an opening overlapping the buried plug and exposing the interlayer insulating film, Etching the interlayer insulating film and the buried capping pattern in sequence using the photoresist film as an etch mask, and the active region and the buried plug as etch buffer films, and Removing the photoresist film from the semiconductor substrate. The method of claim 13, Forming the trench, Forming a material film on the active region, A photoresist film is formed on the material film, the photoresist film is formed to have an opening exposing the material film, and Etching the material film and the semiconductor substrate in sequence using the photoresist film as an etching mask, and Removing the photoresist film from the semiconductor substrate, And the material film is formed to have at least one material. The method of claim 17, Forming the lower pattern, Forming a buried film on the material film to fill the trench, Forming the buried plug partially filling the trench by etching the buried film entirely with the material film as an etching buffer film, Forming a buried capping film on the material film to cover the buried plug to fill the trench, Partially etching the buried capping film and the material film to form the buried capping pattern on the buried plug, and And removing the material film from the semiconductor substrate. The method of claim 13, Forming a wiring insulating film between the active region and the upper pattern and between the active region and the lower pattern, and Forming impurity diffusion regions in the active region to be positioned around the lower pattern to overlap the buried plug, The buried plug and the buried capping pattern may each be a conductive material and an insulating material, the lower pattern may be a gate pattern, and the wiring insulating layer may be different between the active region and the upper pattern, and between the active region and the lower pattern. A method for forming a semiconductor integrated circuit device, characterized in that it is formed using materials, respectively. The method of claim 13, Forming a wiring insulating film between the active region and the upper pattern and between the active region and the lower pattern, and Forming impurity diffusion regions in the active region to be positioned around the lower pattern to overlap the buried plug, The buried plug and the buried capping pattern are conductive materials and insulating materials, the lower pattern is a gate pattern, and the wiring insulating layer is the same material between the active region and the upper pattern, and between the active region and the lower pattern. A method for forming a semiconductor integrated circuit device, characterized in that formed using. Preparing a semiconductor substrate having an element isolation film, Forming a trench in the device isolation layer, A lower pattern is formed in the trench, the lower pattern has a buried plug and a buried capping pattern stacked in turn, and the buried capping pattern is formed to protrude from an upper surface of the device isolation layer defining the trench; An interlayer insulating film is formed on the device isolation layer to cover the lower pattern; A connection hole is formed in the interlayer insulating film, the connection hole is formed to expose the buried plug and the device isolation film around and below the buried plug, and And forming an upper pattern filling the connection hole. The method of claim 21, Forming the upper pattern, An electrode film is formed on the interlayer insulating film so as to fill the connection hole; A photoresist pattern is formed on the electrode layer, wherein the photoresist pattern is formed to correspond to the upper pattern. Etching the electrode film using the photoresist pattern as an etching mask to expose the interlayer insulating film, and Forming a semiconductor integrated circuit device comprising removing the photoresist pattern from the semiconductor substrate The method of claim 22, And the electrode film is at least one conductive material and the upper pattern is a bit line pattern. The method of claim 23, Forming the connection hole, A photoresist film is formed on the interlayer insulating film, the photoresist film is formed to have an opening overlapping the buried plug and exposing the interlayer insulating film; Etching the interlayer insulating film, the device isolation film, and the buried capping pattern by using the photoresist film and the buried plug as an etch mask and an etch buffer film, respectively, and Removing the photoresist film from the semiconductor substrate. The method of claim 21, Forming the trench, Forming a material film on the device isolation layer, A photoresist film is formed on the material film, the photoresist film is formed to have an opening exposing the material film, and Using the photoresist film as an etching mask, the material film and the device isolation layer are sequentially etched, and Removing the photoresist film from the semiconductor substrate, And the material film is formed to have at least one material. The method of claim 25, Forming the lower pattern, Forming a buried film on the material film to fill the trench, Forming the buried plug partially filling the trench by etching the buried film entirely with the material film as an etching buffer film, Forming a buried capping film on the material film to cover the buried plug to fill the trench, Partially etching the buried capping film and the material film to form the buried capping pattern on the buried plug, and And removing the material film from the semiconductor substrate. The method of claim 21, And wherein the buried plug and the buried capping pattern are conductive and insulating materials, respectively, and the lower pattern is a gate pattern. Preparing a semiconductor substrate having an active region and a device isolation film surrounding the region, Forming first and second trenches in the active region and the device isolation layer, respectively, First and second lower patterns are respectively formed in the first and second trenches, and the first and second lower patterns are first buried plugs and first buried capping patterns stacked in turn, and second stacked in turn. Each of the buried plug and the second buried capping pattern, wherein the first and second buried capping patterns are formed to protrude from upper surfaces of the active region and the device isolation layer, respectively; An interlayer insulating film is formed on the active region and the device isolation layer to cover the first and second lower patterns, First and second connection holes are formed in the interlayer insulating layer, wherein the first connection hole exposes the first buried plug and the active area around the first buried plug, and the second connection hole is formed in the second connection hole. A buried plug, and the device isolation film around and below the second buried plug, and Forming first and second upper patterns filling the first and second connection holes, respectively. The method of claim 28, Forming the first and second upper patterns, Forming an electrode film on the interlayer insulating film to fill the first and second connection holes, Photoresist patterns are formed on the electrode layer, the photoresist patterns being formed to correspond to the first and second upper patterns, respectively. Etching the electrode film using the photoresist patterns as an etching mask to expose the interlayer insulating film, and Removing the photoresist patterns from the semiconductor substrate. The method of claim 29, And the electrode film is at least one conductive material and each of the first and second upper patterns is a bit line pattern. The method of claim 30, Forming the first and second connection holes, A photoresist film is formed on the interlayer insulating film, wherein the photoresist film is formed to have openings that respectively overlap with the first and second buried plugs and expose the interlayer insulating film. Etching the interlayer insulating layer, the device isolation layer, and the first and second buried capping patterns using the photoresist film as an etch mask, and the first and second buried plugs and the active region as an etch buffer film, and Removing the photoresist film from the semiconductor substrate. The method of claim 28, Forming the first and second trenches, Forming a material film on the active region and the device isolation layer; Forming a photoresist film on the material film, wherein the photoresist film is formed to have openings positioned in the active region and the device isolation film to expose the material film, and Etching the material film, the active region and the device isolation film using the photoresist film as an etching mask, and Removing the photoresist film from the semiconductor substrate, And the material film is formed to have at least one material. The method of claim 32, Forming the first and second lower patterns, Forming a buried film on the material film to fill the first and second trenches, Forming the first and second buried plugs which partially fill the first and second trenches by etching the buried film entirely by using the material film as an etching buffer film, Forming a buried capping film on the material film to cover the first and second buried plugs to fill the first and second trenches, Partially etching the buried capping film and the material film to form the first and second buried capping patterns on the first and second buried plugs, respectively; and And removing the material film from the semiconductor substrate. The method of claim 28, Wherein the first and second buried plugs are conductive materials, and the first and second buried capping patterns are insulating materials. The method of claim 28, Forming a wiring insulating film between the active region and the first upper pattern, between the active region and the first lower pattern, and Forming impurity diffusion regions in the active region to be positioned around the first lower pattern to overlap the first buried plug, Each of the first and second lower patterns is a gate pattern, and the wiring insulating layer is formed using different materials between the active region and the first upper pattern, and between the active region and the first lower pattern, respectively. Method for forming a semiconductor integrated circuit device, characterized in that. The method of claim 28, Forming a wiring insulating film between the active region and the first upper pattern, between the active region and the first lower pattern, and Forming impurity diffusion regions in the active region to be positioned around the first lower pattern to overlap the first buried plug, Each of the first and second lower patterns is a gate pattern, and the wiring insulating layer is formed using the same material between the active region and the first upper pattern and between the active region and the first lower pattern. A method of forming a semiconductor integrated circuit device.

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