KR100818098B1 - Internal voltage generator for semiconductor device - Google Patents

Abstract

An internal voltage generator of a semiconductor memory device is provided to control to set margin at the level for minimizing a total leakage current by clamping the level of a back bias voltage. A back bias voltage level detector(100) includes a first detector part detecting a back bias voltage clamped constantly at low temperature and a second detector part detecting a back bias voltage varying according to temperature, and outputs a back bias voltage control signal having margin corresponding to temperature according to the voltage detected in the first and the second detector part. A ring oscillator(200) generates a first pulse signal with variable pulse width by the back bias voltage control signal. A control part(300) outputs a plurality of second pulse signals with different phase by receiving the first pulse signal. A back bias voltage pumping part(400) performs pumping operation to control a back bias voltage by the plurality of second pulse signals, and outputs a target back bias voltage.

Description

Internal Power Generator Circuit for Semiconductor Memory Devices

1 is a circuit diagram of a level detector of a back bias voltage according to the prior art.

2 is a block diagram illustrating an internal power generation circuit according to an embodiment of the present invention.

3 is a detailed circuit diagram of a back bias voltage (Vbb) level detector according to the embodiment of FIG.

4 is a detailed circuit diagram of a ring oscillator according to the embodiment of FIG.

5 is a detailed circuit diagram illustrating a control unit according to the embodiment of FIG. 2.

6 is a waveform diagram illustrating an operation of a control unit according to the embodiment of FIG. 2.

7 is a detailed circuit diagram illustrating a back bias voltage pumping unit according to the embodiment of FIG. 2.

FIG. 8 is a graph illustrating a comparison between a back bias voltage level difference according to an exemplary embodiment of the present invention.

The present invention relates to a semiconductor memory, and more particularly, to an internal power generation circuit of a semiconductor memory.

Recently, due to the high speed, high density, and low power consumption of semiconductor memories, internal power supplies used internally have a great influence on DRAM operation.

Among them, the back bias voltage plays a big role in stabilizing DRAM operation.

In general, the back bias voltage can be used to prevent unnecessary bias caused by PN junction in the DRAM chip, data loss or latch-up of the memory cell, and to adjust the threshold voltage that varies with temperature. Can be used.

On the other hand, there is a phenomenon that the threshold voltage changes depending on the temperature, which can be referred to the following [Equation 1].

 [Equation 1]

 Vth (T) = Vth (0)-a (T- T0)

Here, Vth (T) represents a threshold voltage with increasing temperature, and Vth (0) is a threshold voltage at room temperature. In addition, a (0.5-5 mV / degree C) is a temperature constant, T is a changed temperature, and T0 represents a room temperature (298 degrees Cf).

[Equation 1] regarding the threshold voltage according to the above temperature shows that the threshold voltage decreases as the temperature increases, and the threshold voltage increases when the temperature decreases.

This is particularly problematic when the temperature is lowered and the threshold voltage is increased, which causes a tWR fail that does not meet the time required to write and recover data in DRAM.

In addition, a cell composed of most NMOS transistors loses a threshold voltage when transferring " high " data, and thus it is necessary to adjust the threshold voltage using a back bias voltage.

In order to solve the problems described above, the back bias voltage Vbb is adjusted using a level detection device of the back bias voltage.

1 illustrates a level detector of a conventional back bias voltage Vbb.

This has a configuration in which the back bias voltage Vbb is measured using a change in the resistance value according to the temperature of the transistor.

Specifically, the PMOS transistor PM1 having the source and bias terminals connected to each other and the NMOS transistor NM1 having the source and bias terminals connected in series are connected to each other, and the cell voltage Vcore is applied to the source of the PMOS transistor PM1. The back bias voltage is applied to the source of the NMOS transistor NM1.

In addition, the PMOS transistor PM1 to which the ground voltage Vss is applied to the gate and the NMOS transistor NM1 to which the cell voltage Vcore is applied are always turned on, and an output node between the two transistors according to the back bias voltage Vbb. The level of N1 is changed.

On the other hand, a driver in which the PMOS transistor PM2 and the NMOS transistor NM2 are CMOS-coupled to the output node N1 is configured, and through this driver, an output signal depending on the level of the node N1 is connected to the node N2. The level shifter 2 is provided to the level shifter 2, and the level shifter 2 outputs a back bias control signal bbeb through the inverters I4 and I6 connected in series after shifting the level of the input signal.

However, such a back bias voltage (Vbb) level detector (Vbb) detects the back bias voltage (Vbb) that changes linearly with temperature, which means that the back bias voltage (Vbb) that is adjusted in a section where the temperature is too high or too low. ) Caused the phenomenon to become too high or too low.

This defeated the use of the regulated back bias voltage (Vbb).

In addition, as the back bias voltage Vbb is lower, the leakage current of the channel is decreased, and the leakage current at the junction is increased, so that the total leakage current is minimized. It is necessary to adjust the back bias voltage (Vbb) with a margin at the level.

An object of the present invention for solving the above problems is to control the level of the back bias voltage bbeb used in the semiconductor memory device to have a margin corresponding to the temperature.

Another object of the present invention is to control the level of the back bias voltage used in the semiconductor memory device by clamping the margin at a level at which the total liquid current is minimized.

The internal power generation circuit of the semiconductor memory device according to the present invention for achieving the above object is a first detector for detecting a back bias voltage clamped at a constant low temperature and a second detector for detecting a back bias voltage that changes with temperature A back bias voltage level detector including a back side and outputting a back bias voltage adjustment signal having a margin corresponding to a temperature according to the voltages detected by the first and second detectors; A ring oscillator for generating a first pulse signal having a variable pulse width in response to the back bias voltage control signal; A controller configured to receive the first pulse signal and output a plurality of second pulse signals having different phases; And a back bias voltage pumping unit configured to output a target back bias voltage by performing a pumping operation for adjusting a back bias voltage by the plurality of second pulse signals.
The first detector may include: first voltage dividing means including resistors connected in series between a cell voltage and the back bias voltage to output a divided voltage having a temperature dependency; And first output means having different levels of output by using the divided voltage of the first voltage dividing means at the low temperature.
The second detector may include: second voltage dividing means for outputting a divided voltage having a temperature dependence using resistance of transistors connected in series between a cell voltage and the back bias voltage; And second output means for driving and outputting the divided voltage of the second voltage dividing means which is output in correspondence with the back bias voltage which changes according to the temperature.
In order to achieve the object of the present invention, an internal power generation circuit of another semiconductor memory device includes a first detector unit detecting a back bias voltage that is constantly clamped at a high temperature, and a second detector unit detecting a back bias voltage that varies with temperature. A back bias voltage level detector including a back bias voltage adjustment signal having a margin corresponding to a temperature according to voltages detected by the first and second detectors; A ring oscillator for generating a first pulse signal having a variable pulse width in response to the back bias voltage control signal; A controller configured to receive the first pulse signal and output a plurality of second pulse signals having different phases; And a back bias voltage pumping unit configured to output a target back bias voltage by performing a pumping operation for adjusting a back bias voltage by the plurality of second pulse signals.
The first detector may include: third voltage dividing means for outputting a divided voltage having a temperature dependency using resistance of PMOS transistors connected in series between a cell voltage and a ground voltage; And third output means having different levels of output by using the divided voltage of the third voltage dividing means at a high temperature.
The controller may output one or more pairs of the second pulse signals having opposite phases to control the back bias voltage pumping unit according to the first pulse signal.
The back bias voltage pumping unit may further precharge the first node and the second node to a back bias voltage level by a pair of third pulse signals having opposite phases included in the second pulse signal. Charge part; A switching unit configured to selectively switch according to potential levels of the first node and the second node to control the connection between the third node and the fourth node, which are both boosting nodes; And a boosting unit configured to selectively boost the third node and the fourth node, which are both boosting nodes, to a back bias pumping voltage level by a pair of fourth pulse signals having different phases included in the second pulse signal. It includes.

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Hereinafter, a preferred embodiment of an internal power generation circuit of a semiconductor memory device according to the present invention will be described in detail with reference to the accompanying drawings.

The internal power generation circuit of the semiconductor memory device of the present invention pumps the back bias voltage (Vbb) level detector 100, the oscillator 200, the control unit 300, and the back bias voltage (Vbb) as shown in FIG. The unit 400 is provided.

Here, the Vbb level detector 100 generates a back bias voltage control signal bbeb and provides it to the oscillator 200, and the oscillator 200 has a pulse signal having a pulse width corresponding to the back bias control signal bbeb. The osc is provided to the controller 300, and the controller 300 generates a plurality of pulse signals p1, p2, g1, and g2 for pumping as a pulse signal osc and provides the same to the Vbb pumping unit 400. In addition, the Vbb pumping unit 400 pumps the back bias voltage Vbb by the pulse signals p1, p2, g1 and g2, and the pumped back bias voltage Vbb is output through the capacitor Cv.

3 is a detailed circuit diagram of the Vbb level detector 100 according to an embodiment of the present invention.

Referring to FIG. 3, the Vbb level detector 100 includes a detector 102 for clamping a back bias voltage at a low temperature, a detector 104 for detecting a back bias voltage that varies with temperature, and a back bias voltage at a high temperature. The detector 106 for clamping the detector 106, the inverter I16 connected in series with the NOR gate NOR1 to which the output signal of the detector 102 and the detector 104 is applied, and the output and detector of the inverter I16. A NAND gate NAND1 to which an output of the unit 106 is applied; A level shifter 110 connected in series with the NAND gate NAND1, and a delay unit 112 delaying an output signal of the level shifter 110.

In the above configuration, the detector unit 102 prevents the absolute value of the back bias voltage Vbb from becoming lower than a predetermined level at a low temperature. The level output is maintained to prevent the detected back bias voltage from continuously decreasing with temperature.

Specifically, the detector 102 may include resistors R1 and R2 connected in series to a node to which a cell voltage Vcore is applied, a PMOS transistor PM10 and an NMOS transistor NM10 connected in series, and a PMOS transistor PM10 and an NMOS. An inverter I10 for inverting the output between the transistors N10 is provided.

In addition, the node a1 between the series connected resistors R1 and R2 is connected to the gate of the PMOS transistor PM10 having the source terminal and the bias terminal connected thereto, and the NMOS transistor NM10 having the source terminal and the bias terminal connected with the cell voltage Vcore. ) Is applied to the gate.

The back bias voltage Vbb is applied to the resistor R2, and the ground voltage Vss is applied to the source of the NMOS transistor NM10.

The detector unit 102 is configured to clamp the back bias voltage detected at a low temperature to a predetermined level (about -0.4 V) so that the level of the output node changes around the predetermined back bias voltage (about -0.4 V). It is preferred to be configured.

In addition, the detector 102 connects the resistors R1 and R2 in series between the cell voltage Vcore and the back bias voltage Vbb, and is connected to the resistors R1 and R2 according to the back bias voltage Vbb. The divided voltage is applied to the gate of the PMOS transistor PM10.

On the other hand, when the back bias voltage Vbb goes below a certain level (usually -0.4V), the node a1 is at the "low" level, and the PMOS transistor PM10 is turned on.

In addition, as the PMOS transistor PM10 is turned on, the output of the detector 102 becomes a "low" level.

Therefore, when the back bias voltage Vbb rises above a certain level (typically -0.4V), the node a1 becomes high level, the PMOS transistor PM10 is inactivated, and the node a2 which is the output of the clamping circuit part A is therefore. ) Becomes the "high" level.

The detector 104 detects the back bias voltage Vbb that changes constantly according to the temperature, and detects the back bias voltage Vbb so that the back bias voltage can be adjusted according to the temperature.

Specifically, the detector unit 104 includes a PMOS transistor PM12 and a PMOS transistor PM14 to which a cell voltage Vcore is applied to a source terminal, and an NMOS transistor NM12 is connected to a drain of the PMOS transistor PM12. The NMOS transistor NM14 is connected in series with the PMOS transistor PM14.

In addition, the source and bias terminals of the PMOS transistors PM12 and PM14 and the NMOS transistors NM12 and NM14 are connected.

Meanwhile, the ground voltage Vss is applied to the gate of the PMOS transistor PM12, and the cell voltage Vcore is applied to the gate of the NMOS transistor NM12.

The output terminal formed through the common node b1 between the PMOS transistor PM12 and the NMOS transistor NM12 is applied to the gates of the PMOS transistor PM14 and the NMOS transistor NM14, and the PMOS transistor PM14 is described above. And the output between NMOS transistor NM14 are inverted by inverter I12.

The detector 104 has different resistance values for the PMOS transistor PM12 and the NMOS transistor NM12 according to the back bias voltage, and the voltage of the output terminal provided between the PMOS transistor PM12 and the NMOS transistor NM12. The level of will change.

If the back bias voltage is high, node b1 is at the "high" level, and the level of node b3 is the logic level of the "high" state by the inverters.

On the other hand, when the back bias voltage is low, the node b1 is at the "low" level, and the output of the detector unit 104 is at the "low" state.

On the other hand, the detector unit 106 serves to clamp the back bias voltage so as not to be lower than the target voltage at a high temperature.

Specifically, the detector 106 includes a PMOS transistor PM16 and a PMOS transistor PM20 to which a cell voltage Vcore is applied to a source terminal, and a PMOS transistor PM16 is connected in series to the drain of the PMOS transistor PM16. The NMOS transistor NM16 is connected in series to the PMOS transistor PM20.

In addition, the PMOS transistors PM16, PM18, and PM20 and the NMOS transistor NM16 have a source and a bias terminal connected thereto.

On the other hand, the ground voltage Vss is applied to the gate of the PMOS transistor PM16, and the back bias voltage Vbb is applied to the gate of the PMOS transistor PM18.

The output voltage is applied to the gates of the PMOS transistor PM20 and the NMOS transistor NM16 through the common node c1 between the PMOS transistor PM16 and the PMOS transistor PM18, and the PMOS transistor PM20. And the output between NMOS transistor NM16 are inverted by inverter I14.

On the other hand, the detector 106 has different conditions under which the PMOS transistor PM16 and the PMOS transistor PM18 are activated according to a change in the back bias voltage according to temperature, and thus, between the PMOS transistor PM16 and the PMOS transistor PM18. The divided voltage of is also changed.

Therefore, the level of the node c1 varies with temperature.

When the back bias voltage is high (about -0.8V or more), the node c1 becomes the "high" level, the inverters change the level of the node c1, and the detector unit 106 outputs a high state. .

On the other hand, when the back bias voltage is low (about -0.8 V or less), the node c1 is at the "low" level, and the output of the detector unit 106 is at the low state.

Meanwhile, the first output unit generates the back bias voltage control signal bbeb according to the outputs of the detectors 102, 104, and 106 that detect the back bias voltage.

Specifically, if the back bias voltage is high (about -0.2V), the detector unit 102 detects a voltage higher than the reference voltage at which the output is changed, and puts the node a3 in the "high" state. Make.

In addition, the detector unit 104 always turns on the transistor regardless of the absolute value of the back bias voltage having a negative voltage, outputs a "high" level signal at the sensed voltage, and the node b3. ) To "high" state.

On the other hand, the NOR1, to which the detector 102 and the output of the detector 104 are applied, outputs a signal of "low" level, and the inverter connected in series is inverted, so that the node det0 is "high" level. Makes the state of

Here, the detector section 106 makes the output of the node c3 "high" level higher than the reference voltage (about -0.8V) at which the level of the node c1 changes.

Therefore, the "high" level signals of the node det0 and the node c3 are applied to the NAND gate NAND1.

The applied signal is NAND to the NAND gate NAND1, resulting in a signal of "low" level.

Here, the signal of the "low" level is changed by the level shifter 110 to a predetermined reference level, and is delayed and output by the delay unit 112.

Therefore, the Vbb level detector 100 outputs a back bias adjustment signal bbeb of the "low" level.

In addition, a "low" level back bias adjustment signal bbeb is applied to the ring oscillator 200.

If the back bias voltage is low (about -1.0 V), the detector unit 102 detects a voltage lower than the reference voltage at which the output changes, and makes the node a3 "low".

In addition, the detector unit 104 always turns on the transistor and turns to a “high” level at the sensed voltage, regardless of the absolute value of the back bias voltage having a negative voltage, and the node b3 is “high”. "State.

On the other hand, the NOR1 to which the detector 102 and the output of the detector 104 are applied outputs a "low" level signal, and the inverter connected in series inverts the node det0 to a "high" level. Make it state.

Here, the detector section 106 lowers the level of the node c1 to a reference voltage (about -0.8 V) at which the level is changed, thereby making the output of the node c3 a "low" level.

Therefore, the "high" level and "low" level signals of the node det0 and the node c3 are applied to the NAND gate NAMD1.

The applied signal is NAND to the NAND gate NAND1, resulting in a "high" level signal.

Here, the signal of the "high" level is changed by the level shifter 110 to a predetermined reference level, and is delayed and output by the delay unit 112.

Therefore, the Vbb level detector 100 outputs a back bias adjustment signal bbeb of the "high" level.

In addition, a back bias adjustment signal bbeb of the "high" level is applied to the ring oscillator 200.

If the back bias voltage is about -0.6 V, the detector unit 102 detects the back bias voltage lower than the reference voltage at which the output changes, thereby bringing the node a3 to a "low" state.

In addition, the detector unit 104 may turn the transistor b on and become a “high” level at the sensed voltage regardless of the absolute value of the back bias voltage having a negative voltage, and the node b3 may be “high”. Make it.

On the other hand, the NOR1 to which the detector 102 and the output of the detector 104 are applied outputs a "low" level signal, and the inverter connected in series inverts the node det0 to a "high" level. Make it state.

Here, the detector section 106 makes the output of the node c3 "high" level higher than the reference voltage (about -0.8V) at which the level of the node c1 changes.

Therefore, the "high" level signals of the node det0 and the node c3 are applied to the NAND gate NAMD1.

The applied signal is NAND to the NAND gate NAND1, resulting in a signal of "low" level.

Here, the signal of the "low" level is changed by the level shifter 110 to a predetermined reference level, and is delayed and output by the delay unit 112.

Therefore, the Vbb level detector 100 outputs a back bias adjustment signal bbeb of the "low" level.

In addition, a "low" level back bias adjustment signal bbeb is applied to the ring oscillator 200.

As a result, the Vbb level detector 100 outputs a back bias adjustment signal bbeb of the "low" level or the "high" level, and the ring oscillator 200 generates a pulse according to the back bias adjustment signal bbeb. osc) outputs a signal.

4 shows a ring oscillator 200 of the present invention.

Referring to FIG. 4, the ring oscillator 200 includes inverter chains I22 I23, I24, and I25 connected in series with a NOR gate NOR10 to which a back bias control signal bbeb of the Vbb level detector 100 is applied. .

In addition, an output node is provided between the NOR gate NOR10 and the inverter chains I22 I23, I24, and I25, and the inverter chains I20 and I21 are connected in series to the output node, and a pulse signal that is an output of the ring oscillator 200. Print (osc)

On the other hand, when the back bias control signal bbeb is applied to the ring oscillator 200 and the applied signal is in the "low" state, a pulse signal osc in the "high" state is generated to the next control unit 300. The controller 300 generates the pulse signals p1, p2, g1, and g2 that control the operation of the Vbb pumping unit 400.

On the other hand, when the back bias voltage Vbb reaches the target voltage level, the Vbb level detector 100 generates a "high" level back bias voltage control signal bbeb, and the ring oscillator 200 is oscillated. Do not output the pulse signal osc.

Therefore, operations of the controller 300 and the Vbb pumping unit 400 are disabled.

5 illustrates a control unit 300 according to an embodiment of the present invention.

Referring to FIG. 5, the controller 300 receives a pulse signal osc output from the ring oscillator 200 as an input, and controls pulse signals p1, p2, g1, and g2 controlling the operation of the Vbb pumping unit 400. )

In detail, the control unit 300 controls the applied pulse signal osc to the pulse signal p1 delayed by the inverter chains I30 and I31 and the pulse signal p1 inverted to the pulse signal p1 by the inverter I32. output p2).

In addition, the controller 300 NAND-combines the applied pulse signal osc and the signal delayed by the inverter chains I33 and I34 by the NAND gate NAND30, and the NAND-combined signal is transferred to the inverter chains I35 and I36. Is delayed and output as a pulse signal g1.

On the other hand, the pulse signal g2 is NAND-combined by the NAND gate NAND32 with a signal delayed by the pulse signal osc and the inverter chains I33 and I34, and the NAND-combined signal is converted into the inverter chains I37, I38, and I36. It is generated by output via).

As a result, the pulse signal p1 and the pulse signal p2 have opposite phases, and the pulse signal g1 and the pulse signal g2 also have opposite phases.

Meanwhile, referring to FIG. 6, an operation waveform diagram of a signal generated by the controller 300 may be described.

The controller 300 delays and inverts the pulse signal osc to generate pulse signals p1 and p2 having opposite phases, and are pulsed to the NAND gate, delayed and inverted, and have different periods and have opposite phases. (g1, g2) was produced.

The pulse signals p1, p2, g1, and g2 have a characteristic of adjusting the operation of the Vbb pump unit 400 according to the level.

On the other hand, Figure 7 shows a preferred embodiment of the Vbb pumping unit 400.

Referring to FIG. 7, the Vbb pumping unit 400 may be configured as a doubler pump operating in dual using a period.

Specifically, according to the pulse signals g1 and g2 provided by the controller 300, the Vbb pumping unit 400 selectively precharges both nodes g and h to which the pulse signals g1 and g2 are applied to the back bias voltage level. A precharge unit 70 to be controlled, a switching unit 72 which is selectively switched according to potential levels of both nodes g and h, and controls the connection with both boosting nodes e and f, and a pulse signal g1, The boosting unit 74 may boost both side boosting nodes e, f selectively to the back bias pumping voltage level under the control of the pulse signals p1 and p2 having a different timing than g2).

The Vbb pumping unit 400 having such a configuration performs a pumping operation according to the states of the respective pulse signals p1, p2, g1, and g2 to adjust the potential difference of the back bias pumping voltage.

Specifically, the operation of the Vbb pump 400 is as follows.

When the pulse signal g1 changes to the "high" level Vdd in the Vbb pump unit 400, the node g is clamped to the threshold voltage level of the PMOS transistor PM40 by the PMOS transistor PM40.

 On the other hand, the NMOS transistor NM40 is turned off by the pulse signal p2.

On the contrary, when the pulse signal g1 changes to the "low" level (Ground), the node g changes to the "low" level (threshold voltage-Vdd) to turn on the PMOS transistor PM44.

On the other hand, when the pulse signal p1 changes to the "low" level Ground, the level of the node e is changed to the "low" level (-Vdd) by the PMOS transistor PM44. At this time, the NMOS transistor NM40 is turned on by the pulse signal p2, and Vbb has a negative value and is pumped.

Similarly, when the pulse signal g2 whose phase is opposite to the pulse signal g1 changes to the "high" level Vdd, the node h causes the node h to level at the threshold voltage of the PMOS transistor PM42 by the PMOS transistor PM42. Is clamped.

At this time, the NMOS transistor NM42 is in an off state by the node e, and when the pulse signal g2 becomes the "low" level (Ground) from the "high" level Vdd, the node f ) Becomes the "low" level (Ground).

On the other hand, when the pulse signal p2 becomes the "low" level (Ground) from the "high" level Vdd, the node f changes to the "low" level (-Vdd).

At this time, the NMOS transistor NM42 is turned on by the node e, that is, the pulse signal p1, and the VBB has a negative value and is pumped.

According to the embodiment of the present invention, the back bias voltage according to the temperature may be detected, and the back bias voltage may be appropriately adjusted by feeding back according to the detected voltage.

7 shows the results of detection of the back bias voltage for temperature changes in accordance with a preferred embodiment of the present invention.

Referring to FIG. 7, the detection of the back bias voltage according to the present invention is detected by constantly clamping the back bias voltage in a temperature section above or below a certain section, and detects a back bias voltage that varies with temperature at a certain section of temperature. Thus, unlike the conventional back bias voltage detection, the back bias voltage may be shifted to a target level.

Therefore, the internal power generation circuit of the semiconductor memory device of the present invention includes a back bias voltage level detector in which the back bias voltage Vbb is clamped in accordance with temperature, thereby adjusting the detected back bias voltage and stable to the power supply voltage. It provides a semiconductor memory device that operates.

Claims (10)

delete delete A first detector unit detecting a back bias voltage that is constantly clamped at a low temperature, and a second detector unit detecting a back bias voltage that changes according to temperature, wherein the temperature is measured according to the voltages detected by the first and second detector units. A back bias voltage level detector for outputting a back bias voltage adjustment signal having a margin corresponding thereto; A ring oscillator for generating a first pulse signal having a variable pulse width in response to the back bias voltage control signal; A controller configured to receive the first pulse signal and output a plurality of second pulse signals having different phases; And A back bias voltage pumping unit configured to output a target back bias voltage by performing a pumping operation for adjusting a back bias voltage by the plurality of second pulse signals; Internal power generation circuit of the semiconductor memory device comprising a. The method of claim 3, wherein The first detector unit, First voltage dividing means having resistors connected in series between the cell voltage and the back bias voltage to output a divided voltage having a temperature dependency; And First output means having different levels of output by using the divided voltage of the first voltage dividing means at the low temperature; An internal power generation circuit of the semiconductor memory device having a. The method of claim 3, wherein The second detector unit, Second voltage dividing means for outputting a divided voltage having a temperature dependence using resistance of transistors connected in series between a cell voltage and a back bias voltage; And Second output means for driving and outputting the divided voltage of the second voltage dividing means which is output in correspondence with the back bias voltage which varies with the temperature; An internal power generation circuit of the semiconductor memory device having a. A first detector unit detecting a back bias voltage that is constantly clamped at a high temperature, and a second detector unit detecting a back bias voltage that varies with temperature, wherein the temperature is measured according to the voltages detected by the first and second detector units. A back bias voltage level detector for outputting a back bias voltage adjustment signal having a margin corresponding to the back bias voltage level; A ring oscillator for generating a first pulse signal having a variable pulse width in response to the back bias voltage control signal; A controller configured to receive the first pulse signal and output a plurality of second pulse signals having different phases; And A back bias voltage pumping unit configured to output a target back bias voltage by performing a pumping operation for adjusting a back bias voltage by the plurality of second pulse signals; Internal power generation circuit of the semiconductor memory device comprising a. The method of claim 6, The first detector unit, Third voltage dividing means for outputting a divided voltage having a temperature dependency using resistance of PMOS transistors connected in series between a cell voltage and a ground voltage; And Third output means having a different level of output by using the divided voltage of the third voltage dividing means at the high temperature; Internal power generation circuit of the semiconductor memory device having a. delete The method according to claim 3 or 6, wherein And the control unit outputs one or more pairs of the second pulse signals having opposite phases to control the back bias voltage pumping unit according to the first pulse signal. The method according to claim 3 or 6, wherein The back bias voltage pumping unit, A precharge unit selectively precharging the first node and the second node to a back bias voltage level by a pair of third pulse signals having opposite phases included in the second pulse signal; A switching unit configured to selectively switch according to potential levels of the first node and the second node to control the connection between the third node and the fourth node, which are both boosting nodes; And A boosting unit configured to boost the third node and the fourth node, which are both boosting nodes, to a back bias pumping voltage level by a pair of fourth pulse signals having different opposite phases included in the second pulse signal; Internal power generation circuit of the semiconductor memory device comprising a.

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