KR100813005B1 - 1-step Etching Method for Cu/Mo line having inner Mo barrier layer by Mo - Google Patents

Abstract

In the present invention, the step of sequentially depositing a molybdenum (Mo) layer, a copper (Cu) layer on the substrate; Cu etching the copper layer and the molybdenum layer using a etchant comprising a main etchant comprising an oxidizing agent and an etchant and an auxiliary etchant of an additive type capable of lowering the potential difference between copper and molybdenum. By providing batch etching method of / Mo wiring, it is possible to develop products with improved production yield by forming Cu / Mo wiring with improved taper characteristics in one etching process, and to provide reliable metal wiring for large area and high resolution liquid crystal display. The development of the device can be facilitated and the scope of application can be extended to related electronic products.

Description

1-step Etching Method for Cu / Mo line having inner Mo barrier layer by Mo}             

1 is a plan view of an array substrate for a general liquid crystal display device.

2 is a cross-sectional view taken along the line II-II of FIG. 1.

Figures 3a to 3c is a step-by-step diagram showing the manufacturing process of a conventional Cu / Ti wiring.

4 is a view showing a rework process of a metal wiring for a liquid crystal display device to which a conventional Cu / Ti wiring structure is applied.

5 is a view showing a cross-sectional structure after a batch etching process of a conventional Cu / Mo wiring.

Figures 6a to 6c is a step-by-step diagram showing the manufacturing process of the Cu / Mo wiring according to the present invention.

7 is a cross-sectional view of a thin film transistor for a liquid crystal display device to which a Cu / Mo wiring is applied according to the present invention.

8 shows the taper characteristics of Cu / Mo wiring according to the present invention.

<Explanation of symbols for main parts of drawing>

100: transparent substrate 108a: first metal wiring                 

108b: second metal wiring 108: metal wiring

VIa: Metal Wiring Formation Area VIb: Peripheral Area

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to metal wiring for liquid crystal display devices, and more particularly, to an etching method of a copper wiring including a barrier layer among such metal wirings.

The liquid crystal display device is most popular as a next generation advanced display device device having low power consumption, good portability, technology-intensive and high added value.

The liquid crystal display device injects a liquid crystal between two substrates on which a transparent electrode is formed, and drives the liquid crystal display to obtain an image effect by using a difference in refractive index of light due to the anisotropy of the liquid crystal.

Currently, a thin film transistor (TFT) for opening and closing each pixel is positioned for each pixel, and the thin film transistor serves as a switch so that the first electrode is turned on and off in units of pixels, and the second electrode is a common electrode. The active matrix liquid crystal display (AM-LCD) used has attracted the most attention because of its excellent resolution and video performance.

The material forming the metal wiring, which serves as a signal intermediary in such a liquid crystal display device, can be improved in reliability and price competitiveness as it is selected from a metal having low resistivity and strong corrosion resistance. As the metal wiring material, aluminum (Al) or aluminum (Al alloy) was mainly used.

Hereinafter, a basic structure of an array substrate for a liquid crystal display device will be described with reference to the drawings.

1 is a plan view of an array substrate for a general liquid crystal display device.

As shown in the drawing, the gate wiring 14 is formed in the horizontal direction, and the data wiring 20 is formed in the vertical direction crossing the gate wiring 14. The gate and data wirings 14 and 20 are formed. The thin film transistor T, which is a switching element, is formed at the intersection point, and the thin film transistor T is formed through the drain contact hole 28 in the pixel region defined as an area where the gate and the data lines 14 and 20 intersect. ) Is connected to the pixel electrode 30.

The thin film transistor T overlaps the gate electrode 12 branched from the gate wiring 14, an island-like semiconductor layer 18 covering the gate electrode 12, and both ends of the semiconductor layer 18 at predetermined intervals. And a source electrode 22 branched from the data line 20 and a drain electrode 24 spaced apart from the source electrode 22 and connecting the pixel electrode 30 and the thin film transistor T.

2 is a cross-sectional view taken along the line II-II of FIG. 1.

As illustrated, a gate electrode 12 is formed on the transparent substrate 1, and a gate insulating film 16 is formed on the gate electrode 12 and on the entire surface of the substrate, and the upper portion of the gate insulating film 16 is formed. The semiconductor layer 18 is formed in the position which covers the gate electrode 12 of this, The source layer and the drain electrode 22 and 24 which are spaced at predetermined intervals from each other are formed in this semiconductor layer 18, This source And a channel ch is formed in the separation section between the drain electrodes 22 and 24.

The semiconductor layer 18 includes an active layer 18a made of pure amorphous silicon (a-Si), and an ohmic contact layer 18b made of impurity amorphous silicon (n + a-Si) positioned on the active layer 18a. It is composed of A passivation layer 26 having a drain contact hole 28 exposing a part of the drain electrode 24 is formed on the thin film transistor T, and a drain is formed in the pixel region P above the passivation layer 26. The pixel electrode 30 connected to the drain electrode 24 is formed through the contact hole 28.

Meanwhile, in supplying scan signals and data signals from an external circuit to the liquid crystal panel, the scan signals cause the thin film transistors of each pixel to be sequentially turned on and off through the gate wirings, and the data signals are turned on through the data wirings. It is applied to the pixel electrode connected to the thin film transistor of the state. Accordingly, when the area and resolution are increased to SVGA, XGA, SXGA, VXGA, etc., scanning time is shortened and signal processing speed is increased. Therefore, it is inevitable to select gate and data wiring from low-resistance metal material to cope with this problem. Do.

Accordingly, in recent years, the replacement of copper (Cu) having a specific resistivity and an electromigration (Electromigration) characteristics than the conventional metal wiring material has been actively proposed. However, copper has a weak adhesive strength with the glass substrate, and even a relatively low temperature (approximately 200 °) has a strong diffusion force on the silicon material layer (insulation layer, semiconductor layer), which is substantially difficult to apply as a single metal wiring material.

In order to solve this problem, when the copper wiring is used as the gate and data wiring, it is possible to prevent diffusion into the semiconductor layer and adhesion characteristics of the substrate at the interface between the glass substrate and the gate wiring, and the interface between the semiconductor layer and the data wiring, respectively. A copper wiring structure including a separate barrier layer has been proposed. Initially, a Cu / Ti wiring structure using titanium (Ti) as a barrier metal material has been proposed.

3A to 3C show a step of manufacturing a conventional Cu / Ti wiring step by step, including the rework process of the Cu / Ti wiring.

In FIG. 3A, the gate wiring 32 is formed on the glass substrate 1, but not shown in the drawing. In this step, a Ti layer serving as an adhesive barrier with the glass substrate 1 is deposited; Depositing a Cu layer on the Ti layer, applying a PR layer having a gate wiring pattern, and etching the Cu layer 32b and the Ti layer 32a in this order using the PR layer as a mask. And forming (32).

In this case, the Ti layer 32a is typically etched by an etchant containing fluorine (F) ions. The hydrofluoric acid (HF), which is a representative etchant containing the fluorine ion, may be formed of a silicon-based material as well as the Ti layer 32a. As shown in the drawing, the glass substrate 1, the silicon insulating material, and the semiconductor material are etch-reactive with the glass substrate 1 on the peripheral region IIIb except for the substrate region IIIa corresponding to the gate wiring. As a part of the glass substrate 1 is etched according to the reaction, the initial substrate surface in the region IIIb is etched by " IIIc ", thereby degrading the flatness characteristic of the substrate.                         

FIG. 3B is a re-etching step for removing the gate wiring 32 pattern in FIG. 3A. In this step, the gate wiring 32 in FIG. 3A is removed and the entire substrate is exposed. In this step, as the glass substrate 1 in the region IIIb is etched simultaneously in the process of removing the gate wiring 32 pattern on the region IIIa, the flatness characteristic of the substrate is further degraded.

In FIG. 3C, as the gate wiring 34 is re-formed on the glass substrate 1 having passed through FIG. 3B, the gate wiring 34 is deformed at a position corresponding to the region IIIa due to a process margin or the like. It is easy to form at the boundary of IIIa and IIIb. Accordingly, the gate wiring 34 is likely to generate a step along the non-uniform surface of the substrate, and induces a pattern defect of other elements formed based on the position of the gate wiring 34, thereby reducing process efficiency. have.

Hereinafter, the problem at the time of the rework process of the Cu / Ti wiring which contacts a silicon insulation layer is demonstrated.

4 is a diagram illustrating a rework process of a metal wiring for a liquid crystal display device employing a conventional Cu / Ti wiring structure.

As shown in the drawing, when the Cu / Ti metal wiring is applied as the metal wiring material for the liquid crystal display device and the array process is performed, any one of a silicon oxide film (SiO _X ) and a silicon nitride film (SiN _X ) is formed on the gate wiring 32. In the structure in which the gate insulating film 36 made of a material is formed, after the semiconductor layer, the source and drain electrode forming processes are performed, the source and drain electrode patterns are reworked. Since the fluorine ions are used to etch the layer, the gate insulating film 36 made of the silicon material of the lower layer is etched by the etchant, and thus the gate electrode 32 having poor film forming characteristics of the gate insulating film 36 is etched. The short circuit phenomenon that exposes the gate electrode 32 is likely to occur in the excessive stepped portion IIId.

In order to solve the above problems, recently, Cu / Mo wiring technology using molybdenum (Mo), which is a metal material capable of etching using an etchant that does not have etching reactivity with a silicon-based material, and can act as a barrier for the Cu metal layer, has been developed. Was introduced.

In the etching process of Cu / Mo wiring, a technique for batch etching using an etchant consisting of a mixed solution of hydrogen peroxide (H ₂ O ₂ ) and acetic acid (CH ₃ COOH) as an etchant for etching has been introduced. The etching mechanism of Cu / Mo by cheat is as following Formula (1), (2), (3).

Cu + H ₂ 0 ₂ → CuO + H ₂ 0 ---------- (1)

Cu0 + 2CH ₃ COOH → 2 (CH ₃ COO) Cu + H ₂ 0 ---------- (2)

Mo + 3H ₂ 0 ₂ = Mo0 ₃ + 3H ₂ 0 ---------- (3)

5 is a view showing a cross-sectional structure after a batch etching process of a conventional Cu / Mo wiring.

Conventionally, in the process of collectively etching Cu / Mo using the same etchant, Cu is caused by galvanic phenomenon by the potential difference between Cu and Mo (for example, Cu = -0.3 eV, Mo = 0.2 eV). As the etching reactivity of Mo having a higher oxidation potential is higher, etching becomes more active, resulting in undercut, a phenomenon in which the Mo metal layer is overetched than the Cu metal layer.

As shown in the figure, the taper property of the Cu / Ti wiring 38 is degraded as the Mo metal layer 38a constituting the lower layer is undercut than the Cu metal layer 38b constituting the upper layer, which causes the voltage-current characteristics of the wiring. It causes the drop.

In order to solve the problems appearing in the batch etching process of the Cu / Mo wiring as described above, by providing an etchant and etching method in which a separate additive that can solve the undercut problem of the Mo metal layer in the Cu / Mo wiring, It is an object to easily apply to a large area / high resolution liquid crystal display device.

The additive may be a material capable of lowering the potential difference between the Cu metal and the Mo metal.

In order to achieve the above object, one feature of the present invention comprises the steps of depositing a molybdenum (Mo) layer, a copper (Cu) layer on the substrate in turn; Forming a wiring photoresist layer on the copper layer; An etchant including a main etchant including an oxidizing agent and an etchant for the copper layer exposed to the outside of the photoresist layer and a molybdenum layer below it, and an additive type auxiliary etchant capable of lowering the potential difference between copper and molybdenum. Provided is a batch etching method of Cu / Mo wiring including batch etching using the same.

The oxidizing agent is hydrogen peroxide (H ₂ O ₂ ), the etching agent is acetic acid (CH ₃ COOH), the auxiliary etchant is an etchant containing ammonium acetate (CH ₃ COONO ₄ ), the auxiliary etchant is DI water It characterized by including.

In addition, the deposition thickness of the molybdenum layer and the copper layer is characterized in that each of 50 kPa ~ 200 kPa, 1500 kPa ~ 2500 kPa.

In still another aspect of the present invention, a molybdenum (Mo) layer and a copper (Cu) layer are sequentially formed on a substrate, and the potential difference between the main etchant including an oxidizing agent and an etchant, and copper and molybdenum can be lowered. Forming a gate wiring of a double layer structure of molybdenum and copper and a gate electrode having a double layer structure branched from the gate wiring by batch etching using an etchant including an additive type auxiliary etchant; Forming a gate insulating film over the gate wiring and the gate electrode of the double layer structure; Forming a semiconductor layer over the gate insulating film; A molybdenum (Mo) layer and a copper (Cu) layer are sequentially formed on the semiconductor layer and the gate insulating layer, and the additive is an auxiliary type auxiliary additive capable of lowering the potential difference between copper and molybdenum. Batch etching is performed using an etchant including an etchant to form a data wiring having a double layer structure of molybdenum and copper intersecting the gate wiring on the gate insulating film, and at the same time, a double layer structure branching from the data wiring over the semiconductor layer. A method of manufacturing an array substrate for a liquid crystal display device, the method comprising: forming a source electrode and a drain electrode spaced apart from the source electrode.

As such, the present invention relates to an etchant for Cu / Mo batch etching and an etching method of Cu / Mo using such an etchant.

The etchant comprises a main etchant composed of an oxidizing agent and an etching agent of Cu, and an auxiliary etchant which is a kind of additive capable of preventing undercutting of the Mo metal by lowering the potential difference between the Cu metal and the Mo metal. It is done.

Examples of the oxidizing agent of Cu include hydrogen peroxide and iron nitrate (Fe (NO ₃ ) ₃ ), preferably hydrogen peroxide, and the Cu etchant may be acetic acid, ammonium acetate (CH ₃ C0ONH ₄ ), sulfuric acid ( H ₂ SO ₄ ), preferably acetic acid. The additive is preferably ammonium acetate. In the etching process of Cu / Mo, ammonium acetate is mild to ammonium ions and acetate ions, and ammonium ions among these ionic materials serve to lower the potential difference between copper and molybdenum.

6A to 6C are sectional views illustrating an etching process of Cu / Mo wiring according to the present invention.

In FIG. 6A, the Mo metal layer 102 and the Cu metal layer 104 are sequentially deposited on the transparent substrate 100, and the PR layer 106 having a predetermined pattern is formed on the Cu metal layer 104. Step.

Although not shown in the drawings, the forming of the PR layer 106 includes applying a PR material and placing a mask having a predetermined pattern on the PR material to form the PR layer 106 through exposure and development. It's a step.

In this step, the Cu / Mo wiring formation region VIa and the peripheral region VIb, which are regions where the PR layer 106 is located, are defined on the substrate.

In FIG. 6B, the Cu layer (104 in FIG. 4A) and the Mo layer (102 in FIG. 4A) are collectively etched using the PR layer 106 as a mask to form the first and second metal metal layers 108a and 108b, respectively. Step.

At this time, the batch etching etchant is composed of a main etchant and additives, the main etchant is preferably a mixed etchant of acetic acid and hydrogen peroxide, the additive is selected from a material that can lower the potential difference between the Cu metal and Mo metal. Next, ammonium acetate is used.

The addition ratio of the additive is not limited, it is preferable to mix and use in the main etchant in a state dissolved in a certain amount in DI water.

In the batch etching process, the ammonium acetate lowers the potential difference between the Cu metal and the Mo metal, thereby reducing the reactivity of the highly oxidizing Mo metal, thereby preventing the undercut phenomenon of the Mo metal even when both metals are simultaneously etched using the same etchant. You can prevent it.

In FIG. 6C, the PR layer 106 is stripped after the batch etching step to complete the metal wiring 108 including the first and second metal layers 108a and 108b.

As illustrated, in the present invention, after the etching process of the metal wiring 108 using Cu / Mo, the transparent substrate 100 in the VIa region where the metal wiring 108 is formed and the VIb region where the transparent substrate 100 is exposed. The planarization characteristic of the metal wire 108 can be kept constant and the data characteristic of the metal wiring 108 can be improved.

7 is a cross-sectional view of a thin film transistor for a liquid crystal display device to which a Cu / Mo wiring according to the present invention is applied.

As illustrated, in the thin film transistor T including the gate electrode 110, the semiconductor layer 112, and the source and drain electrodes 114 and 116, the gate electrode 110, the source and drain electrodes 114. And 116 are each composed of a Cu metal layer having a barrier layer as a lower layer.

In more detail, the gate electrode 110 is composed of the first and second gate metal layers 110a and 110b, and the source and drain electrodes 114 and 116 are the first and second source metal layers 114a and 114b and the drain. The electrode 116 is composed of first and second drain metal layers 116a and 116b, wherein the second gate, source and drain metal layers 110b, 114b and 116b are formed of Mo metal layers, and the first gate, source and drain The metal layers 110a, 114a, and 116a are made of a Cu metal layer, and these two metal layers are collectively etched.

8 is a diagram showing the taper characteristics of Cu / Mo wiring according to the present invention, in which the deposition thicknesses of Cu / Mo are 2,000 Å and 100 각각, respectively, and the batch etching method according to the present invention has a JET (Just Etch time) of 50 sec. The taper characteristics of the Cu / Mo wiring formed by the present invention can be seen, and as shown, the step portions between the Mo metal layer constituting the lower layer and the Cu metal layer constituting the upper layer are formed in a uniformly connected pattern.

Such a Cu / Mo wiring according to the present invention can be applied to a gate wiring and a data wiring for a liquid crystal display device, and can also be applied to a metal wiring for an electronic device including a liquid crystal display device.

However, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the spirit of the present invention.

As described above, according to the etchant for Cu / Mo wiring batch etching according to the present invention, it is possible to form a Cu / Mo wiring with improved taper characteristics in one etching process, thereby developing a product having improved production yield, and a reliable metal. The provision of wiring can promote the development of large area and high resolution liquid crystal display devices, and can extend the scope of application to related electronic products.

Claims (6)

Sequentially depositing a molybdenum (Mo) layer and a copper (Cu) layer on the substrate; Forming a wiring photoresist layer on the copper layer; The main etchant including an oxidizing agent and an etchant for the copper layer exposed to the outside of the photoresist layer and the molybdenum layer below the copper layer, and the molybdenum layer to lower the potential difference between the copper layer and the molybdenum layer Forming a Cu / Mo wiring having an inclined side by collectively etching the molybdenum layer and the copper layer using an etchant including a dropping additive type auxiliary etchant; Batch etching method of Cu / Mo wiring comprising a. The method of claim 1, Wherein the oxidant is hydrogen peroxide (H ₂ O ₂ ), and the etching agent is acetic acid (CH ₃ COOH). The method of claim 1, The auxiliary etchant is an etchant containing ammonium acetate (CH ₃ C0ONH ₄ ) is a batch etching method of Cu / Mo wiring. The method of claim 3, wherein The auxiliary etchant includes a batch etching method of Cu / Mo wiring including DI water. The method of claim 1, The deposition thickness of the molybdenum layer and the copper layer is 50 kPa ~ 200 kPa, 1500 kPa ~ 2500 kPa, the batch etching method of the Cu / Mo wiring. A first molybdenum (Mo) layer and a first copper (Cu) layer are sequentially formed on the substrate, and a potential difference between the main etchant including an oxidizing agent and an etchant, and the first copper layer and the first molybdenum layer The first molybdenum layer and the first copper layer are collectively etched by using an etchant comprising an auxiliary etchant of an additive type that lowers the reactivity of the first molybdenum layer. Forming a gate wiring having a double-layer structure consisting of one molybdenum layer and said first copper layer and a gate electrode branched from said gate wiring; Forming a gate insulating film over the gate wiring and the gate electrode; Forming a semiconductor layer over the gate insulating film; A second molybdenum (Mo) layer and a second copper (Cu) layer are sequentially formed on the semiconductor layer and the gate insulating layer, and a main etchant including an oxidizing agent and an etching agent, the second copper layer, and the second By lowering the potential difference of the molybdenum layer and batch etching using the etchant including the auxiliary etchant of the additive type to reduce the reactivity of the second molybdenum layer, the gate insulating film intersects with the gate wiring. A data layer having a double layer structure formed of the second molybdenum layer and the second copper layer having an inclined side surface, and at the same time, a source electrode branched from the data line over the semiconductor layer, and a drain spaced apart from the source electrode. Forming an electrode Method of manufacturing an array substrate for a liquid crystal display device comprising a.

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