KR100806800B1 - Array substrate of liquid crystal display and manufacturing method of the same - Google Patents

Abstract

The present invention is an array substrate for a liquid crystal display device suitable for high opening ratio, high resolution, and large area by using a polycrystalline silicon layer as a semiconductor layer in a so-called TFT on color filter (TOC) structure in which a thin film transistor is formed on a color filter layer. It is to provide. The array substrate for a liquid crystal display device according to the present invention includes a black matrix layer formed on the insulating substrate at regular intervals, a color filter layer formed in a space between the black matrix layers, and a front surface of the substrate including the color filter layer. A planarization film formed, a buffer layer formed on the planarization film, a polycrystalline silicon layer patterned on the buffer layer, a gate electrode formed on the polycrystalline silicon layer, and a substrate front including the gate electrode. A first passivation layer formed on the first passivation layer, a source / drain electrode formed on the first passivation layer to be connected to the semiconductor layer through a first contact hole, and a second passivation layer formed on the entire surface of the substrate including the source / drain electrode; And a pixel electrically connected to the drain electrode on the second passivation layer through a second contact hole. It comprises an electrode.

High resolution, low temperature polysilicon, TOC

Description

Array substrate for liquid crystal display device and manufacturing method therefor {Array substrate of liquid crystal display and manufacturing method of the same}

1 is a structural cross-sectional view of an array substrate for a liquid crystal display device according to a first prior art.

2 is a cross-sectional structural view of an array substrate for a liquid crystal display device according to a second prior art.

3 is a structural cross-sectional view of an array substrate for a liquid crystal display device according to the present invention;

4A through 4D are cross-sectional views illustrating an array substrate for a liquid crystal display device and a method of manufacturing the same according to the present invention.

Explanation of symbols for the main parts of the drawings

301: insulating substrate 302: black matrix layer

303: color filter layer 304: planarization film

305: buffer layer 306: polycrystalline silicon layer

307: gate insulating film 308: gate electrode

310: first passivation layer 311, 312: source / drain electrode

313: second passivation layer 314: pixel electrode

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device and a method for manufacturing the same. In particular, a polycrystalline silicon is used as a semiconductor layer in a so-called TFT on color filter (TOC) structure that forms a thin film transistor on a color filter layer, thereby achieving high resolution, large area, and high aperture ratio. The present invention relates to an array substrate for a liquid crystal display device and a method of manufacturing the same.

Although TFT-LCDs have high density and large area, and TFT mobility is urgently required to fabricate display parts and driving circuit parts on the same substrate, amorphous silicon thin film transistors (a-Si: H TFT) ) Is difficult to satisfy. Recently, a polysilicon thin film transistor (Poly-Si TFT) has attracted much attention as a method to effectively solve this problem. Since polycrystalline silicon TFTs have high mobility, they have the advantage of allowing peripheral circuits to be integrated on glass substrates, thus attracting much attention in terms of reducing production costs.

Polycrystalline silicon TFTs have higher mobility than amorphous silicon TFTs, and are advantageous as switching elements of high-resolution panels, and are suitable for projection panels in which a lot of light is emitted due to less photocurrent compared to amorphous silicon TFTs. Smaller panels and higher resolutions are mainly used for high-temperature processes, while lower-temperature processes are mainly used for larger panels. The main goal is to reduce the cost of materials by incorporating drive ICs.

On the other hand, low-temperature polycrystalline silicon formation methods include solid phase crystallization, laser crystallization, direct deposition, and metal heat treatment, but low-temperature glass substrates can be used at a low temperature of 450 ° C. or lower, and laser, which is the closest to large-area crystallization, can be used. Crystallization is the most popular.

Hereinafter, an array substrate for a liquid crystal display device according to the prior art will be described in detail with reference to the drawings.

1 is a structural cross-sectional view of an array substrate for a liquid crystal display device according to the prior art.

As shown in FIG. 1, a buffer layer 102 is formed on an insulating substrate 101 such as a glass substrate to reduce the influence of impurities on the glass substrate, and a polycrystalline silicon material is formed on the buffer layer 102. The semiconductor layer 103 is patterned. A gate insulating layer 104 is patterned on the semiconductor layer 103, and a gate electrode 105 is formed on the gate insulating layer 104. An insulating first protective film 106 is formed on the entire surface of the substrate including the gate electrode 105. Source / drain electrodes 107 and 108 electrically connected to the semiconductor layer 103 are formed on the first passivation layer 106 through the first contact hole. A second passivation layer 109 is formed over the entire surface of the substrate including the source / drain electrodes 107 and 108, and the pixel electrode 110 for applying a voltage to the liquid crystal is formed on the second passivation layer 109. It is formed to be connected to the drain electrode 108 through.

2 is a structural cross-sectional view of an array substrate for a liquid crystal display device according to another exemplary embodiment.

As shown in FIG. 2, black matrices 202 are formed on the insulating substrate 201 at regular intervals, and R, G, and B are used to implement color expression in the spaces between the black matrix layers 202. The color filter layer 203 is formed, and the planarization film 204 is formed on the entire substrate including the color filter layer 203. A gate electrode 205 is formed on the planarization film 204. A gate insulating layer 206 is stacked on the entire surface of the substrate including the gate electrode 205, and a semiconductor layer 207 made of amorphous silicon is formed on the gate insulating layer 206. The conductive source / drain electrodes 208 and 209 are patterned on the amorphous silicon semiconductor layer 207, and a passivation layer 210 is formed on the entire surface of the substrate including the source / drain electrodes 208 and 209. The pixel electrode 211 for applying a voltage to the liquid crystal on the passivation layer 210 is formed to be connected to the drain electrode through the contact hole.

However, the conventional liquid crystal display array substrate and its manufacturing method have the following problems.

The array substrate for a liquid crystal display device having the structure shown in FIG. 1 has the disadvantage of deterioration in resolution due to unevenness when the upper and lower plates are bonded. The liquid crystal display device having the structure shown in FIG. 2 uses amorphous silicon as a semiconductor layer. Due to the low mobility it is not applicable to high-speed operation circuit, there is a problem that can not be mounted to the driver IC on the board to the large area.

The present invention has been made to solve the above problems, by using a polycrystalline silicon as a semiconductor layer in a so-called TOC (TFT On Color filter) structure to form a thin film transistor on the color filter layer, high resolution, large area and high aperture ratio An object of the present invention is to provide an array substrate for a liquid crystal display device and a method of manufacturing the same.

The array substrate for a liquid crystal display device of the present invention for achieving the above object is a black matrix layer formed on the insulating substrate at regular intervals, a color filter layer formed in a space between the black matrix layer, and the color filter layer A planarization film formed over the entire substrate, a buffer layer formed on the planarization film, a polycrystalline silicon layer patterned on the buffer layer, a gate electrode formed on the polycrystalline silicon layer, and the gate electrode A first passivation layer formed over the entire surface of the substrate including the first passivation layer, a source / drain electrode formed on the first passivation layer so as to be connected to the semiconductor layer through a first contact hole, and formed on the front surface of the substrate including the source / drain electrode; And a second protective film formed on the second protective film and electrically connected to the drain electrode through a second contact hole. And a pixel electrode connected to each other, wherein the manufacturing method includes forming a black matrix layer at a predetermined interval on an insulating substrate, forming a color filter layer in a space between the black matrix layers, and the color. Forming a planarization film over the entire surface of the substrate including the filter layer, forming a polycrystalline silicon layer on the planarization film, forming a gate electrode on the polycrystalline silicon layer, and firstly forming a gate electrode over the substrate including the gate electrode; Forming a passivation layer, forming a source / drain electrode on the first passivation layer so as to be connected to the semiconductor layer through a first contact hole, and forming a second passivation layer on the entire surface of the substrate including the source / drain electrode; And forming a pixel electrode on the second passivation layer so as to be electrically connected to the drain electrode through a second contact hole. It characterized by comprising the step.

On the other hand, a black matrix layer is formed on a substrate facing the substrate to prevent light from being transmitted to the thin film transistor formed on the substrate.

Hereinafter, an array substrate for a liquid crystal display device and a method of manufacturing the same according to the present invention will be described in detail with reference to the accompanying drawings.

3 is a structural cross-sectional view of an array substrate for a liquid crystal display device according to the present invention.

As shown in FIG. 3, black matrices 302 are formed on the insulating substrate 301 at predetermined intervals, and R, G, and B are used to implement color expression in the spaces between the black matrix layers 302. A color filter layer 303 is formed, and a planarization film 304 is formed over the entire substrate including the color filter layer 303. A buffer layer 305 is formed on the planarization film 304 to reduce the influence of impurities on the glass substrate, and a semiconductor layer 306 of polycrystalline silicon is patterned on the buffer layer 305. . A gate insulating layer 307 is patterned on the semiconductor layer 306, and a gate electrode 308 is formed on the gate insulating layer 307. An insulating first protective film 309 is formed on the entire surface of the substrate including the gate electrode 308. Source / drain electrodes 310 and 311 electrically connected to the semiconductor layer are formed on the first passivation layer 309 through the first contact hole. A second passivation layer 312 is formed on an entire surface of the substrate including the source / drain electrodes 310 and 311, and a pixel electrode 313 that applies a voltage to the liquid crystal on the second passivation layer 312 includes a second contact hole. It is formed to be connected to the drain electrode 311 through.

Here, the material of the buffer layer is a silicon compound including silicon oxide, silicon nitride, and the material of the planarization layer is BCB (Benzocyclobutene), HSQ (Hydrogen Silsesquioxane), SSQ (Silsesquioxane), MSSQ (Methyl Silsesquioxane), POSS (Polyhedral Oligomeric Silsesquioxane) All organic compounds whose properties are hardened by Cure after spin coating such as FO _x (Flowable Oxide) are possible.

4A through 4D are cross-sectional views illustrating an array substrate for a liquid crystal display device and a method of manufacturing the same according to the present invention.

As shown in FIG. 4A, the color filter layer 303 is formed on the insulating substrate 301 at a predetermined interval, and implements color expression in the space between the black matrix layers 302. To form. Thereafter, the planarization film 304 is coated on the entire surface of the substrate including the color filter layer 303 using spin coating. The material of the planarization layer may be any organic compound whose physical properties are hardened by Cure after spin coating such as BCB (Benzocyclobutene), HSQ, SSQ, MSSQ, POSS, FO _x and the like.

Subsequently, as illustrated in FIG. 4B, a buffer layer 305 is formed by stacking a silicon compound such as silicon oxide or silicon nitride on the planarization film 304 to reduce the influence of impurities on the glass substrate. Subsequently, silicon or amorphous silicon material is deposited on the buffer layer 305 by chemical vapor deposition, and then irradiated with laser to form polycrystalline silicon 306a.

As shown in FIG. 4C, after forming the semiconductor layer 306 by patterning the polycrystalline silicon layer 306a, a chemical vapor deposition method and a sputtering method are performed on the semiconductor layer 306. After the deposition by using, in order to pattern the gate insulating film 307 and the gate electrode 308 to form.

As shown in FIG. 4D, an insulating first passivation layer 309 is formed over the entire surface of the substrate including the gate electrode 308, and then the semiconductor layer is formed through the first contact hole on the first passivation layer 309. Each of the source / drain electrodes 310 and 311 electrically connected to the 306 is formed. Thereafter, a second passivation layer 312 is formed over the entire surface of the substrate including the source / drain electrodes 310 and 311, and the pixel electrode 313 for applying a voltage to the liquid crystal is formed on the second passivation layer to form a second contact hole. It is formed to be connected to the drain electrode 311 through.

Subsequently, although not shown in the drawings, the process of manufacturing the liquid crystal display device according to the present invention is completed by bonding to a substrate having a black matrix formed thereon to prevent light transmission to the thin film transistor facing the substrate, and encapsulating after liquid crystal injection. .

As described above, the liquid crystal display array substrate of the present invention and its manufacturing method have the following effects.

By forming a color filter layer and a thin film transistor on one substrate, it is possible to solve the problem of total pitch due to non-uniformity of upper and lower plates and to achieve high opening ratio. There is an advantage to reap.

Claims (10)

A black matrix layer formed on the insulating substrate at regular intervals; A color filter layer formed in a space between the black matrix layers; A planarization layer formed over the entire surface of the substrate including the color filter layer; A buffer layer formed on the planarization film, and a polycrystalline silicon layer patterned on the buffer layer; A gate electrode formed on the polycrystalline silicon layer; A first passivation layer formed over the entire surface of the substrate including the gate electrode; A source / drain electrode formed on the first passivation layer so as to be connected to the polycrystalline silicon layer through a first contact hole; A second passivation layer formed over an entire surface of the substrate including the source / drain electrodes; And a pixel electrode electrically connected to the drain electrode through the second contact hole on the second passivation layer. The array substrate of claim 1, wherein the material of the planarization layer is one of benzocyclobutene (BCB), HSQ, SSQ, MSSQ, POSS, and FO _x . The array substrate of claim 1, wherein the material of the buffer layer is one of silicon oxide (SiO ₂ ), silicon nitride (SiN _x ), or silicon nitrogen oxide (SiN _xy O _y ). Forming a black matrix layer on the insulating substrate at regular intervals; Forming a color filter layer in a space between the black matrix layers; Forming a planarization film over the entire substrate including the color filter layer; Forming a buffer layer on the planarization film; Forming a polycrystalline silicon layer on the buffer layer; Forming a gate electrode on the polycrystalline silicon layer; Forming a first passivation layer over the entire surface of the substrate including the gate electrode; Forming a source / drain electrode on the first passivation layer to be connected to the polycrystalline silicon layer through a first contact hole; Forming a second passivation layer over an entire surface of the substrate including the source / drain electrodes; And forming a pixel electrode on the second passivation layer so as to be electrically connected to the drain electrode through a second contact hole. The method of claim 4, wherein the material of the planarization layer is one of BCB (Benzocyclobutene), HSQ, SSQ, MSSQ, POSS, and FO _x . The method of claim 4, wherein the material of the buffer layer is one of silicon oxide (SiO ₂ ), silicon nitride (SiN _x ), and silicon nitrogen oxide (SiN _xy O _y ). The process of claim 4, wherein the polycrystalline silicon layer is formed, Forming an amorphous silicon layer on the buffer layer; And crystallizing the amorphous silicon layer to form a polycrystalline silicon layer. The method of claim 7, wherein the crystallization of the amorphous silicon layer is performed through laser irradiation. The array substrate of claim 2, wherein the planarization layer is formed by a cur after spin coating. 6. The method of claim 5, wherein the planarization layer is formed by a curing process after spin coating.

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