KR100791626B1 - Programable clock generator and Pipelined Convertor therewith - Google Patents

Abstract

A pipelined converter using a programmable clock generator and a programmable clock generator is disclosed.

According to the present invention, a first programmable inversion unit having an input terminal connected to a reference clock and varying an interval for inverting the reference clock according to a predetermined control voltage, an inverter unit connected to the reference clock to invert the reference clock, and the inverter A second programmable inverter configured to vary an interval for inverting the input terminal signal according to a predetermined control voltage, a set input connected to the reference clock, and a reset input connected to an output of the first programmable inverter. The first latch circuit and the set input connected to the inverter unit and the reset input includes a second latch circuit connected to the output of the second programmable inverting unit.

According to the present invention, it is possible to implement a high-resolution ADC while maintaining the linearity of the pipelined ADC circuit while lowering power consumption, and by using a clock signal having an optimum duty ratio by changing the control voltage according to power consumption. Therefore, the power consumption can be minimized.

Description

Programmable clock generator and Pipelined Convertor therewith}

1 is a circuit diagram showing one stage in a conventional pipeline converter.

2A is a timing diagram of a clock signal and an output signal used in FIG. 1.

FIG. 2B is a graph showing a simulation result with respect to FIG. 2A.

3 is a block diagram of a pipeline converter to which the present invention is applied.

4 is a block diagram of a programmable clock generator in accordance with one embodiment of the present invention.

5A is a detailed circuit diagram of FIG. 4.

FIG. 5B is a timing diagram of the node-by-node signal of FIG. 5A.

6 is a block diagram of a programmable clock generator in accordance with another embodiment of the present invention.

FIG. 7A is a detailed circuit diagram of FIG. 6.

FIG. 7B is a timing diagram of the node-by-node signal of FIG. 7A.

8 is a block diagram of a pipeline converter using a programmable clock generator in accordance with another embodiment of the present invention.

9 is a block diagram of a pipeline converter using a programmable clock generator in accordance with another embodiment of the present invention.

10A is a timing diagram of a clock signal and an output signal according to FIGS. 4 and 6.

10B is a graph showing a simulation result with respect to FIG. 10A.

TECHNICAL FIELD The present invention relates to a clock generator, and more particularly, to a pipeline converter using a programmable clock generator and a programmable clock generator.

Currently, many researches for implementing low power pipeline ADC (Analog to Digital Convertor) have been focused on the power-consuming amplifier (Amp) field.

The first method is to share and use an amplifier. The MD amp's op amp is used only during the holding, that is, the amplification period, and the stage of the adjacent MDAC is used. ) Performs the function with the clock signals opposite each other at the same time. Therefore, one op amp is divided and used during each amplification period in the MDAC of two adjacent stages.

This method can reduce the number of op amps used in the entire stage by half, which can greatly reduce power consumption, but there are various other disadvantages.

First, an additional switch is required, and this switch has a series resistance component, which causes the settling characteristic of each stage to decrease together with the sampling capacitor of the input stage. In addition, when high-speed operation is required, the effect of the on-resistance is further increased, thereby reducing the linearity of the circuit. Of course, this effect can be reduced by adjusting the size of the switch, but the method of increasing the size also introduces a trade-off relationship that increases characteristics such as charge injection and clock feed through. Will have The increase in these switches therefore requires additional sophisticated designs to reduce many error sources.

The second method to reduce the power consumption of the amplifier (Amp) is to implement the gain in an open loop structure using a subtractor (Subtractor).

1 is a circuit diagram showing one stage in a conventional pipeline converter.

A plurality of switches and stages that are opened and closed according to a sampling phase Φ 1 or a holding phase Φ 2 include the ADC 110, the DAC 120, and the amplifier 130.

During the sampling phase, F1, the analog input signal is sampled by the sampling capacitor Cs. In this case, the Most Significant Bit (MSB) is determined by comparing an analog input signal with a reference value.

During the holding phase, Ф2, the capacitor is switched towards the DAC 120 output, and the residual components are amplified and compared to a reference value.

The next stage performs the same operation in a phase opposite to the previous stay.

FIG. 2A is a timing diagram of the clock signals Ф1 and Ф2 and the output signal Vres (l) used in FIG.

FIG. 2A shows an output result of MDAC when a clock signal having a typical 50% / 50% duty is applied. Although settling is being performed during the MDAC amplification cycle, it can be seen that a faster settling time is required to satisfy the high resolution. Therefore, this result requires an op amp having a wider unity gain frequency.

FIG. 2B is a graph showing a simulation result with respect to FIG. 2A.

Therefore, in the conventional pipeline converter, the gain is sensitively changed according to the characteristics of channel length modulation and mismatch of the transistor, so that it is very difficult to maintain the linearity of the entire circuit, The implementation of the ADC that requires the application is limited, there is a problem that the power consumption is large.

Therefore, the first technical problem to be achieved by the present invention is to provide a programmable clock generator that can maintain the linearity of the pipelined ADC circuit, and implement a high resolution ADC while lowering power consumption.

A second technical object of the present invention is to provide a pipeline converter using the programmable clock generator.

In order to solve the first technical problem described above, the present invention is a first programmable inverting unit is connected to the reference clock, the first programmable inverting unit for varying the interval for inverting the reference clock according to a predetermined control voltage, An inverter unit for inverting a reference clock, an input terminal is connected to the inverter unit, a second programmable inverter for varying an interval for inverting the input terminal signal according to a predetermined control voltage, a set input is connected to the reference clock, and a reset Providing a programmable clock generator comprising a first latch circuit having an input coupled to the output of the first programmable inverter and a second latch circuit having a reset input coupled to the inverter and a reset input coupled to the output of the second programmable inverter do.

In addition, in order to solve the first technical problem described above, the present invention is connected to a first programmable delay unit, the input terminal is connected to the reference clock, the variable delay period for delaying the reference clock according to a predetermined control voltage, the reference clock An inverter unit for inverting the reference clock, an input terminal of the inverter unit is connected, a second programmable delay unit for varying a period for delaying the reference clock according to a predetermined control voltage, and a set input is connected to the reference clock And a third latch circuit having a reset input connected to the output of the first programmable delay unit and a fourth latch circuit having a reset input connected to the inverter unit and a reset input connected to the output of the second programmable delay unit. To provide.

Meanwhile, in order to solve the above second technical problem, the present invention provides a pipelined analog-to-digital converter of an M stage for converting an analog signal into a bit value of a corresponding M bit for an arbitrary integer N of a predetermined integer M or less. A first programmable inversion unit having an input terminal coupled to a reference clock and varying an interval for inverting the reference clock according to a predetermined control voltage, an inverter unit connected to the reference clock to invert the reference clock, and the inverter unit A second programmable inverter configured to vary an interval for inverting the input terminal signal according to a predetermined control voltage, a set input connected to the reference clock, and a reset input connected to an output of the first programmable inverter; N-1th stage clock of the pipeline analog-to-digital converter A first latch circuit and a set input applied to the output to the inverter unit and a reset input to the output of the second programmable inverter to apply an output signal to the N-th stage clock input of the pipeline analog-to-digital converter. A pipeline converter using a programmable clock generator comprising a second latch circuit is provided.

In addition, in order to solve the second technical problem described above, the present invention provides a pipelined analog-to-digital converter of M stages for converting an analog signal into a bit value of a corresponding M bit for an arbitrary integer N below a predetermined integer M. A first programmable delay unit having an input terminal coupled to a reference clock and varying an interval for delaying the reference clock according to a predetermined control voltage, an inverter unit connected to the reference clock to invert the reference clock, and the inverter unit A second programmable delay unit configured to vary an interval for delaying the reference clock according to a predetermined control voltage, a set input connected to the reference clock, and a reset input connected to an output of the first programmable delay unit Output signal to the N-1 th stage of the analog-to-digital converter of the pipeline; A third latch circuit and a set input applied to the last clock input are connected to the inverter section, and a reset input is connected to the output of the second programmable delay section, and the output signal is connected to the N-th stage clock input of the pipeline analog to digital converter section. A pipeline converter using a programmable clock generator including a fourth latch circuit to be applied is provided.

In order to solve the problems of the conventional pipeline converter, the present invention provides a new method of sample / hold method that can implement low power consumption and maintain linearity of the entire circuit without requiring a separate circuit. to provide.

The sample / hold time technique, or programmable clock generator, according to the present invention reduces the power consumption of MDAC, the largest power dissipation part of the pipeline ADC, thus eliminating the need for a separate circuit design. The line ADC can be designed for applications in mobile applications such as wired and wireless communication systems and digital video equipment.

Hereinafter, with reference to the drawings will be described a preferred embodiment of the present invention.

3 is a block diagram of a pipeline converter to which the present invention is applied.

Pipeline converters, or pipelined ADCs, have a sample & hold that first converts the analog inputs to the corresponding DC values at the input, and are comparators, sub A / D converters, sub D / A converters, subtractors, and gains. Amp is included. In particular, the D / A converter, the subtractor and the gain amplifier (Amp) are combined to be referred to as MDAC.

D-flip flops, such as delay cells, are used to delay and synchronize the digital outputs at each stage.

Each stage is synchronized with a clock signal by a programmable clock generator in accordance with the present invention.

The operation of the MDAC op amp Amp is limited to the hold mode, i.e., the amplification period, thus providing a clock signal that uses a portion of the sampling period for the amplification period. At this time, the duty cycle is not 50% / 50%.

A case in which the clock signal according to the present invention has a duty cycle of 25/75% is described as an example.

If one cycle is 20ns, a clock signal with a duty cycle of 25/75%, compared to a typical clock with a 50% / 50% duty cycle, has a 5ns sampling time when the input signal is fully charged to the sample capacitor. With a 15ns amplification cycle. Therefore, when the duty cycle of 25/75%, it can be seen that the margin for the settling time by 5 ns increases.

It can be seen that the following equations (1), (2) and (3) are established between the characteristics of the op amp (Amp) used in the closed loop structure and the settling time.

Thus, a very wide unity gain frequency is required to settling the output value to a value within the resolution required for each bit during the limited amplification time. However, such a high performance op amp (Amp) not only increases the power consumption due to the increased current consumption, but also has a very difficult design. However, a clock signal with a duty cycle of 25% / 75% enables the use of low power op amps, thereby reducing the power consumption of pipeline ADCs.

A clock scheme with a duty ratio of 25% / 75% will have 150% of the time of the conventional amplification time, resulting in low power with less unity gain frequency due to this settling time margin. The op amp of the amplifier has a sufficiently stable output value.

In addition, since the digital value processed in each bit is also operated at the same time as the amplification of MDAC, the increased margin provides a wider margin for the delay of the digital function block. do. Therefore, the design of the digital blocks also has the advantage that it can proceed more easily. In addition, the additional power consumption for implementing a clock scheme with a duty ratio of 25% / 75% is almost negligible.

4 is a block diagram of a programmable clock generator in accordance with one embodiment of the present invention.

The first programmable inverting unit 410 has an input terminal connected to the reference clock EXT CLK, and varies a section for inverting the reference clock EXT CLK according to a predetermined control voltage.

The inverter unit 420 is connected to the reference clock EXT CLK and inverts and outputs the reference clock EXT CLK.

In the second programmable inverting unit 430, an input terminal is connected to the inverter unit 420, and the length of a section for inverting the input terminal signal is changed according to a predetermined control voltage.

The first latch circuit 440 has a set input connected to the reference clock EX CLK, and a reset input connected to the output of the first programmable inverting unit 410.

The second latch circuit 450 has a set input connected to the inverter unit 420, and a reset input connected to the output of the second programmable inverting unit 430.

The inputs and outputs of the first latch circuit 440 and the second latch circuit 450 are shown in Table 1.

S R Q

L L Q (n-1)

(n-1) L H L H H L H L H H not allowed

는 반전 출력을 나타낸다. 또한, L은 로우 레벨, H는 하이 레벨을 나타낸다. Q(n-1),

(n-1)는 이전 레벨을 그대로 유지한다는 것을 나타낸다.In Table 1, S is set input, R is reset input, Q is output,

Indicates an inverted output. In addition, L represents a low level and H represents a high level. Q (n-1),

(n-1) indicates that the previous level is maintained as it is.

5A is a detailed circuit diagram of FIG. 4.

FIG. 5A illustrates a programmable clock generator using a pulse shrink circuit.

By controlling the current flowing through the inverter by applying the control voltage Vcont from the outside, it is possible to adjust the time to fall to the ground of the inverter.

The first programmable inverting unit 510 is configured to change an interval in which an input terminal is connected to the reference clock EXT CLK and inverts the reference clock EXT CLK according to a predetermined control voltage.

The inverter unit 520 is connected to the reference clock EXT CLK and inverts and outputs the reference clock EXT CLK.

The second programmable inverting unit 530 has an input terminal connected to the inverter unit 520 and varies the length of the section for inverting the input terminal signal according to a predetermined control voltage.

In this case, the first programmable inverting unit 510 and the second programmable inverting unit 530 may include a variable inverter circuit 511 for varying an amount of a current inverting an input signal to ground according to a predetermined control voltage. Inverter circuits 512 for inverting signals are alternately arranged.

The first latch circuit 540 has a set input connected to the reference clock EX CLK, and a reset input connected to the output of the first programmable inverting unit 510.

The second latch circuit 550 has a set input connected to the inverter unit 520, and a reset input connected to the output of the second programmable inverting unit 530.

FIG. 5B is a timing diagram of the node-by-node signal of FIG. 5A.

As shown in FIG. 5B, it can be seen that the signal at the node B has the same period as the reference clock EXCL CLK, but the section having 1 as much as ΔT is inverted to zero.

By varying the control voltage Vcont, the duty ratio of the output signal can be freely realized, and based on this, the op-to used in the MDAC of the pipelined-ADC can be used. Amplification, which is the operating period of the amplifier, can be adjusted, enabling the ADC to have the same performance and minimize power consumption from the user's point of view.

6 is a block diagram of a programmable clock generator in accordance with another embodiment of the present invention.

The first programmable delay unit 610 has an input terminal connected to the reference clock EXT CLK, delays and outputs the reference clock EXT CLK according to a predetermined control voltage, and outputs the reference clock EXT CLK according to a predetermined control voltage. The length of the section for delaying) is varied.

The inverter unit 620 is connected to the reference clock EXT CLK and inverts and outputs the reference clock EXT CLK.

The second programmable delay unit 630 has an input terminal connected to the inverter unit 620, delays the reference clock EXT CLK according to a predetermined control voltage, and delays the reference clock EXT CLK according to the predetermined control voltage. The length of the section to be varied.

The third latch circuit 640 has a set input connected to the reference clock EXCL CLK, and a reset input connected to the output of the first programmable delay unit 610.

The fourth latch circuit 650 has a set input connected to the inverter unit 620, and a reset input connected to the output of the second programmable delay unit 650.

At this time, the input and output of the third latch circuit 640 and the fourth latch circuit 650 are shown in Table 1.

FIG. 7A is a detailed circuit diagram of FIG. 6.

FIG. 7A illustrates a programmable clock generator using a delay cell.

The first programmable delay unit 710 has an input terminal connected to the reference clock EXT CLK, delays and outputs the reference clock EXT CLK according to a predetermined control voltage, and outputs the reference clock EXT CLK according to a predetermined control voltage. The length of the section for delaying) is varied.

The inverter unit 720 is connected to the reference clock EXT CLK and inverts and outputs the reference clock EXT CLK.

The second programmable delay unit 730 has an input terminal connected to the inverter unit 720, delays the reference clock EXT CLK according to a predetermined control voltage, and delays the reference clock EXT CLK according to the predetermined control voltage. The length of the section to be varied.

In this case, the first programmable delay unit 710 and the second programmable delay unit 730 include a plurality of inverter circuits 711 for inverting the input signal. In addition, the first programmable delay unit 710 and the second programmable delay unit 730 are continuously provided with a variable inverter circuit 712 for varying an amount of a current inverting an input signal to ground according to a predetermined control voltage. It is arranged form.

The third latch circuit 740 has a set input connected to a reference clock EX CLK, and a reset input connected to an output of the first programmable delay unit 710.

The fourth latch circuit 750 has a set input connected to the inverter unit 720, and a reset input connected to the output of the second programmable delay unit 750.

FIG. 7B is a timing diagram of the node-by-node signal of FIG. 7A.

The circuit of FIG. 7A is similar to the circuit of FIG. 5A, but the order of the pulse shrink circuit is changed, and the signal at the node B has the same period as the reference clock EXCL CLK. It can be seen that the signal delayed by ΔT comes out with. Accordingly, a circuit having a programmable duty ratio can be implemented.

8 is a block diagram of a pipeline converter using a programmable clock generator in accordance with another embodiment of the present invention.

The pipelined analog-to-digital converter 860 is configured with an M stage for converting an analog signal into a bit value of a corresponding M bit for an arbitrary integer N equal to or less than a predetermined integer M.

The first programmable inverting unit 810 has an input terminal connected to the reference clock EXT CLK, and varies a section in which the reference clock EXT CLK is inverted according to a predetermined control voltage. The inverter unit 820 is connected to the reference clock EXT CLK and inverts and outputs the reference clock EXT CLK. The second programmable inverting unit 830 has an input terminal connected to the inverter unit 820, and varies the length of the section for inverting the input terminal signal according to a predetermined control voltage.

Preferably, the first programmable inverting unit 810 and the second programmable inverting unit 830 may include a variable inverter circuit 511 for varying an amount of a current inverting an input signal to ground according to a predetermined control voltage; Inverter circuits 512 for inverting the input signal may be alternately arranged.

The first latch circuit 840 has a set input connected to the reference clock EX CLK, and a reset input connected to the output of the first programmable inverting unit 810. The first latch circuit 840 applies an output signal to the N-1 th stage clock input of the pipeline analog-digital converter 860. The second latch circuit 850 has a set input connected to the inverter unit 820, and a reset input connected to the output of the second programmable inverting unit 830. The second latch circuit 850 applies an output signal to the N-th stage clock input of the pipeline analog-to-digital converter 860.

Preferably, the outputs of the first latch circuit 840 and the second latch circuit 850 are interchanged to apply to the N th stage clock input and the N-1 th clock input of the pipelined analog-to-digital converter 860, respectively. Can be.

Preferably, the first programmable inverting unit 810 and the second control voltage are configured to extend a predetermined control voltage longer than a sampling period in which an analog signal is charged in a sample capacitor (not shown) of the pipeline analog-to-digital converter 860. The control unit may further include a control voltage applying unit 865 applied to the programmable inverting unit 830.

Preferably, the pipelined analog-to-digital converter 860 may include a different number of delay cells for delaying output of the bit value for each stage.

Preferably, the power measuring unit 870 for measuring the power consumption of the pipeline analog-to-digital converter 870 and the control voltage applying unit 865 adjusts the magnitude of the control voltage according to the magnitude of the measured power consumption. The feedback unit 880 may further include.

9 is a block diagram of a pipeline converter using a programmable clock generator in accordance with another embodiment of the present invention.

The pipelined analog-to-digital converter 960 is configured with an M stage for converting an analog signal into a bit value of a corresponding M bit for an arbitrary integer N equal to or less than a predetermined constant M.

The first programmable delay unit 910 has an input terminal connected to the reference clock EXT CLK, delays and outputs the reference clock EXT CLK according to a predetermined control voltage, and outputs the reference clock EXT CLK according to a predetermined control voltage. The length of the section for delaying) is varied. The inverter unit 920 is connected to the reference clock EXT CLK to invert and output the reference clock EXT CLK. The second programmable delay unit 930 has an input terminal connected to the inverter unit 920, delays the reference clock EXT CLK according to a predetermined control voltage, and delays the reference clock EXT CLK according to the predetermined control voltage. The length of the section to be varied.

Preferably, the first programmable delay unit 910 and the second programmable delay unit 930 may include a variable inverter circuit 711 for varying an amount of a current inverting an input signal to ground according to a predetermined control voltage; Inverter circuits 712 for inverting the input signal can be configured to be alternately arranged.

The third latch circuit 940 has a set input connected to the reference clock EX CLK, and a reset input connected to the output of the first programmable delay unit 910. The third latch circuit 940 applies the output signal to the N-th stage clock input of the pipeline analog-to-digital converter 960. The fourth latch circuit 950 has a set input connected to the inverter unit 920, and a reset input connected to the output of the second programmable delay unit 950. The fourth latch circuit 950 applies the output signal to the N-th stage clock input of the pipeline analog-to-digital converter 960.

Preferably, the outputs of the third latch circuit 940 and the fourth latch circuit 950 are interchanged to apply to the N th stage clock input and the N-1 th clock input of the pipeline analog-to-digital converter 960, respectively. Can be.

Preferably, the first programmable delay unit 910 and the second control voltage are configured to extend a predetermined control voltage longer than a sampling period in which an analog signal is charged in a sample capacitor (not shown) of the pipeline analog-to-digital converter 960. The apparatus may further include a control voltage applying unit 965 applied to the programmable delay unit 930.

Preferably, the pipelined analog-to-digital converter 960 may include different numbers of delay cells for delaying output of the bit value for each stage.

Preferably, the power measuring unit 970 measuring the power consumption of the pipeline analog-to-digital converter 970 and controlling the magnitude of the control voltage by the control voltage applying unit 965 according to the measured power consumption. The feedback unit 980 may further include.

10A is a timing diagram of the clock signals Ф1 and Ф2 and the output signal Vres (l) according to FIGS. 4 and 6.

FIG. 10A illustrates the output of MDAC when a clock signal having a varying duty ratio (eg, a duty of 25% / 75%) is applied according to the present invention.

As can be seen from the output result, it operates with the same settling time, but it can be seen that the output of MDAC has a more stable value through a relatively wider amplification cycle.

In order to improve the performance, it is required to adjust the sample and hold time of the entire MDAC while maintaining the characteristics of the amplifier.

Therefore, according to the present invention, an ADC having the same performance can be implemented using an op amp (Amp) that consumes relatively little power, and a pipeline ADC with low power consumption can be designed.

10B is a graph showing a simulation result with respect to FIG. 10A.

It can be seen that the simulation results are similar to those of FIG. 10A.

Although the present invention has been described with reference to one embodiment shown in the drawings, this is merely exemplary and will be understood by those of ordinary skill in the art that various modifications and variations can be made therefrom. However, such modifications should be considered to be within the technical protection scope of the present invention. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

As described above, according to the present invention, while maintaining the linearity of the pipelined ADC circuit, it is possible to implement a high-resolution ADC while lowering power consumption, and having an optimal duty ratio by changing the control voltage according to the power consumption. By using the clock signal, the power consumption can be minimized.

Claims (12)

A first programmable inverting unit connected to an input terminal of the input terminal and varying an interval for inverting the reference clock according to a predetermined control voltage; An inverter unit connected to the reference clock to invert the reference clock; A second programmable inverting unit connected to an input of the inverter and varying a section for inverting the input terminal signal according to a predetermined control voltage; A first latch circuit having a set input coupled to the reference clock and a reset input coupled to an output of the first programmable inverter; And A set input is coupled to the inverter portion, and a reset input comprises a second latch circuit coupled to an output of the second programmable inverter portion, The first programmable inverter and the second programmable inverter And a variable inverter circuit for varying an amount of the current inverting the input signal flowing to ground according to a predetermined control voltage and an inverter circuit for inverting the input signal. delete A first programmable delay unit connected to an input terminal of the input terminal and varying an interval for delaying the reference clock according to a predetermined control voltage; An inverter unit connected to the reference clock to invert the reference clock; A second programmable delay unit having an input terminal connected to the inverter unit and varying an interval for delaying the reference clock according to a predetermined control voltage; A third latch circuit having a set input coupled to the reference clock and a reset input coupled to an output of the first programmable delay portion; And A fourth latch circuit coupled to a set input coupled to the inverter portion, and a reset input coupled to an output of the second programmable delay portion; The first programmable delay unit and the second programmable delay unit And a plurality of inverter circuits for inverting the input signal are arranged, and a variable inverter circuit for varying the amount of the current inverting the input signal flowing to the ground in accordance with a predetermined control voltage is arranged in succession. . delete For any integer N less than or equal to the predetermined constant M, A pipelined analog-to-digital converter of M stages for converting an analog signal into bit values of corresponding M bits; A first programmable inverting unit connected to an input terminal of the input terminal and varying an interval for inverting the reference clock according to a predetermined control voltage; An inverter unit connected to the reference clock to invert the reference clock; A second programmable inverting unit connected to an input of the inverter and varying a section for inverting the input terminal signal according to a predetermined control voltage; A first latch circuit having a set input coupled to the reference clock and a reset input coupled to an output of the first programmable inverter, for applying an output signal to the N-1 th stage clock input of the pipeline analog to digital converter; A second latch circuit connected to a set input connected to the inverter unit and a reset input connected to an output of the second programmable inverting unit to apply an output signal to an Nth stage clock input of the pipeline analog to digital converter; The first programmable inverter and the second programmable inverter Pipeline converter using a programmable clock generator, characterized in that the variable inverter circuit for varying the amount of the current inverting the input signal flows to ground in accordance with a predetermined control voltage and the inverter circuit for inverting the input signal are alternately arranged. . delete The method of claim 5, A control voltage applying unit configured to apply a predetermined control voltage to the first programmable inverting unit and the second programmable inverting unit to extend the amplification period to a sampling capacitor in which the analog signal is charged to the sample capacitor of the pipeline analog to digital converter. And a pipeline converter using a programmable clock generator. The method of claim 5, A power measuring unit measuring power consumption of the pipeline analog to digital converter; And And a feedback unit for adjusting the magnitude of the predetermined control voltage according to the measured power consumption. For any integer N less than or equal to the predetermined constant M, A pipelined analog-to-digital converter of M stages for converting an analog signal into bit values of corresponding M bits; A first programmable delay unit connected to an input terminal of the input terminal and varying an interval for delaying the reference clock according to a predetermined control voltage; An inverter unit connected to the reference clock to invert the reference clock; A second programmable delay unit having an input terminal connected to the inverter unit and varying an interval for delaying the reference clock according to a predetermined control voltage; A third latch circuit having a set input connected to the reference clock and a reset input connected to an output of the first programmable delay unit to apply an output signal to the N-1 th stage clock input of the pipelined analog-digital converter; And A fourth latch circuit for connecting a set input to the inverter unit and a reset input to an output of the second programmable delay unit to apply an output signal to the N-th stage clock input of the pipelined analog-to-digital converter; The first programmable delay unit and the second programmable delay unit And a plurality of inverter circuits for inverting the input signal are arranged, and a variable inverter circuit for continuously varying the amount of the current inverting the input signal flowing to the ground according to a predetermined control voltage. Pipeline converter. delete The method of claim 9, And a control voltage applying unit configured to apply a predetermined control voltage to the first programmable delay unit and the second programmable delay unit to extend the amplification interval to the sample capacitor of the pipeline analog to digital converter. And pipeline converter using a programmable clock generator. The method of claim 9, A power measuring unit measuring power consumption of the pipeline analog to digital converter; And And a feedback unit for adjusting the magnitude of the predetermined control voltage according to the measured power consumption.

Images