JP2001117667A - Phase-locked loop(pll)/clock generator having programmable deviation and frequency - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a PLL clock generator for dynamically changing generated clock frequency, and for dynamically adjusting the deviation of a clock signal. SOLUTION: In this phase-locked loop(PLL)/clock generator 300 having programmable frequencies and deviation, the frequencies of a generated clock signal are dynamically changed by a computer program, and the deviation of the generated clock signal can be adjusted dynamically. Also, the deviation of the signal due to the change of loading can be compensated. Thus, the deviation of the clock signal can be controlled satisfactorily by the PLL clock generator 300 based on a closed loop constitution, and high level stability and durability can be realized for the system.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

FIELD OF THE INVENTION The present invention relates generally to clock generators and, more particularly, to a phase locked loop (PLL) having programmable offset and frequency.
-Regarding a clock generator.

[0002]

2. Description of the Related Art With the advancement of semiconductor technology, the operating frequency of digital circuit systems is increasing. Therefore, clock synchronizatio
Problem n) is an important issue for designers.
Clock synchronization includes not only a single clock signal, but also multiple clock signals. Generally, the skew of a clock signal is determined by a clock generator or loading based on an open loop configuration. As the trace length from the clock generator to the load becomes longer or the load increases, the problem of clock signal drift becomes more acute. For example, many devices shared a single clock generator on a computer motherboard. Further, the memory size can be dynamically changed according to a user's request. In addition, there are many interface slots for connecting to peripherals depending on practical requirements. Therefore, the loading on the clock signal is changed according to the change in the memory scale and the amount of peripheral devices. No wonder that the open loop configuration cannot resolve the signal drift. On the other hand, it is necessary to change the frequency of the clock signal. If all clock signals are provided by an external clock generator, it is difficult to arbitrarily change the clock frequency since the frequency of the clock signal is fixed.

FIG. 1 is a schematic block diagram of a computer motherboard using a conventional clock generator.
In the figure, a single clock generator 150 outputs a clock signal CP.
U-CLK and SYS-CLK are provided. The clock signal CPU-CLK is connected to the CPU 110 and the chipset (c
The clock signal SYS-CLK is providing a signal to the chipset 120 and the devices 141-14N via a bus 130 while providing a signal to the chipset 120 and the devices 141-14N. Since the chipset 120 is responsible for controlling the operation of the computer motherboard, the clock signal SY
It is necessary to refer to both the S-CLK and the clock signal CPU-CLK. The devices 141 to 14N are peripheral devices. Various numbers of peripherals can be connected to the computer motherboard, and therefore the clock signal SYS-C
The loading on the LK varies depending on the number of connected devices. Changing the loading on the clock signal SYS-CLK affects the clock signal shift and consequently the overall system stability.

[0004] If the multiplexed clock signal is
If provided to the devices in the system from zero, the designer can better control the clock signal drift to give the system more stability and durability.
Further, the frequency of the clock signal can be dynamically changed by a computer program.

[0005]

In summary, the conventional clock generator has the following disadvantages. 1. If the clock signal is provided by an external clock generator, the frequency of the clock signal can be easily changed, especially by a computer program. 2. Clock signals provided based on the open loop configuration are affected by loading changes that result in significant difficulties in controlling clock signal drift, and the resulting system stability.

It is therefore an object of the present invention to provide a phase locked loop (PLL) clock generator having a programmable frequency that dynamically changes the generated clock frequency.

It is another object of the present invention to provide a PLL clock generator having a programmable offset which dynamically adjusts the offset of the clock signal.

[0008]

In accordance with the above objects of the present invention, there is provided a phase locked loop (PLL) clock generator having a programmable frequency and offset, wherein the clock signal is provided. It is generated based on the reference signal. The clock generator includes a plurality of first delay devices each having a first terminal and a second terminal;
A multiplex communication device; a plurality of second delay devices each having a first terminal and a second terminal; a second multiplex communication device;
LL signal generator.

[0009] The plurality of first delay devices are sequentially cascaded by connecting the second terminal of one first delay device to the first terminal of the adjacent first delay device.
One of the plurality of first delay devices has a first terminal connected to the reference signal.

The first multiplex communication device has a plurality of input terminals, an output terminal, and a first selection input. The plurality of input terminals of the first multiplex communication device are respectively connected to the reference signal and the second terminals of the plurality of first delay devices, and one of the plurality of input signals to the first multiplex communication device is It is connected by a first selection input and is coupled to an output terminal of a first multiplex communication device.

The plurality of second delay devices are sequentially cascaded by connecting the second terminal of one second delay device to the first terminal of the adjacent second delay device.
A first terminal of one of the second delay devices is connected to the feedback signal.

The second multiplex communication apparatus has a plurality of input terminals, an output terminal, and a second selection input. The plurality of input terminals of the second multiplex communication device are connected to the feedback signal and the second terminals of the plurality of second delay devices, respectively, and one of the plurality of input signals to the second multiplex communication device is: Selected by the second selection input and coupled to the output terminal of the second multiplex communication device.

The PLL signal generator has a first input terminal, a second input terminal, and an output terminal. A first input terminal of the PLL signal generator is connected to an output terminal of the first multiplex communication device, and a second input terminal of the PLL signal generator is connected to a second input terminal.
It is connected to the output terminal of the multiplex communication device. The clock signal is generated from the output terminal of the PLL signal generator and is fed back, thereby functioning as a feedback signal via a conductive line.

According to a preferred embodiment of the present invention, a clock signal is fed back at the midpoint of the conductive line to function as a feedback signal, providing a clock signal required by an external device.

The PL in the PLL clock generator described above
The L signal generator includes a plurality of first dividers each having an input terminal and an output terminal, a third multiplex communication device, a plurality of second dividers each having an input terminal and an output terminal, and a fourth multiplex communication device. , A PLL core circuit, a plurality of third dividers each having an input terminal and an output terminal, and a fifth multiplex communication device.

The input terminals of the plurality of first dividers are connected to the output terminals of the first multiplex communication device.

The third multiplex communication apparatus has a plurality of input terminals, an output terminal, and a third selection input. The input terminals of the third multiplex communication device are connected to the output terminals of the plurality of first dividers, respectively, and one of the plurality of input signals to the third multiplex communication device is selected by the third selection input to perform the third multiplex. It is connected to the output terminal of the communication device.

The input terminals of the plurality of second dividers are connected to the output terminals of the second multiplex communication device.

The fourth multiplex communication device has a plurality of input terminals, an output terminal, and a fourth selection input. The plurality of input terminals of the fourth multiplex communication device are respectively connected to the output terminals of the plurality of second dividers, and one of the plurality of input signals to the fourth multiplex communication device is selected by the fourth selection input, and It is coupled to the output terminal of the device for multiplex communication.

The PLL core circuit has a reference input terminal, a feedback input terminal, and an output terminal. PL
The L-core circuit generates a signal at an output terminal based on a phase difference between a signal at a reference input terminal and a signal at a feedback input terminal. The reference input terminal is connected to the output terminal of the third multiplex communication device, and the feedback input terminal is connected to the output terminal of the fourth multiplex communication device.

The input terminals of the plurality of third dividers are connected to the output terminals of the PLL core circuit.

The fifth multiplex communication device has a plurality of input terminals and output terminals. A plurality of input terminals of the fifth multiplex communication device are respectively connected to output terminals of the plurality of third dividers, and a clock signal is generated from an output terminal of the fifth multiplex communication device.

The foregoing general description and the following detailed description are exemplary and are intended to provide further explanation of the invention as claimed.

[0024]

BRIEF DESCRIPTION OF THE DRAWINGS The accompanying drawings provide a further understanding of the present invention, and are incorporated in and constitute a part of this specification.
The drawings illustrate embodiments of the invention and, together with the disclosure, serve to explain the principles.

Preferred embodiments of the present invention will be described in detail, and examples of the embodiments are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used in the drawings and the description to refer to the same or substantially the same element.

FIG. 2 is a block diagram of a phase locked loop (PLL) signal generator 200 having a programmable frequency, according to a preferred embodiment of the present invention.
As shown in FIG. 2, the PLL signal generator 200 generates a clock signal CLK2 having a variable frequency based on the reference signal REF-CLK. PLL signal generator 200
Are dividers 211 to 21N, multiplex communication device 220, dividers 231 to 23N, multiplex communication device 240, PLL core circuit 250, dividers 261 to 26N
N, multiplex communication device 270 and multiplex communication device 280
It has.

The reference signal REF-CLK is supplied to the divider 211
~ 21N input terminals and dividers 211 ~ 21
N divides the frequency of the reference signal REF-CLK by a different number and obtains signals of different frequencies as the outputs of the dividers 211 to 21N. Then, dividers 211 to 21N
Is connected to the input terminal of the multiplex communication device 220 controlled by the selection input REF-SEL. Therefore, one of the plurality of inputs to the multiplex communication device 220 is selected as the output signal REF-CLK '. Reference signal REF-CLK and multiplex communication device 2
The ratio between the output signal REF-CLK 'from 20 can be determined by the select input REF-SEL.

The feedback signal FB-CLK is connected to the input terminals of the dividers 231 to 23N.
1 to 23N divide the frequency of the feedback signal FB-CLK by different numbers to obtain signals of different frequencies as the outputs of the dividers 231 to 23N. Then, the output signals from the dividers 231 to 23N are connected to the selection input FB-S
It is connected to the input terminal of the multiplex communication device 240 controlled by the EL. Therefore, the multiplex communication device 240
Is selected as the output signal FB-CLK '. Feedback signal FB-CLK
And an output signal FB-CL from the multiplex communication device 240
The ratio between K 'can be determined by the selection input FB-SEL.

The PLL core circuit 250 is responsible for performing the main functions of the PLL signal generator 200. The PLL signal generator 200 outputs the output signal REF from the multiplex communication device 220.
-CLK ', a reference input terminal R-IN connected to the output signal FB-CLK' from the multiplex communication device 240, and an output terminal PO for generating the output signal CLK. Contains. PLL
The core circuit 250 determines the frequency and phase of the output signal CLK based on the phase difference between the output signal REF-CLK 'from the multiplex communication device 220 and the output signal FB-CLK' from the multiplex communication device 240. Can be adjusted. Therefore, the phase difference between the signal REF-CLK 'and the signal REF-CLK' can be minimized.

The output signal CLK from the output terminal PO of the PLL core circuit 250 is connected to the input terminals of the dividers 261 to 26N. The dividers 261 to 26N are connected to the signal CL.
The frequency of K is divided by different numbers and divided by dividers 261-26.
Signals of different frequencies are obtained as N outputs. Output signals from the dividers 261 to 26N are output to the multiplex communication device 27.
0 and the input terminal of the multiplex communication device 280. One of a plurality of inputs to the multiplex communication device 280 controlled by the selection input SEL is selected as an output clock signal CLK2 required by an external circuit.

The multiplex communication apparatus 270 generates an output signal CLK1 functioning as a feedback signal FB-CLK. Then, the feedback signal FB-CL
K denotes the dividers 231 to 23N and the multiplex communication device 240.
, To the feedback input terminal F-IN of the PLL core circuit 250 to form a closed phase loop. The use of the multiplexing device 270 is not for selecting a frequency for the feedback signal FB-CLK. Instead, multiplexing device 270 provides signal C
The time delay between LK1 and signal CLK2 (time d
elay), and is used to better control clock signal drift.

It is understood from the above-described PLL signal generator 200 that clock signal CLK having a desired frequency is used.
2 is a selection input REF based on the reference signal REF-CLK.
-SEL, FB-SEL, and SEL. Reference signal REF-CLK
_{Has a} frequency fr, the reference signal RE
The ratio between F-CLK and signal REF-CLK 'is N determined by select input REF-SEL, and the ratio between feedback signal FB-CLK and signal FB-CLK' is select input FB-SEL. And the ratio between the signals CLK and CLK1 is fixed at one. Therefore, the signal CLK generated by the PLL signal generator 200 has a frequency of f _r ^* N / D. The multiplex communication device 280 outputs a clock signal CLK having a desired frequency.
2 has been used to select. By using many multiplexing devices, it is possible to provide clock signals with different frequencies required by different types of circuits.

Based on the above-described PLL signal generator 200, it is possible to better control the deviation of the clock signal described in detail below.

FIG. 3 is a block diagram of a phase locked loop (PLL) clock generator 300 having a programmable frequency and offset. PLL clock generator 300 generates a clock signal CLK1 requested by an external circuit based on reference signal REF-CLK0. As shown in FIG. 3, the PLL clock generator 30
0 indicates delay devices 311 to 31N and multiplex communication device 32
0, delay devices 331 to 33N, multiplex communication device 340,
And a PLL signal generator 200. Delay device 3
11 to 31N are sequentially cascaded. The reference signal REF-CLK0 is connected to an input terminal of the first delay device 311. The multiplex communication device 320 includes:
A plurality of input terminals, an output terminal, and a selection input are provided. The input terminal of the multiplex communication device 320 is connected to the reference signal RE.
F-CLK0 and the outputs of the delay devices 311 to 31N, respectively. The multiplex communication device 320 selects the input S1 in such a manner that one of the plurality of inputs of the multiplex communication device 320 is selected as the output signal REF-CLK.
Is controlled by At that time, the output signal REF-C
LK is connected to PLL signal generator 200.

Similarly, the delay devices 331 to 33N
They are cascaded sequentially. Feedback signal FB-
CLK0 is connected to the input terminal of the first delay device 331. The multiplex communication device 340 has a plurality of input terminals, output terminals, and selection inputs. Multiplex communication device 34
0 are input to the feedback signal FB-CL
K0 and the outputs of the delay devices 331-33N, respectively. The multiplex communication device 340 is controlled by the selection input S2 in such a way that one of the plurality of input terminals of the multiplex communication device 340 is selected as the output signal FB-CLK. At that time, the output signal FB-CLK becomes P
It is connected to the LL signal generator 200.

The PLL signal generator 200 in FIG. 3 is shown in FIG. 2 and includes a reference input terminal, a feedback input terminal, and an output terminal. The reference input of the PLL signal generator 200 is connected to a signal REF-CLK from the output of the multiplexing device 320, while the PLL
The feedback input terminal of the signal generator 200 is connected to the signal FB-CLK from the output terminal of the multiplex communication device 340. A clock signal CLK1 is generated by a PLL signal generator 200, and a conductive line 3
It functions as a feedback signal FB-CLK0 via the reference numeral 50. As shown in FIG. 2, the PLL core circuit 250 in the PLL signal generator 200 outputs the output signal C
The frequency and phase of LK are adjusted, and the signal REF-CLK '
FB-CLK 'is minimized. The output signal CLK is composed of a signal REF-CLK 'and a signal FB.
−CLK ′. The PLL signal generator 200 can generate the clock signal CLK1 based on the relationship between the reference signal REF-CLK and the feedback signal FB-CLK.

Signal delay due to line length
In consideration of the above, the clock signal CLK1 is fed back and the conductive line 350
Functions as a feedback signal FB-CLK0 via

Therefore, the PLL clock generator 300
Controlled by the selection inputs S1 and S2, the reference signal RE
Delay device 3 between F-CLK0 and signal REF-CLK
11-31N, as well as the feedback signal FB-C
Delay devices 331 to 331 between LK0 and signal FB-CLK
It is also adjusted by 3N. Therefore, the clock signal C
The deviation of LK1 can be controllably minimized.

FIG. 4 shows a phase locked loop (PLL).
FIG. 2 is a schematic block diagram of a computer motherboard using a clock generator. As shown in FIG.
The chipset 420 includes PLL clock generators 421 and 422. The PLL clock generator 421 has C
A clock signal CPU-CLK is generated for the PU 410, and the PLL clock generator 422 outputs the clock signal SYS-CLK to the devices 441 to 44N via the bus 430.
Generate Bus 430 is based on a reference SREF from reference signal generator 450. PLL clock generators 421 and 422 having a structure as shown in FIG.
It generates clock signals CPU-CLK and SYS-CLK based on the reference signal SREF from the reference signal generator 450. Clock signals CPU-CLK and SYS-CLK generated from PLL clock generators 421 and 422
The frequency and the deviation are adjusted separately. for that reason,
A clock signal having a desired frequency is obtained, and the clock signal CP
The deviation between U-CLK and SYS-CLK is minimized. To indicate loading on the device, the feedback signal is taken at the midpoint of the line length from the output of the PLL clock generator to the device. Therefore, the feedback signal and
The deviation from the clock signal to the device can be maintained in the same way. For example, the clock signal CPU-CLK is connected to the conductive line 4
The information is provided to the CPU 410 via 61. The feedback signal is taken at the midpoint of line 461 and
It is connected to a PLL clock generator 421 via 62. Similarly, the clock signal SYS-CLK is connected to the conductive line 4
It is connected to the bus 430 via 71. The feedback signal is taken at an appropriate location on bus 430 and is connected to PLL clock generator 422 via conductive line 472.

The clock signal CPU transmitted to the CPU 410 based on the computer motherboard described above.
-CLK and the frequency of the clock signal SYS-CLK transmitted to the devices 441 to 44N can be adjusted based on the operating speed of the CPU 410 and the devices 441 to 44N.
The deviation of the clock signal CPU-CLK can be adjusted depending on the actual distance between the CPU 410 and the chipset 420. Furthermore, the deviation of the clock signal SYS-CLK can also be adjusted depending on the actual loading on the bus 430 and the number of devices connected to the bus 430. Therefore, CP
The deviation of the clock signal transmitted to U410 and the devices 441 to 44N can be minimized.

Also, in accordance with a preferred embodiment of the present invention, a PLL clock generator in a chipset on a computer motherboard can provide the clock signal required by the system. Further, clock signal drift can be better controlled through a closed loop configuration of the PLL clock generator. Clock signal deviations can also be adjusted by computer programs based on actual requirements. For example, if many memories or interface cards are assembled, and as a result the actual loading and the deviation of the clock signal are increased, the delay time of the signal from the reference input is reduced by the clock signal. It has been increased to compensate for the shift. To change jumper settings on the motherboard, the user (us
Manual operation by er) is not required. Conversely, the loading imposed on the clock signal is the basic input / output system (B
IOS) program automatically. Therefore, the setting of the deviation can be automatically adjusted.

In summary, a PL with programmable frequency and offset according to a preferred embodiment of the present invention
The L clock generator has the following advantages. 1. The frequency of the clock signal generated by the PLL clock generator can be dynamically changed by a computer program. 2. Since the clock signal generated by the PLL clock generator can be dynamically adjusted by a computer program, the deviation of the clock signal can be better controlled.

As will be apparent to those skilled in the art, various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. It is intended in view of the above that the present invention includes modifications and variations of this invention, provided that such modifications and variations fall within the scope of the claims and their equivalents. .

[0044]

In summary, a P with programmable frequency and offset according to a preferred embodiment of the present invention
The LL clock generator has the following advantages. 1. The frequency of the clock signal generated by the PLL clock generator can be dynamically changed by a computer program. 2. Since the clock signal generated by the PLL clock generator can be dynamically adjusted by a computer program, the deviation of the clock signal can be better controlled.

[Brief description of the drawings]

FIG. 1 is a schematic block diagram of a computer motherboard using a conventional clock generator.

FIG. 2 illustrates a preferred embodiment of the present invention.
FIG. 2 is a block diagram of a phase locked loop (PLL) signal generator having a programmable frequency.

FIG. 3 is a block diagram of a phase locked loop (PLL) clock generator with programmable frequency and offset.

FIG. 4 is a schematic block diagram of a computer motherboard using a phase locked loop (PLL) clock generator.

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Wang Wei, 526, 3rd Floor, Fifth Section, Zhongxiao East Road, Taipei, Taiwan 5B079 BA20 BB10 BC03 CC02 CC14 DD03 DD06 DD20 5J106 CC52 CC58 DD09 DD34 GG10 HH10 KK32

Claims (3)

[Claims] 1. A phase locked loop (PLL) clock generator having a programmable frequency and a deviation for generating a clock signal based on a reference signal, the PLL clock generator comprising a first terminal and a second terminal. A plurality of first delay devices each having a plurality of input terminals, an output terminal, and a first multiplex communication device having a first selection input; and a plurality of second delay devices each having a first terminal and a second terminal. A second multiplex communication device having a plurality of input terminals, an output terminal, and a second selection input; and a P having a first input terminal, a second input terminal, and an output terminal.
An LL signal generator, wherein the plurality of first delay devices are a second delay device of one first delay device.
A terminal is connected in cascade sequentially by connecting a first terminal of the adjacent first delay device, and a first terminal of one of the plurality of first delay devices is connected to the reference signal. The input terminals of the first multiplex communication device are respectively connected to the reference signal and the second terminals of the plurality of first delay devices, and the input terminals of the plurality of input signals to the first multiplex communication device are connected. One of the second delay devices is selected by the first selection input and coupled to an output terminal of the first multiplex communication device;
By connecting the terminal and the first terminal of the adjacent second delay device, the terminals are sequentially cascaded, and the first terminal of one of the plurality of second delay devices is connected to the feedback signal. A plurality of input terminals of the second multiplex communication device are connected to the feedback signal and second terminals of the plurality of second delay devices, respectively, and a plurality of input signals to the first multiplex communication device are connected. One is selected by the second selection input and coupled to an output terminal of the second multiplex communication device, and a first input terminal of the PLL signal generator is connected to an output terminal of the first multiplex communication device. A second input terminal of the PLL signal generator is connected to an output terminal of the second multiplex communication device, and the clock signal requested by an external device is generated from an output terminal of the PLL signal generator. And the clock signal, by being fed back, PLL clock generator having a programmable frequency and displacement, characterized in that function as the feedback signal through the conductive line. 2. The PLL clock generator according to claim 1, wherein said clock signal functions as a feedback signal by being fed back at an intermediate point of said conductive line. PLL clock generator with programmable frequency and offset. 3. The PLL clock generator according to claim 1, wherein said PLL signal generator comprises a plurality of first dividers each having an input terminal and an output terminal; and a plurality of input terminals. A third multiplex communication device having an input terminal, an output terminal, and a third selection input; a plurality of second dividers each having an input terminal and an output terminal; and a plurality of input terminals, an output terminal, and a fourth selection input. A four-way multiplex communication device, a PLL core circuit having a reference input terminal, a feedback input terminal, and an output terminal; a plurality of third dividers each having an input terminal and an output terminal; and a fourth having a plurality of input terminals and an output terminal. A fifth multiplex communication device, wherein input terminals of the plurality of first dividers are connected to output terminals of the first multiplex communication device; An input terminal of a multiplex communication device is connected to an output terminal of each of the plurality of first dividers, and one of a plurality of input signals to the third multiplex communication device is selected by the third selection input, and An input terminal of the third multiplex communication device is coupled to an output terminal of the third multiplex communication device; an input terminal of the plurality of second dividers is connected to an output terminal of the second multiplex communication device; One of a plurality of input signals to the fourth multiplex communication device is selected by the fourth selection input and connected to the output terminal of the fourth multiplex communication device. The reference input terminal is connected to an output terminal of the third multiplex communication device, and the feedback input terminal is connected to an output terminal of the fourth multiplex communication device; A signal is generated from the output terminal based on a phase difference between a signal of an input terminal and a signal of the feedback input terminal; input terminals of the plurality of third dividers are connected to output terminals of the PLL core circuit; A programmable frequency, wherein an input terminal of the multiplex communication device is connected to an output terminal of each of the plurality of third dividers, and the clock signal is generated from an output terminal of the fifth multiplex communication device. And PLL clock generator with offset.