KR100636329B1 - Multi network interface card and method of the multi network interface card - Google Patents

Abstract

The present invention relates to the integration of a network interface device used in a transmission system of a network, and supplies clock signals of a frequency required in each mode to integrate respective modes operated by clock signals of different frequencies, The present invention relates to an integrated network interface device and a method of operating the same, which select and operate a block signal suitable for each operation mode.

Integrated Network Interface Unit, Clock Signal, Field Programmable Gate Array (FPGA), Asynchronous Transfer Mode (ATM), Line Interface Unit (LIU)

Description

MULTI NETWORK INTERFACE CARD AND METHOD OF THE MULTI NETWORK INTERFACE CARD}             

1 is a block diagram of an integrated network interface device according to the present invention.

2 is a flowchart illustrating the operation of the integrated network interface device according to the present invention.

The present invention relates to a network interface device used in a transmission system of a network and a method of operating the same, and more particularly, to an integrated network device capable of supporting a plurality of transmission methods and a method of operating the same.

Generally, a transmission system of a network is implemented using various network interface devices as needed. For example, consider DS3 and E3 in Asynchronous Transfer Mode (ATM). Current ATM network interface devices can support DS3 or E3 respectively. Of course, other network interface devices are the same. However, by using different network interface devices according to the respective methods as described above, there may be problems such as incompatibility between products, difficulty in shape management of products, and redundant investment of development costs. In order to solve these problems, integration of various network interface devices is required.

Accordingly, an object of the present invention is to provide a network interface device incorporating DS3 and E3 of an ATM system and a method of operating the same.

Another object of the present invention is to provide a network interface device for implementing DS3 and E3 of an ATM system on a single PCB and a method of operating the same.

It is still another object of the present invention to provide a network interface device and a method of operating the same, in which a plurality of devices using different frequencies are used in a network transmission system.

Still another object of the present invention is to provide a network device and a method of operating the same, which can implement a plurality of interfaces used in a network transmission system on a single PCB.

The present invention to provide such objects; A network interface device used for a transmission system of a network, comprising: a plurality of operating modes, a LIU (Line Interface Unit) operating in one mode selected from the plurality of operation modes, and a respective operation mode of the LIU. A clock generator for generating a plurality of corresponding clock signals, a clock signal corresponding to an operation mode to be executed, is selected from the clock generator and output to the LIU, and the LIU is controlled to be executed An integrated network interface device is provided which includes a clock controller for driving a mode.

In addition, the present invention; A network interface device of an asynchronous transmission mode system, comprising: a LIU operating in a DS3 or E3 mode, a clock generator for generating a clock signal for DS3 and a clock signal for E3, and an operation mode to be executed is the DS3 mode. In this case, the clock generator selects the clock signal for DS3 and outputs it to the LIU. If the operation mode to be executed is the E3 mode, the clock generator selects the clock signal for E3 and outputs the signal to the LIU. After that, it proposes an integrated network interface device comprising a clock control unit for controlling the LIU to drive each mode to be executed.

In addition, the present invention; A transmission system comprising an integrated network interface device operating in a plurality of modes by providing different clock signals to a LIU, the transmission system comprising: a first process of selecting an operation mode of the network interface device, and a clock corresponding to the selected operation mode; And a third process of selecting a signal, and providing a selected clock signal to the LIU, and controlling the LIU to drive the selected operation mode. Suggest.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. In describing the present invention, if it is determined that the detailed description of the related known function or configuration may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted.

The present invention described below relates to a network interface device incorporating a plurality of devices using clock signals of different frequencies and a method of operating the same. It is assumed that the network interface device to which the present invention described below is applied differs only in the frequency of the clock signal to be used, and the other parts are the same device.

The present invention provides a clock generator capable of providing a clock signal required by each device for integrating a plurality of devices using clock signals of different frequencies, and a control for selecting a clock signal corresponding to each operation mode. It may include a circuit. Hereinafter, the present invention will be described. The description of the present invention will be made by taking a network interface device incorporating DS3 and E3 of an Asynchronous Transfer Mode (ATM) system as an example. However, this is only to help the understanding of the present invention, the present invention is not limited thereby. The present invention can be applied to all devices that satisfy the above requirements.

DS3 and E3 of the ATM system have a circuit that processes data in ATM cells only, differing only in clock frequency and pulse shape in terms of physical line characteristics; The software is the same. That is, DS3 and E3 of the ATM system satisfy the prerequisites for the application of the present invention. Hereinafter, the present invention will be described using the integration of DS3 and E3 in an ATM system.

1 is a configuration diagram of an integrated network interface device according to the present invention.

The Line Interface Unit (LIU) 100 of FIG. 1 is a commercial chip that supports both DS3 and E3. A typical DS3 / E3 LIU commercial chip is designed to interface the DS3 and E3 by controlling the input clock and the DS3 / E3 select pin.

The first clock generator 120 or the second clock generator 130 provides a clock signal requested by the LIU 100. In this case, the first clock generator 120 and the second clock generator 130 should be implemented to supply a clock synchronized with the system synchronization source. This is because the network interface device must be interfaced in synchronization with the system synchronization source. As shown in FIG. 1, when the first clock generator 120 and the second clock generator 130 generate their respective clock signals, a reference clock signal 107 as a reference thereof is It is provided to each clock generator 120 or 130 from the clock controller 110. In this case, the clock controller 110 generates a reference clock signal 107 provided to the clock generator 120 or 130 by using the recovery clock 105 received from the LIU 110.

In the present embodiment incorporating DS3 and E3 of the ATM system, the first clock generation unit 120 supplies a 44.736 MHz clock signal (first clock signal in FIG. 1) 109, which is a clock for DS3, to the LIU 100. To provide. The second clock generator 130 provides a clock signal (second clock signal of FIG. 1) 111 of 34.368 MHz, which is a clock for E3, to the LIU 100. At this time, the clock signal provided by the first clock generator 120 or the second clock generator 130 is selectively provided to the LIU 100 according to the operation of the LIU 100. That is, when the LIU 100 operates as DS3, the clock signal of the first clock generator 120 is provided to the LIU 100. When the LIU 100 operates as E3, the clock of the second clock generator 130 is applied. The signal is provided to the LIU 100. Here, the first clock generator 120 and the second clock generator 130 may be implemented using an IC integrated circuit phase locked loop (PLL). If possible, the first clock generator 120 and the second clock generator 130 may be implemented as one clock generator that generates both the clock signal for DS3 and the clock signal for E3.

The clock control unit 110 provides an integrated network interface device according to the present invention so that a suitable clock signal among the clock signals of the first clock generator 120 or the second clock generator 130 can be provided to the LIU 100. To control. The clock controller 110 selects a clock generator 120 or 130 that generates a clock signal suitable for the operation mode of the LIU 100, receives a clock signal from the selected clock generator, and outputs the clock signal to the LIU 100. The clock controller 110 may select the operation mode of the LIU 100 by outputting a selection signal 101 indicating the operation mode of the LIU 100 to the LIU 100. The clock controller may be implemented using an FPGA or the like.

The ATM part 140 is a general configuration of an ATM system except for a network interface device. Detailed description of the ATM part 140 will be omitted.

Next, the implementation of the clock control unit 110 using the FPGA will be described.

The clock controller 110 should be assigned a pin to control the DS3 or E3 control pin of the LIU 100.

The clock controller 110 should be able to generate the reference clock signal 107 of the first clock generator 120 or the second clock generator 130 from the recovery clock signal 105 received from the LIU 100. do. In this case, the clock controller 110 may be configured to generate the reference clock signal 107 by discriminating whether it is a DS3 clock signal or an E3 clock signal. In general, the clock controller 110 divides the recovery signal 105 to generate the reference clock signal 107.

The clock controller 110 selects a suitable clock signal according to the operation mode of the LIU 100. That is, when the LIU 100 operates as a DS3, the clock controller 110 receives a clock signal 109 of 44.736 MHz from the first clock generator 120, outputs the clock signal 109 to the LIU 100, and outputs the LIU 100. If the E3 is operated as E3 receives the clock signal 111 of 34.368MHz from the second clock generator 130 and outputs to the LIU (100).

The three operations of the clock controller 110, that is, the operation mode selection of the LIU 100, the clock signal selection to be provided to the LIU 100, and the reference clock signal 107 for the clock generator 120 or 130. A detailed description of the provision is as follows. Described here is an embodiment in which the clock controller 110 is implemented using an FPGA.

First, the clock controller 110 may select an operation mode of the LIU 100 using the following logic.

The following is a code according to an embodiment of the DS3 / E3 selection of the clock control unit 110.

Here, the value is set to HIGH (1) when operating in DS3 and LOW (0) when operating in E3. Of course, this setting may vary as needed. The meaning of each variable in the code is as follows.

fpga_p_reset: A signal for applying a reset to a network interface device when power is applied.

wr_en: An interface write signal between the CPU (not shown) and the clock control unit 110 in the network interface device.

DS3_E3_select: DS3 / E3 control signal output by the clock control unit 110 to the LIU 100. Corresponds to 101 signal of FIG.

DS3_E3_select_signal: Signal for DS3 / E3 control signal from clock control unit 110 to LIU 100.

DS3_E3_select_cs: DS3_E3_select register signal to check the selection.

bpd (0 to 7): Interface signal between the CPU in the network interface device and the clock control unit 110, the data signal.

On the other hand, in the code, the network interface device is set to operate as DS3 upon initial power application. This setting can be changed depending on whether the product mainly operates with E3 or DS3, and thus the present invention is not limited thereto. The clock controller 110 may change the DS3_E3_select signal under the control of a CPU (not shown).

Next, the selection of the clock signal to be provided to the LIU 100 performed by the clock control unit 110 will be described. The following is an example of code that the clock control unit 110 selects a clock signal.

Tx_clock <= DS3_clock when DS3_E3_select_signal = '0' else E3_click;

The meanings of the variables used in the code are as follows.

Tx_clock: DS3 or E3 clock provided to LIU (100). Corresponds to 103 in FIG. 1.

DS3_clock: A clock signal having a frequency of 44.736 MHz, which is a clock signal of DS3. Corresponds to 109 of FIG. 1.

E3_clock: A clock signal having a frequency of 34.368 MHz, which is a clock signal of E3. Corresponds to 111 of FIG. 1.

The clock controller 110 may select a clock signal provided to the LIU 100 according to the DS3_E3_select signal.

Finally, the logic for generating the reference clock signal 107 to be provided to the clock generator 120 or 130 from the recovery signal 105 received by the clock control unit 110 from the LIU 100 will be described. This logic can be configured to select the counter value to divide when the value of DS3_E3_select_signal is 1 or 0 to generate a reference clock signal suitable for each interface.

The following is the code according to an embodiment of the generation of the reference clock signal 107 using the recovery signal 105, which is performed by the clock control unit 110.

The meanings of the variables used in the code are as follows.

Count_rclk: Counting variable for dispensing.

Cnt_reclk: Count variable for dispensing.

The code is a code for generating a reference clock signal of 8 kHz.

As described above, the integrated network interface device according to the present invention includes the LIU 100 capable of operating as DS3 or E3, and clock generators 120 and 130 for generating a clock signal for DS3 and a clock signal for E3, respectively. ) And a clock control unit 110 that selects and provides a suitable clock signal to the LIU 100 according to an operation mode of the LIU 100. Expanding this further, the present invention could be used not only for the integration of DS3 / E3 but also for the integration of other network interfaces.

Next, a method according to the present invention will be described with reference to the accompanying drawings.

2 is a flowchart illustrating the operation of the integrated network interface device according to the present invention.

2 is a flowchart illustrating an operation according to the above-described code.

In operation 200, when power is applied to the network interface device, the clock controller 110 receives a reset signal fpga_p_reset from a CPU (not shown) of the network interface device. In operation 200, the clock controller 110 determines whether the applied fpga_p_reset signal has a value of “1”. The fpga_p_reset signal may have a value of "1" or "0". As the code shows, when the fpga_p_reset signal is "0", the network interface device operates in DS3 mode. Therefore, if it is determined in step 202 that the fpga_p_reset signal has a value of "0" instead of "1", the network interface device is set as 210. By setting 210, the DS3 / E3 selection signal 101 has a "high" value, that is, a "1" value. The clock controller 110 generates a DS3 / E3 selection signal 101 having a value of “1” and outputs the same to the LIU 100. The LIU 100 that receives the DS3 / E3 selection signal 101 having the value “1” is operated in the DS3 mode. The clock signal 103 provided to the LIU 100 becomes 44.736 MHz, which is a clock signal of the DS3.

On the other hand, even if the fpga_p_reset signal has a value of "1", the network interface device may operate in the E3 mode. Steps 204, 206, and 208 of FIG. 2 are processes for determining whether the network interface device operates in the DS3 mode or the E3 mode.

In step 204, the clock controller 110 determines whether the DS3_E3_select_cs signal has a value of “0”. If the DS3_E3_select_cs signal does not have a value of "0", that is, if the DS3_E3_select_cs signal has a value of "1", the network interface device operates in the DS3 mode and is set as 210.

On the other hand, if the DS3_E3_select_cs signal has a value of "0", the clock controller 110 receives the bpd (7) value as the value of DS3_E3_select_signal. The bpd (7) value can be a value of "0" or "1".

In step 208, the clock controller 110 determines whether the value of DS3_E3_select_signal is “0”. If the value of the DS3_E3_select_signal is not "0", that is, the value of the DS3_E3_select_signal is "1", the network interface device operates in the DS3 mode and is set as 210.

On the other hand, if the value of DS3_E3_select_signal is "0", the network interface device operates in the E3 mode and is set as 212. That is, the network interface device operates at E3, and a clock signal having a frequency of 34.368 MHz, which is a clock signal of E3, is provided to the LIU 1000.

As described above, the present invention creates a separate network interface device by integrating the network interface device operating in the DS3 mode and the network interface device operating in the E3 mode, and by enabling the operation in the appropriate mode according to the needs of the system It eliminates the inconvenience of using.

Meanwhile, the present invention can be extended not only to the DS3 / E3 mode of an ATM system but also to other network interface devices using only clock signals differently in a transmission system.

By applying the present invention as described above, it is possible to implement the DS3 and E3 method of the ATM-based transmission system using a clock signal of different frequencies using one network interface device. This can reduce the development period and reduce development costs.

Claims (13)

In the network interface device used in the network transmission system, A LIU (Line Interface Unit) including a plurality of operation modes and operating in one mode selected from the plurality of operation modes; A clock generator which generates a plurality of clock signals corresponding to each operation mode of the LIU; An integrated network interface device including a clock control unit configured to select a clock signal corresponding to an operation mode to be executed from the clock generator and output the clock signal to the LIU, and to control the LIU to drive the operation mode to be executed; . The method of claim 1, wherein the LIU, The integrated network interface device, characterized in that the commercial chip that supports all the plurality of operating modes. The method of claim 1, wherein the clock control unit, And a reference clock signal for generating each clock signal to the clock generator. The method of claim 1, wherein the clock control unit, Integrated network interface device implemented in FPGA. The method of claim 1, wherein the clock generator, And a plurality of IC PLLs each generating clock signals corresponding to each of the plurality of operating modes. In the network interface device of the asynchronous transmission mode system, LIU running in DS3 or E3 mode, A clock generator for generating a clock signal for DS3 and a clock signal for E3; If the operation mode to be executed is the DS3 mode, the clock generator selects the clock signal for the DS3 and outputs the signal to the LIU. If the operation mode to be executed is the E3 mode, the clock generator determines the E3. And a clock control unit for selecting a clock signal for outputting the signal to the LIU and controlling the LIU to drive each mode to be executed. The method of claim 6, wherein the LIU, Integrated network interface device, a commercial chip that supports both DS3 and E3. The method of claim 6, wherein the clock control unit, Integrated network interface device implemented in FPGA. The method of claim 6, wherein the clock control unit, Integrated network interface device for controlling the operation mode of the LIU by outputting a control signal for selecting the DS3 or E3 to the LIU. The method of claim 6, wherein the clock generator, A first clock generator for generating a clock signal for DS3; An integrated network interface device comprising a second clock generator for generating a clock signal for E3. The method of claim 10, And the first clock generator is an IC PLL for generating a clock signal having a frequency of 44.736 MHz, and the second clock generator is an IC PLL for generating a clock signal having a frequency of 34.368 MHz. The method of claim 6, wherein the clock control unit, And a reference clock signal for generating a clock signal to the clock generator. A transmission system comprising an integrated network interface device operating in a plurality of modes by providing different clock signals to a LIU, A first step of selecting an operation mode of the network interface device; Selecting a clock signal corresponding to the selected operation mode; And providing a selected clock signal to the LIU, and controlling the LIU to drive the selected operation mode.

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