JP2000013219A - Programmable pll clock generator - Google Patents

Abstract

PROBLEM TO BE SOLVED: To eliminate variation of jitters without dependency on the frequency of an output clock and to hold a small value by providing variable frequency dividers for plural inputs to a phase comparator and further providing a variable frequency divider behind VCO. SOLUTION: The phase comparator 102 uses a signal having its frequency divided to Fin/D as a reference signal and compares the phase with the other input signal to send the phase relation in the form of a digital signal to a charge pump circuit 103. Then the signal is sent to the VCO 107 through a low-pass filter 104. The signal of the VCO 107 is divided by a variable frequency divider 106 and outputted as a clock signal of frequency Fout. Further, this signal is further divided by a variable frequency divider 105 and fed back to the phase comparator 102. Therefore, the operation point of the VCO 107 has no large variation and is held in a high-frequency range.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a clock generator employing a PLL system.

[0002]

2. Description of the Related Art In a conventional programmable PLL clock generator, one or more variable frequency dividers capable of changing a frequency dividing ratio are provided inside or outside a closed loop in order to obtain a plurality of output frequencies. Therefore, the frequency of the output clock is determined by the frequency of the input reference clock signal and the frequency division ratio of the variable frequency divider. At this time, the VCO behaves so as to change the operating frequency according to the frequency division ratio of the variable frequency divider. Therefore, changing the frequency of the output clock
Was to change the operating frequency of the VCO.

[0003]

However, when examining the relationship between the jitter of the output clock and the operating frequency of the VCO, it has been found that the lower the operating frequency of the VCO, the greater the jitter, and the higher the operating frequency of the VCO, the smaller the jitter. In other words, the jitter characteristic differs depending on the frequency value of the output clock, and the lower the frequency of the output clock, the greater the jitter.

[0004]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention provides a plurality of variable frequency dividers in a closed loop so that the operating frequency of a VCO does not greatly change even if the frequency of an output clock changes. And a variable frequency divider is configured so that the operating frequency of the VCO does not change significantly even when the frequency of the output clock changes.

[0005]

Embodiments of the present invention will be described below with reference to the drawings.

(Embodiment 1) FIG. 1 is a diagram showing an embodiment of a programmable PLL clock generator according to the first aspect of the present invention. As shown in FIG. 1, a clock signal having a fixed frequency Fin is input to the variable frequency divider 101 and frequency-divided, and then enters the phase comparator 102. Then, the phase comparator 102 compares the phase of the signal divided by Fin / D with the other input signal and sets the phase relationship to a digital signal.
Send a signal to 03. The charge pump circuit 103 converts the digital signal into a charge / discharge current and outputs it. Thereafter, the signal is sent to the VCO 107 through the low-pass filter 104. The VCO 107 is a voltage / frequency conversion circuit having the characteristics shown in FIG. 2, and the frequency of the output signal is determined by the input voltage of the VCO. The signal of the VCO 107 is frequency-divided by the variable frequency divider 106 and output as a clock signal having a frequency of Fout. The signal is further divided by the variable frequency divider 105 and fed back to the phase comparator 102. Here, the frequency division ratio of the variable frequency divider 101, the variable frequency divider 105, and the variable frequency divider 106 is determined by the frequency selection signal S
The value of “in” is determined by the decoder circuit 108.

[0007]

[Table 1]

Assuming that Fout can be selected from five types shown in Table 1, the D value of the variable frequency divider 101, the N value of the variable frequency divider 105, and the M value of the variable frequency divider 106 are shown in Table 1. Value. At this time, Fvco, Fout, N, D,
The relationship of M is expressed by the following equation.

[0009]

(Equation 1)

Conventionally, as shown in FIG.
Only two variable dividers were used for one input. Alternatively, two variable frequency dividers are used for one input of the phase comparator as shown in the patent of the publication number H09191247. In the conventional example of FIG.
D value of the variable frequency divider 201 with respect to ut, the variable frequency divider 20
The N value of 5 is as shown in Table 2. FIG. 4 shows the relationship between Fvco and the input voltage Vcp of the VCO. The relationship between Fvco, Fout, N, and D at this time is as follows.

[0011]

(Equation 2)

[0012]

[Table 2]

At present, in a circuit of this type, the higher the operating frequency of the VCO, the smaller the jitter of the output signal.
The lower, the higher the jitter of the output signal. on the other hand,
For a user using this clock generator, it is desirable that the jitter is small and constant regardless of the output frequency regardless of the output frequency selected. However, in the conventional circuit, as is apparent from Table 2, Fou
t is proportional to Fvco, and the operating points are widely dispersed also in FIG. That is, when Fout is low, the jitter is large, and when it is high, the jitter is small.

The present invention has a circuit configuration as shown in FIG. 1 in order to reduce this effect. The configuration of FIG. 1 is characterized by providing a variable frequency divider for each of two inputs of the phase comparator 102 and the VCO 10
7 is further provided with a variable frequency divider. The two variable dividers used for the two inputs of the phase comparator 102 work to match the frequency in the phase comparator, and the variable divider at the next stage of the VCO does not greatly change Fvco. Also, it works to set the output clock to the target frequency Fout. Therefore, as shown in FIG. 2, the operating point of the VCO does not greatly change and is kept in a high frequency region. Therefore, the jitter can be kept at a small value without changing even when the Fout changes.

[0015]

As described above, according to the present invention, by providing a plurality of variable frequency dividers inside and outside the closed loop, the operating point of the VCO does not greatly change depending on the value of the output frequency. Therefore, the jitter can be kept at a small value without changing the jitter without depending on the frequency of the output clock.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing one embodiment of the present invention.

FIG. 2 is a characteristic diagram of a VCO in FIG. 1;

FIG. 3 is a configuration diagram showing a conventional example.

FIG. 4 is a characteristic diagram of the VCO in FIG. 3;

[Explanation of symbols]

 Reference Signs List 101 variable frequency divider 102 phase comparator 103 charge pump circuit 104 low-pass filter 105 variable frequency divider 106 variable frequency divider 107 VCO 108 decoder 201 variable frequency divider 202 phase comparator 203 charge pump circuit 204 low-pass filter 205 Variable frequency divider 206 Fixed frequency divider 207 VCO 208 Decoder

Claims (1)

[Claims] 1. A phase comparator for comparing a phase of a reference clock signal input from the outside with a clock signal generated internally, and a charge for generating a reference current for charging / discharging using an output of the phase comparator. A pump circuit; a VCO that operates by receiving a signal obtained by passing a reference current output from the charge pump circuit through a low-pass filter;
A programmable PLL clock generator that has a frequency divider that divides the signal of O and feeds it back to the phase comparator and generates a clock of an arbitrary frequency that constitutes a closed loop circuit. A programmable PLL clock generator characterized in that the operating frequency of the VCO is substantially constant.