KR100784759B1 - Plasma Display Panel - Google Patents

Abstract

The present invention relates to a plasma display panel, and further includes a dielectric layer having a relatively low dielectric constant between the electrode and the substrate to reduce the overall parasitic capacitance value, thereby improving driving efficiency.

The plasma display panel of the present invention has a dielectric constant different from that of a substrate, a first dielectric layer formed on the substrate, an electrode formed on the first dielectric layer, and the first dielectric layer, and covering the electrode. It is preferred to include a second dielectric layer formed over the first dielectric layer.

In addition, another plasma display panel of the present invention includes a substrate, a first dielectric layer formed on the substrate, a plurality of electrodes formed on the first dielectric layer, and the plurality of electrodes on the first dielectric layer. It is preferred to include a second dielectric layer formed between the electrodes and a third dielectric layer formed to cover the electrode and the second dielectric layer.

Description

Plasma Display Panel

1 is a diagram for explaining a conventional plasma display panel.

2 is a view for explaining a problem of the conventional plasma display panel.

3A to 3B are views for explaining a first embodiment of the plasma display panel structure of the present invention.

4 is a view for explaining the structure of the back substrate of the plasma display panel of the present invention in more detail.

FIG. 5 is a diagram for explaining parasitic capacitance in the plasma display panel of the present invention; FIG.

6A to 6B are views for explaining still another example of the first embodiment of the structure of the plasma display panel of the present invention;

Fig. 7 is a view for explaining a second embodiment of the structure of the plasma display panel of the present invention.

8A to 8C are views for explaining the structure of the front substrate of the plasma display panel of the present invention in more detail.

Fig. 9 is a view for explaining a third embodiment of the structure of the plasma display panel of the present invention.

10 is a view for explaining still another example of the third embodiment of the structure of the plasma display panel of the present invention;

11A to 11C are views for explaining a fourth embodiment of the structure of a plasma display panel of the present invention.

<Explanation of symbols for main parts of the drawings>

300: front panel 301: front substrate

302 scan electrode 303 sustain electrode

304: upper dielectric layer 305: protective layer

310: rear panel 311: rear substrate

312: partition 313: address electrode

314 phosphor layer 315 first lower dielectric layer

316: second lower dielectric layer

The present invention relates to a plasma display panel.

In general, a phosphor layer is formed in a discharge cell partitioned by a partition, and a plurality of electrodes is formed in a plasma display panel.

The driving voltage is supplied to the discharge cell through this electrode.

Then, the discharge is generated by the driving voltage supplied in the discharge cell. In this case, when discharged by a driving voltage in the discharge cell, the discharge gas filled in the discharge cell generates vacuum ultraviolet rays, and the vacuum ultraviolet light emits the phosphor formed in the discharge cell to emit visible light. Generates.

The visible light displays an image on the screen of the plasma display panel.

1 is a view for explaining a conventional plasma display panel.

Referring to FIG. 1, a conventional plasma display panel includes a substrate 100, electrodes 110 and 120 formed on the substrate 100, and dielectric layers formed on the substrate 100 on which the electrodes 110 and 120 are formed. 130.

Here, the dielectric layer 130 protects the electrodes 110 and 120 from damage such as dielectric breakdown, and serves to stabilize the discharge.

If the dielectric layer 130 has excessively low permittivity, the discharge becomes unstable, and the dielectric layers 130 may not be sufficiently secured to protect the electrodes 110 and 120.

On the other hand, in the case where the dielectric constant of the dielectric layer 130 is excessively high, the discharge is sufficiently stabilized and the electrodes 110 and 120 can be sufficiently secured, but the capacitance value between the electrodes 110 and 120 is large. This increase causes a problem that the driving efficiency decreases. This will be described with reference to FIG. 2.

2 is a view for explaining the problem of the conventional plasma display panel.

Referring to FIG. 2, parasitic capacitance is generated due to a voltage difference between the electrodes 110 and 120 during driving. This parasitic capacitance can be determined in general by the sum of C1 and C2, as shown here in FIG.

Here, the C1 parasitic capacitance greatly depends on the dielectric constant of the substrate 100, and the C2 parasitic capacitance greatly depends on the dielectric constant of the dielectric layer 130.

Therefore, when the dielectric constant of the dielectric layer 130 is excessively high, the C2 parasitic capacitance value is excessively increased or decreased, resulting in a problem that the overall driving efficiency is lowered.

On the other hand, since the substrate 100 is generally made of a glass material, the dielectric constant of the substrate 100 is relatively very high.

Therefore, when driving, the C1 parasitic capacitance value is greatly increased, resulting in a problem that the overall driving efficiency is further lowered.

SUMMARY OF THE INVENTION In order to solve the above problems, an object of the present invention is to provide a plasma display panel in which the total capacitance value is reduced by improving the structure of the dielectric layer.

Plasma display panel of the present invention for achieving the above object is different from the dielectric constant of the substrate, the first dielectric layer formed on the substrate, the electrode formed on the first dielectric layer and the first dielectric layer, It is preferred to include a second dielectric layer formed over the first dielectric layer to cover the electrode.

In addition, the first dielectric layer is characterized by a lower dielectric constant than the second dielectric layer.

The dielectric constant of the first dielectric layer is characterized by being 0.01 to 0.5 times the dielectric constant of the second dielectric layer.

In addition, the thickness of the first dielectric layer is characterized in that less than 0.1 times 10 times the thickness of the electrode.

Also, the thickness of the first dielectric layer is approximately equal to the thickness of the electrode.

In addition, the thickness of the second dielectric layer is characterized in that more than 2 times 10 times the thickness of the electrode.

In addition, the first dielectric layer is characterized by having a protrusion projecting in the direction of the second dielectric layer between the electrodes.

In addition, the protrusion may be protruded at the same height as the electrode or protruded higher.

Another plasma display panel of the present invention for achieving the above object is a substrate, a first dielectric layer formed on the substrate, a plurality of electrodes formed on the first dielectric layer, and the top of the first dielectric layer Preferably include a second dielectric layer formed between the plurality of electrodes and a third dielectric layer formed to cover the electrode and the second dielectric layer.

In addition, the third dielectric layer is characterized by a higher dielectric constant than the first dielectric layer and the second dielectric layer.

In addition, the dielectric constant of the third dielectric layer is characterized by being at least two times and at most 100 times the dielectric constant of the first dielectric layer or the second dielectric layer.

In addition, the thickness of the first dielectric layer is characterized in that less than 0.1 times 10 times the thickness of the electrode.

Also, the thickness of the first dielectric layer is approximately equal to the thickness of the electrode.

Also, the thickness of the second dielectric layer is approximately equal to or greater than the thickness of the electrode.

In addition, the thickness of the third dielectric layer is characterized in that more than 2 times 10 times the thickness of the electrode.

Hereinafter, a plasma display panel of the present invention will be described in detail with reference to the accompanying drawings.

Hereinafter, a plasma display panel of the present invention will be described in detail with reference to the accompanying drawings.

3A to 3B are views for explaining a first embodiment of the structure of the plasma display panel of the present invention.

First, referring to FIG. 3A, a first embodiment of a plasma display panel of the present invention includes a front substrate 301 on which electrodes, preferably scan electrodes 302 and Y and sustain electrodes 303 and Z, are formed. A back substrate including the front panel 300 and an electrode intersecting the aforementioned scan electrodes 302 and Y and the sustain electrodes 303 and Z, preferably address electrodes 313a, 313b, 313c, and X. The rear panel 310 including the 311 is bonded to each other.

Here, the electrodes formed on the front substrate 301, preferably the scan electrodes 302 and Y and the sustain electrodes 303 and Z, generate a discharge in a discharge space, that is, a discharge cell, and at the same time Maintain the discharge.

The dielectric layer, preferably on the upper surface of the front substrate 301 on which the scan electrodes 302 and Y and the sustain electrodes 303 and Z are formed, covers the scan electrodes 302 and Y and the sustain electrodes 303 and Z. Upper dielectric layer 304 is formed.

This upper dielectric layer 304 limits the discharge current of the scan electrodes 302 and Y and the sustain electrodes 303 and Z and insulates the scan electrodes 302 and Y from the sustain electrodes 303 and Z.

A protective layer 305 is formed on the top surface of the upper dielectric layer 304 to facilitate a discharge condition. The protective layer 305 is formed through a method of depositing a material such as magnesium oxide (MgO) over the upper dielectric layer 304.

Meanwhile, a first lower dielectric layer 316 is formed on the back substrate 311. The first lower dielectric layer 316 reduces a capacitance value between the address electrodes 313a, 313b, 313c, and X when driven. This first lower dielectric layer 316 will be described in more detail later.

The address electrodes 313a, 313b, 313c, and X are electrodes for supplying data pulses to the discharge cells.

The second lower dielectric layer 315 is formed on the rear substrate 311 on which the address electrodes 313a, 313b, 313c, and X are formed to cover the address electrodes 313a, 313b, 313c, and X.

This second lower dielectric layer 315 insulates the address electrodes 313a, 313b, 313c, and X.

A discharge space, that is, a partition 312 such as a stripe type or a well type for partitioning the discharge cell is formed on the second lower dielectric layer 315. Accordingly, discharge cells such as red (R), green (G), and blue (B) are formed between the front substrate 301 and the rear substrate 311.

Here, a predetermined discharge gas is filled in the discharge cell partitioned by the partition 312.

In addition, a phosphor layer 314 is formed in the discharge cell partitioned by the partition 312 to emit visible light for image display during discharge. For example, red (R), green (G), and blue (B) phosphor layers may be formed.

In the plasma display panel of the present invention described above, when the driving voltage is supplied to at least one of the scan electrodes 302 and Y, the sustain electrodes 303 and Z, and the address electrodes 313a, 313b, 313c, and X, the partition wall The discharge occurs in the discharge cell partitioned by 312.

Then, vacuum ultraviolet rays are generated in the discharge gas filled in the discharge cells, and the vacuum ultraviolet rays are applied to the phosphor layer 314 formed in the discharge cells. Then, predetermined visible light is generated in the phosphor layer 314, and the visible light is emitted to the outside through the front substrate 301 on which the upper dielectric layer 304 is formed, and thus the front substrate 301. A predetermined image is displayed on the outer surface of the.

At least one or more of the electrodes described with reference to FIG. 3A, that is, the scan electrodes 302 and Y, the sustain electrodes 303 and Z, and the address electrodes 313a, 313b, 313c, and X include a first electrode and a second electrode. It is preferable to make. This will be described with reference to FIG. 3B.

Referring to FIG. 3B, in the plasma display panel of the present invention, the scan electrodes 302 and Y and the sustain electrodes 303 and Z are formed of a plurality of layers, respectively. More preferably, the scan electrodes 302 and Y and the sustain electrodes 303 and Z include the first electrodes 302a and 303a and the second electrodes 302b and 303b, respectively.

3B illustrates only the case where the scan electrodes 302 and Y and the sustain electrodes 303 and Z include the first electrodes 302a and 303a and the second electrodes 302b and 303b. 313a, 313b, 313c, and X may also comprise a 1st electrode and a 2nd electrode.

Here, in consideration of the light transmittance and the electrical conductivity, the first electrode 302a of the scan electrodes 302 and Y and the sustain electrodes 303 and Z in order to emit light generated in the discharge cell to the outside and to secure driving efficiency. , 303a is preferably made of a substantially transparent material, and the second electrodes 302b, 303b are preferably made of an electrically conductive opaque material.

Here, more preferably, the first electrodes 302a and 303a of the scan electrodes 302 and Y and the sustain electrodes 303 and Z are made of a transparent material including indium tin oxide (ITO). The second electrodes 302b and 303b are made of an electrically conductive opaque material containing silver (Ag).

As such, the reason why the scan electrodes 302 and Y and the first electrodes 302a and 303a of the sustain electrodes 303 and Z are formed to be substantially transparent is that visible light generated in the discharge cells is external to the plasma display panel. This is to ensure that when released to the effective release.

In addition, the reason why the second electrodes 302b and 303b of the scan electrodes 302 and Y and the sustain electrodes 303 and Z are formed of an electrically conductive opaque metal material is the scan electrodes 302 and Y and the sustain electrode. When (303, Z) includes only the substantially transparent first electrodes 302a and 303a, the driving efficiency can be reduced because the electrical conductivity of the first electrodes 302a and 303a is relatively low, so that To compensate for the low electrical conductivity of the first electrodes 302a, 303a which may cause a decrease.

3A to 3B, only one example of the plasma display panel of the present invention is shown and described, and the present invention is not limited to the plasma display panel having the structure shown in FIGS. 3A to 3B. For example, although only red (R), green (G), and blue (B) phosphor layers 314 are formed here in FIGS. 3A to 3B, red (R) and green (G) are different. In addition to the blue (B) phosphor layer, a yellow (Yellow, Y) phosphor layer may be further formed.

The main features of the plasma display panel of the present invention will be more apparent from the following description.

Next, FIG. 4 is a view for explaining the structure of the rear substrate of the plasma display panel of the present invention in more detail.

Referring to FIG. 4, the plasma display panel according to the present invention includes a first lower dielectric layer 316 formed on a substrate, that is, an electrode formed on an upper portion of the first lower dielectric layer 316, that is, an address. It can be seen that the second lower dielectric layer 315 formed over the first lower dielectric layer 316 is sequentially formed to cover the electrodes 313a, 313b, and 313c and the address electrodes 313a, 313b, and 313c. .

Here, the thickness t2 of the first lower dielectric layer 316 is preferably 0.1 times or more and 10 times or less than the thickness t1 of the electrodes, that is, the address electrodes 313a, 313b, and 313c. The reason why the thickness t2 of the first lower dielectric layer 316 is 0.1 times or more and 10 times or less than the thickness t1 of the electrodes, that is, the address electrodes 313a, 313b, and 313c is because of the first lower dielectric layer 316. ), When the thickness t2 is excessively smaller than 0.1 times the thickness t1 of the address electrodes 313a, 313b, and 313c, the thickness t2 of the first lower dielectric layer 316 becomes excessively thin. The likelihood of an increase in the generation of parasitic capacitance in driving increases, while the thickness t2 of the first lower dielectric layer 316 exceeds 10 times the thickness t1 of the address electrodes 313a, 313b, and 313c, and is excessive. In this case, the thickness t2 of the first lower dielectric layer 316 becomes excessively thick, thereby increasing the overall thickness of the plasma display panel of the present invention and increasing the possibility of excessive increase in the total capacitance value. .

More preferably, the thickness t2 of the first lower dielectric layer 316 is approximately equal to the thickness t1 of the address electrodes 313a, 313b, and 313c.

Here, the permittivity of the first lower dielectric layer 316 has a relatively small value. More preferably, the dielectric constant of the first lower dielectric layer 316 is lower than that of the second lower dielectric layer 315.

More preferably, the dielectric constant of the first lower dielectric layer 316 has a value of 0.01 times or more and 0.5 times or less of the dielectric constant of the second lower dielectric layer 315.

As such, the reason for setting the dielectric constant of the first lower dielectric layer 316 to 0.01 times or more and 0.5 times or less of the dielectric constant of the second lower dielectric layer 315 is that the dielectric constant of the first lower dielectric layer 316 is set to the second. If the dielectric constant of the lower dielectric layer 315 is excessively small, less than 0.01 times, the dielectric constant of the first lower dielectric layer 316 is excessively low, resulting in damage such as dielectric breakdown of the address electrodes 313a, 313b, and 313c. If the dielectric constant of the first lower dielectric layer 316 increases excessively by more than 0.5 times the dielectric constant of the second lower dielectric layer 315, the overall parasitic capacitance value increases excessively to drive. This is because the likelihood of efficiency deterioration increases.

In addition, the dielectric constant of the first lower dielectric layer 316 is lower than that of the rear substrate 311.

In addition, the thickness of the second lower dielectric layer 315 is preferably two times or more and ten times or less the thickness t1 of the electrodes, that is, the address electrodes 313a, 313b, and 313c.

As such, the reason for setting the thickness of the second lower dielectric layer 315 to be two or more and ten or less times the thickness t1 of the electrodes, that is, the address electrodes 313a, 313b, and 313c is because of the second lower dielectric ( 315) the second lower dielectric layer covering the address electrodes 313a 313b, 313c when the thickness of the layer becomes excessively small, less than twice the thickness t1 of the electrodes, that is, the address electrodes 313a, 313b, 313c. The possibility that the 315 is excessively thin so that the address electrodes 313a, 313b, and 313c cannot be sufficiently protected from damage such as dielectric breakdown increases, whereas the thickness of the second lower dielectric 315 layer is increased by the electrode, In other words, when the thickness increases excessively by more than 10 times the thickness t1 of the address electrodes 313a, 313b, and 313c, the thickness of the entire plasma display panel increases and the overall parasitic capacitance value increases excessively, thereby lowering the driving efficiency. Because the likelihood of becoming increases.

Here, in consideration of protection from breakdown of the address electrodes 313a, 313b, and 313c and securing of driving efficiency, the thickness of the second lower dielectric 315 layer is the electrode, that is, the address electrodes 313a, 313b, and 313c. It is more preferable that they are 2 times or more and 5 times or less of the thickness t1.

The parasitic capacitance generated when the plasma display panel is driven is described with reference to FIG. 5 as follows.

5 is a diagram for describing parasitic capacitance in the plasma display panel of the present invention.

Referring to FIG. 5, parasitic capacitance is generated between voltages of the address electrodes 313a, 313b, and 313c when the plasma display panel is driven. This parasitic capacitance can be determined as the sum of C1 and C2 in general, as shown here in FIG. 5.

Here, the C1 parasitic capacitance greatly depends on the dielectric constant of the first lower dielectric layer 316, and the C2 parasitic capacitance greatly depends on the dielectric constant of the second lower dielectric layer 315.

Here, because the dielectric constant of the first lower dielectric layer 316 is lower than the second lower dielectric layer 315, the C1 parasitic capacitance has a smaller value than the C2 parasitic capacitance.

Accordingly, the driving efficiency is improved because the overall parasitic capacitance of the plasma display panel of the present invention has a relatively small value as compared with the conventional FIG. 2 described above.

In addition, since the second lower dielectric layer 315 has a sufficiently large dielectric constant than the first lower dielectric layer 316, the second lower dielectric layer 315 protects the address electrodes 313a, 313b, and 313c from damage such as dielectric breakdown and stabilizes discharge.

6A to 6B are views for explaining still another example of the first embodiment of the structure of the plasma display panel of the present invention.

First, referring to FIG. 6A, the first lower dielectric layer 316 further includes protrusions 600 and 610 that protrude in the direction of the second lower dielectric layer 315 between the address electrodes 313a, 313b, and 313c.

The protrusions 600 and 610 may protrude to the same height as the address electrodes 313a, 313b, and 313c.

As such, when the first lower dielectric layer 316 includes protrusions 600 and 610 protruding between the address electrodes 313a, 313b, and 313c, the C2 parasitic capacitance value in FIG. It can be reduced to such a small enough that the driving efficiency can be further improved.

In addition, in the structure of FIG. 6A, since the second lower dielectric layer 315 formed to cover the address electrodes 313a, 313b, and 313c has a sufficiently large dielectric constant, the address electrodes 313a, 313b, and 313c are destroyed. It protects against back damage and stabilizes discharge.

Next, referring to FIG. 6B, unlike FIG. 6A, the protrusions 620 and 630 protrude to a higher height than the address electrodes 313a, 313b, and 313c. As such, the heights of the protrusions 600 and 610 may be variously adjusted.

In the above description, only the lower dielectric layer formed on the rear substrate includes the first lower dielectric layer and the second lower dielectric layer. However, the upper dielectric layer formed on the front substrate is different from the first upper dielectric layer and It is also possible to include a second upper dielectric layer. This is as follows.

7 is a view for explaining a second embodiment of the structure of the plasma display panel of the present invention.

Referring to FIG. 7, unlike the second embodiment of the plasma display panel structure of the present invention as shown in FIG. 3A, the first upper dielectric layer 306 and the second upper dielectric layer 304 are included. In FIG. 7, the description of the above description will be omitted.

Looking at the structure of the front substrate of the plasma display panel of the present invention as shown in FIG. 7 as follows.

8A to 8C are views for explaining the structure of the front substrate of the plasma display panel of the present invention in more detail.

First, referring to FIG. 8A, the plasma display panel of the present invention includes a first upper dielectric layer 306 formed on a substrate, that is, an electrode formed on the first upper dielectric layer 306. A second upper portion formed over the first upper dielectric layer 306 to cover the scan electrodes 302 and Y and the sustain electrodes 303 and Z and the scan electrodes 302 and Y and the sustain electrodes 303 and Z. It can be seen that the dielectric layer 304 is formed in sequence.

Herein, as illustrated in FIG. 3A, the scan electrodes 302 and Y and the sustain electrodes 303 and Z respectively include the first electrodes 302a and 303a and the second electrodes 302b and 303b. do.

Here, the thickness t1 of the first upper dielectric layer 306 is preferably 0.1 to 10 times the thickness of the electrodes, that is, the scan electrodes 302 and Y or the sustain electrodes 303 and Z. The thickness t1 of the first upper dielectric layer 306 is 0.1 to 10 times the thickness of the electrodes, that is, the scan electrodes 302 and Y or the sustain electrodes 303 and Z. When the thickness t1 of the layer 306 is less than 0.1 times the thickness of the scan electrodes 302 and Y or the sustain electrodes 303 and Z, the thickness t1 of the first upper dielectric layer 306 is excessive. The thinning increases the likelihood of dielectric breakdown of the scan electrodes 302 and Y or the sustain electrodes 303 and Z when driven, while the thickness t1 of the first upper dielectric layer 306 is increased by the scan electrode 302. This is because the thickness t1 of the first upper dielectric layer 306 becomes excessively thick when the thickness of the first upper dielectric layer 306 is excessively increased when Y) or the sustain electrodes 303 and Z are increased. .

In addition, the thickness t1 of the first upper dielectric layer 306 is preferably about the same as the thickness of the scan electrodes 302 and Y or the sustain electrodes 303 and Z. More preferably, the thickness t1 of the first upper dielectric layer 306 is approximately equal to the thickness of the first electrodes 302a and 303a of the scan electrodes 302 and Y or the sustain electrodes 303 and Z.

Here, the permittivity of the first upper dielectric layer 306 has a relatively small value. More preferably, the dielectric constant of the first upper dielectric layer 306 is lower than that of the second upper dielectric layer 304.

More preferably, the dielectric constant of the first upper dielectric layer 306 has a value of 0.01 times or more and 0.5 times or less of the dielectric constant of the second upper dielectric layer 304.

As such, the reason for setting the dielectric constant of the first upper dielectric layer 306 to 0.01 times or more and 0.5 times or less of the dielectric constant of the second upper dielectric layer 304 is that the dielectric constant of the first upper dielectric layer 306 is equal to the second. When the dielectric constant of the upper dielectric layer 304 becomes excessively small, less than 0.01 times the dielectric constant of the upper dielectric layer 304, the dielectric constant of the first upper dielectric layer 306 is excessively low to insulate the scan electrodes 302 and Y or the sustain electrodes 303 and Z. The likelihood of damage such as destruction increases, while the overall parasitic capacitance value is increased when the permittivity of the first upper dielectric layer 306 excessively increases by more than 0.5 times the permittivity of the second upper dielectric layer 304. This is because the possibility of excessively increasing and lowering the driving efficiency increases.

In addition, the dielectric constant of this first upper dielectric layer 306 is lower than that of the front substrate 301.

Further, the thickness of the second upper dielectric 304 layer is preferably at least two times and at most ten times the thickness of the electrodes, that is, the scan electrodes 302 and Y or the sustain electrodes 303 and Z. This can be done in the case where the scan electrodes 302 and Y or the sustain electrodes 303 and Z are made of one layer as in FIG. 3A or a plurality of layers as in FIG. 3B.

As such, the reason for setting the thickness of the second upper dielectric 304 layer to be two or more and ten or less times the thickness of the electrodes, that is, the scan electrodes 302 and Y or the sustain electrodes 303 and Z, is because If the thickness of the dielectric 304 layer becomes excessively small, less than twice the thickness of the electrode, i.e., the scan electrode 302, Y or the sustain electrode 303, Z, the scan electrode 302, Y or the sustain electrode ( There is a possibility that the second upper dielectric layer 304 covering 303, Z becomes excessively thin so that the scan electrode 302, Y or the sustain electrode 303, Z cannot be sufficiently protected from damage such as dielectric breakdown. On the other hand, if the thickness of the second upper dielectric 304 layer excessively increases by more than 10 times the thickness of the electrode, i.e., the scan electrode 302, Y or the sustain electrode 303, Z, the entire plasma Increasing the thickness of the display panel and excessively increasing the overall parasitic capacitance value The it is because the possibility of increasing the driving efficiency decreases.

Accordingly, as described in detail with reference to FIG. 5, the parasitic capacitance generated by the voltage difference between the scan electrodes 302 and Y and the sustain electrodes 303 and Z during the driving of the plasma display panel according to the present invention. The value is smaller than before. Therefore, the driving efficiency is improved.

In addition, since the second upper dielectric layer 304 has a sufficiently large permittivity compared to the first upper dielectric layer 306, the scan electrodes 302 and Y or the sustain electrodes 303 and Z are protected from damage such as dielectric breakdown. And stabilizes discharge.

Next, referring to FIG. 8B, the first upper dielectric layer 306 further includes a protrusion 800 protruding in the direction of the second upper dielectric layer 304 between the scan electrodes 302 and Y and the sustain electrodes 303 and Z. Equipped.

The protrusion 800 may protrude to the same height as the scan electrodes 302 and Y and the sustain electrodes 303 and Z. More preferably, the protrusion 800 may protrude by the sum of the heights of the first electrodes 302a and 303a and the second electrodes 302b and 303b of the scan electrodes 302 and Y and the sustain electrodes 303 and Z. have.

Next, referring to FIG. 8C, unlike FIG. 8B, the protrusion 800 protrudes to the same height as the first electrodes 302a and 303a of the scan electrodes 302 and Y and the sustain electrodes 303 and Z.

Although not shown, the protrusion 800 is higher than the sum of the heights of the first electrodes 302a and 303a and the second electrodes 302b and 303b of the scan electrodes 302 and Y and the sustain electrodes 303 and Z. It may protrude.

As such, the height of the protrusion 800 may be variously adjusted.

Next, a third embodiment of the structure of the plasma display panel of the present invention will be described with reference to FIGS. 9 to 10.

9 is a view for explaining a third embodiment of the structure of the plasma display panel of the present invention.

10 is a view for explaining another example of the third embodiment of the structure of the plasma display panel of the present invention.

First, referring to FIG. 9, the plasma display panel of the present invention includes a substrate 900, a first dielectric layer 910 formed on the substrate 900, and a plurality of electrodes formed on the first dielectric layer 910. 940 and a second dielectric layer 920 formed between the plurality of electrodes 940 over the first dielectric layer 910, and covering the electrode 940 and the second dielectric layer 920. A third dielectric layer 930 to be formed.

Here, in FIG. 9, the substrate 900 may be the front substrate 301 or the rear substrate 311 as shown in FIG. 3A.

In addition, the electrode 940 may be the address electrodes 313a, 313b, and 313c as shown in FIG. 3A, or may be the scan electrodes 302 and Y or the sustain electrodes 303 and Z as shown in FIG. 7.

Here, the thickness of the first dielectric layer 910 is preferably 0.1 times or more and 10 times or less of the thickness of the electrode 940. More preferably, the thickness of the first dielectric layer 910 is approximately equal to the thickness of the electrode 940.

In addition, the thickness of the second dielectric layer 920 may be approximately equal to the thickness of the electrode 940.

Here, it is preferable that the third dielectric layer 930 has a higher dielectric constant than the first dielectric layer 910 and the second dielectric layer 920. This third dielectric layer 930 has a dielectric constant large enough to protect the electrode 940.

More preferably, the dielectric constant of the third dielectric layer 930 has a value of at least two times and at most 100 times the dielectric constant of the first dielectric layer 910 or the second dielectric layer 920.

As such, the reason why the dielectric constant of the third dielectric layer 930 is set to two or more times and 100 times or less of the dielectric constant of the first dielectric layer 910 or the second dielectric layer 920 is the third dielectric layer 930. The dielectric constant of the third dielectric layer 930 is excessively low when the dielectric constant of the dielectric layer is excessively smaller than twice the dielectric constant of the first dielectric layer 910 or the second dielectric layer 920 to insulate the electrode 940. The likelihood of damage such as destruction increases, while the dielectric constant of the third dielectric layer 930 may be excessively increased by more than 100 times the dielectric constant of the first dielectric layer 910 or the second dielectric layer 920. In this case, the overall parasitic capacitance value is excessively increased, which increases the possibility of lowering the driving efficiency.

In addition, the first dielectric layer 910 and the second dielectric layer 920 may be made of the same material, or may be made of different materials.

Here, when the first dielectric layer 910 and the second dielectric layer 920 are made of different materials, it is preferable that the second dielectric layer 920 is made of a material having a higher dielectric constant than the first dielectric layer 910. Do. That is, the dielectric constant of the second dielectric layer 920 is higher than that of the first dielectric layer 910.

In addition, the thickness of the third dielectric layer 930 is preferably two times or more and ten times or less the thickness of the electrode 940.

Here, in the structure as shown in FIG. 9, the C1 parasitic capacitance value and the C2 parasitic capacitance value in FIG. 5 may be sufficiently reduced to further improve driving efficiency.

In addition, in such a structure as shown in FIG. 9, since the third dielectric layer 930 formed to cover the electrode 940 and the second dielectric layer 920 has a sufficiently large dielectric constant, damage to the electrode 940 such as breakdown or the like may occur. Protects against and stabilizes discharge.

Next, referring to FIG. 10, unlike FIG. 9, the second dielectric layer 920 has a higher height than the electrode 940. As such, the height of the second dielectric layer 920 may be variously adjusted.

11A to 11C are diagrams for describing a fourth embodiment of the structure of the plasma display panel of the present invention.

First, referring to FIG. 11A, as shown in FIG. 4, the plasma display panel of the present invention is disposed on the first lower dielectric layer 316 and the first lower dielectric layer 316 formed on the substrate, that is, the rear substrate 311. Electrodes formed, that is, address electrodes 313a, 313b, and 313c, and second lower dielectric layers 315 formed over the first lower dielectric layer 316 to cover the address electrodes 313a, 313b, and 313c. In this case, the third lower dielectric layer 1100 may be further formed to cover the second lower dielectric layer 315.

The dielectric constant of the third lower dielectric layer 1100 is preferably higher than that of the second lower dielectric layer 315.

As such, the lower dielectric layer may be formed in various structures.

Next, referring to FIG. 11B, as shown in FIG. 8A, the plasma display panel of the present invention is formed on the substrate, that is, the first upper dielectric layer 306 and the first upper dielectric layer 306 formed on the front substrate 301. The first upper dielectric layer 306 to cover the electrodes formed on the electrodes, that is, the scan electrodes 302 and Y and the sustain electrodes 303 and Z, and the scan electrodes 302 and Y and the sustain electrodes 303 and Z. In the case where the second upper dielectric layer 304 is formed in turn, the third upper dielectric layer 1110 may be further formed to cover the second upper dielectric layer 304.

In this case, as illustrated in FIG. 3A, the scan electrodes 302 and Y and the sustain electrodes 303 and Z respectively include the first electrodes 302a and 303a and the second electrodes 302b and 303b.

The dielectric constant of the third upper dielectric layer 1110 is preferably higher than that of the second upper dielectric layer 304.

As such, the upper dielectric layer may be formed in various structures.

Next, referring to FIG. 11C, as shown in FIG. 9, the plasma display panel according to the present invention includes a substrate 900, a first dielectric layer 910 formed on the substrate 900, and an upper portion of the first dielectric layer 910. A plurality of electrodes 940 formed on the second dielectric layer 920 formed between the plurality of electrodes 940 over the first dielectric layer 910, the electrodes 940 and the second dielectric layers ( In the case of including the third dielectric layer 930 formed to cover the 920, it is also possible to further form the fourth dielectric layer 1120 to cover the third dielectric layer 930.

Here, in FIG. 11C, the substrate 900 may be the front substrate 301 or the rear substrate 311 as shown in FIG. 3A.

In addition, the electrode 940 may be the address electrodes 313a, 313b, and 313c as shown in FIG. 3A, or may be the scan electrodes 302 and Y or the sustain electrodes 303 and Z as shown in FIG. 7.

The dielectric constant of the fourth dielectric layer 1120 is preferably higher than that of the third dielectric layer 930. This fourth dielectric layer 930 has a dielectric constant large enough to protect the electrode 940.

As such, the dielectric layer can be formed in various structures.

As such, the technical configuration of the present invention described above can be understood by those skilled in the art that the present invention can be implemented in other specific forms without changing the technical spirit or essential features of the present invention.

Therefore, the exemplary embodiments described above are to be understood as illustrative and not restrictive in all respects, and the scope of the present invention is indicated by the appended claims rather than the foregoing detailed description, and the meaning and scope of the claims are as follows. And all changes or modifications derived from the equivalent concept should be interpreted as being included in the scope of the present invention.

The plasma display panel of the present invention described above further includes a dielectric layer having a relatively low dielectric constant between the electrode and the substrate, thereby reducing driving parasitic capacitance, thereby improving driving efficiency.

Claims (15)

Board; A first dielectric layer formed on the substrate; An electrode formed on the first dielectric layer; And A second dielectric layer having a different dielectric constant from the first dielectric layer and formed over the first dielectric layer to cover the electrode; Plasma display panel comprising a. The method of claim 1, And wherein the first dielectric layer has a lower dielectric constant than the second dielectric layer. The method of claim 2, And a dielectric constant of the first dielectric layer is 0.01 to 0.5 times the dielectric constant of the second dielectric layer. The method of claim 1, And the thickness of the first dielectric layer is 0.1 to 10 times the thickness of the electrode. The method of claim 4, wherein And the thickness of the first dielectric layer is the same as the thickness of the electrode. The method of claim 1, And the thickness of the second dielectric layer is at least 2 times and at most 10 times the thickness of the electrode. The method of claim 1, And the first dielectric layer has protrusions protruding in the direction of the second dielectric layer between the electrodes. The method of claim 7, wherein And the protrusion protrudes at the same height as the electrode or protrudes higher. Claim 9 was abandoned upon payment of a set-up fee. Board; A first dielectric layer formed on the substrate; A plurality of electrodes formed on the first dielectric layer; A third dielectric layer formed to cover the electrode and the second dielectric layer; Plasma display panel comprising a. Claim 10 was abandoned upon payment of a setup registration fee. The method of claim 9, And the third dielectric layer has a higher dielectric constant than the first dielectric layer and the second dielectric layer. Claim 11 was abandoned upon payment of a setup registration fee. The method of claim 10, And a dielectric constant of the third dielectric layer is at least two times and at most 100 times the dielectric constant of the first dielectric layer or the second dielectric layer. Claim 12 was abandoned upon payment of a registration fee. The method of claim 9, And the thickness of the first dielectric layer is 0.1 to 10 times the thickness of the electrode. Claim 13 was abandoned upon payment of a registration fee. The method of claim 12, And the thickness of the first dielectric layer is the same as the thickness of the electrode. Claim 14 was abandoned when the registration fee was paid. The method of claim 9, And the thickness of the second dielectric layer is equal to or greater than the thickness of the electrode. Claim 15 was abandoned upon payment of a registration fee. The method of claim 9, And the thickness of the third dielectric layer is at least 2 times and at most 10 times the thickness of the electrode.

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