KR100784379B1 - Semiconductor integrated circuit with de-capsulation function - Google Patents

Abstract

The de-encapsulation detection circuit of the smart card disclosed herein consists of first and second voltage dividers and a comparator. The first voltage divider has first and second capacitors, and distributes a power supply voltage to output a first voltage. The second voltage divider has third and fourth capacitors, and divides the power supply voltage to output a second voltage. The comparator compares the first voltage and the second voltage and outputs a comparison signal as the comparison result. Each of the first and fourth capacitors is formed of a metal line arranged on a top layer of a plurality of metal lines formed on the smart card, and each of the second and third capacitors is one metal line of the remaining metal lines. Is formed.

De-Encapsulation, Comparators, Metal Lines, Capacitors, Voltage Dividers

Description

Semiconductor Integrated Circuits with De-Encapsulation Protection {SEMICONDUCTOR INTEGRATED CIRCUIT WITH DE-CAPSULATION FUNCTION}

1 is a circuit diagram showing a decapsulation detection circuit according to a preferred embodiment of the present invention;

2A is a cross-sectional view showing the metal capacitors shown in FIG. 1 before the protective film is removed; And

FIG. 2B is a cross-sectional view illustrating the metal capacitors shown in FIG. 1 after the protective film is removed. FIG.

Explanation of symbols on the main parts of the drawings

100: decapsulation circuit 120, 140: voltage divider

160: comparator

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor integrated circuits, and more particularly, to a decapsulation detection circuit that detects whether a protective film (or an oxide film) formed on a surface of a semiconductor integrated circuit chip has been removed.                         

In general, an IC card, called a smart card, has the same shape and size as a conventional magnetic stripe card, and there are two types of contact and contactless devices, a memory card and a chip card. More precisely, an IC card with a built-in microprocessor is called a smart card, and a contactless card and a memory card without a built-in microprocessor are referred to as a separate name of 'contactless IC card and memory card'. A smart card consists of a central processing unit, EEPROM, ROM, and RAM that store application programs. The most basic advantages of smart cards are high reliability / security, large data storage, and electronic wallet (E-purse) functions, and various applications can be loaded.

As described above, the data stored inside the smart card has a main purpose of safe storage, and when it is leaked to the outside, it is a great risk factor for the user and the system operator. In particular, monitoring signals directly inside the chip to find out the data inside the smart card can lead to fatal data loss. One of such monitoring methods is a method of removing a silicon oxide layer (SiO 2) covering a surface of a chip and monitoring a metal line exposed to the surface of the chip using an oscilloscope. Here, removing the silicon oxide film used as the protective film on the chip surface is referred to as "de-capsulation". When de-encapsulating a chip to prevent monitoring of the chip's internal signals, a detection device is needed that indicates the chip's de-encapsulation.

Such a detection device can be implemented in the following way. By detecting some of the lines inside the chip using polysilicon, removing the silicon oxide film, placing the polysilicon line inside the chip, and inserting a circuit in which the operation is determined according to the connection state of the polysilicon line, the detection apparatus can be implemented. have. If the silicon oxide film is removed, the polysilicon line having properties similar to that of the silicon oxide film is also broken, so that a circuit connected to the polysilicon line does not operate.

As the semiconductor manufacturing process develops, the circuit line width becomes smaller and the space between lines becomes smaller. In addition, since complex circuits have to be implemented in a small area, the line topology is increased by stacking the metal lines connecting the devices in multiple layers. The de-encapsulation detection device described above detects whether a chip is de-encapsulated by arranging a polysilicon line used as a gate of a MOS transistor to come out on the surface of the chip together with a silicon oxide film used as a protective film of the chip.

However, as the manufacturing process becomes more complicated and the metal layer becomes higher, the process of lifting the polysilicon line, which is used as a gate, on the surface of the chip requires a lot of cost and time, which causes the manufacturing cost of the chip. Therefore, a new decapsulation detection circuit is needed.

It is an object of the present invention to provide a decapsulation detection circuit capable of detecting whether a protective film formed on a surface of a semiconductor integrated circuit has been removed without increasing the manufacturing cost.

(Configuration)

According to a feature of the present invention for achieving the above object, a smart card includes a de-encapsulation detection circuit, and the de-encapsulation circuit is composed of first and second voltage dividers and a comparator. The first voltage divider has first and second capacitors, and distributes a power supply voltage to output a first voltage. The second voltage divider has third and fourth capacitors, and divides the power supply voltage to output a second voltage. The comparator compares the first voltage and the second voltage and outputs a comparison signal as the comparison result. Each of the first and fourth capacitors is formed of a metal line arranged on a top layer of a plurality of metal lines formed on a smart card, and each of the second and third capacitors is one of the remaining metal lines. Is formed.

In this embodiment, the first capacitor has the same size as the fourth capacitor, and the second capacitor has the same size as the third capacitor.

In this embodiment, the first and second capacitors are connected in series between the power supply voltage and the ground voltage, and the first voltage is output from the connection node of the first and second capacitors.

In this embodiment, the third and fourth capacitors are connected in series between the power supply voltage and the ground voltage, and the second voltage is output from the connection node of the third and fourth capacitors.

(Action)                     

According to such a circuit, the de-encapsulation detection circuit can be implemented without increasing the chip manufacturing cost by using metal line capacitors whose capacitance varies depending on whether the protective film formed on the chip surface is removed.

(Example)

DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will now be described in detail with reference to the drawings. The de-encapsulation detection circuit according to the present invention is, for example, an 8-bit single-chip CMOS controller (Samsung Electronics' KS88C9408 microcontroller), which is included in a smart card and covers a chip surface (e.g., The silicon oxide film) is removed and the detection result is provided to the central processing unit built in the smart card. The central processing unit performs various control operations (e.g., prevents power-off or leakage of stored data information) according to the detection result. The smart card or KS88C9408 microcontroller includes a central processing unit, general purpose register file and data buffer SRAM, data memory EEPROM, program memory ROM, serial input / output interface, and the like.

1 is a circuit diagram showing a decapsulation detection circuit according to a preferred embodiment of the present invention. Referring to FIG. 1, the decapsulation detection circuit 100 detects whether a protective film (eg, silicon oxide film) covering a chip surface has been removed and outputs a detection signal nDECAP as a detection result. . This detection signal nDECAP is transmitted to the central processing unit of the smart card to which the de-encapsulation detection circuit is applied. The de-encapsulation detection circuit 100 consists of first and second voltage dividers 120 and 140, a comparator 160, a PMOS transistor MP4, an NMOS transistor MN3 and an inverter INV.

1, the first voltage divider 120 is composed of first and second metal line capacitors MET3CAP1 and MET2CAP1 and distributes a power supply voltage VDD to draw a first voltage on ND1. Output The first and second metal line capacitors MET3CAP1 and MET2CAP1 are connected in series between the power supply voltage VDD and the ground voltage VSS in this order. The second voltage divider 140 is composed of third and fourth metal line capacitors MET2CAP2 and MET3CAP2, and distributes the power supply voltage VDD to output a second voltage on ND2. The third and fourth metal line capacitors MET2CAP2 and MET3CAP2 are connected in series between the power supply voltage VDD and the ground voltage VSS in this order.

The comparator 160 compares the voltage provided from the first voltage divider 120 with the voltage provided from the second voltage divider 140 and outputs a comparison signal OUT as a result of the comparison. The comparator 160 is composed of three PMOS transistors MP1-MP3 and two NMOS transistors MN1 and MN2 and is connected as shown. The PMOS transistor MP4 and the NMOS transistor MN3 are connected in series between the power supply voltage VDD and the ground voltage VSS, by the bias voltage VBIAS and the output signal OUT of the comparator 160. Each controlled. The inverter INV is connected to a common connection node of the transistors MP4 and MN3 and outputs a detection signal nDECAP of the de-encapsulation detection circuit 100 according to the potential of the common connection node.                     

According to the de-encapsulation detection circuit 100 of the present invention, the first and fourth metal line capacitors MET3CAP1 and MET3CAP2 have the same size, and the second and third metal line capacitors MET2CAP1 and MET2CAP2. ) Have the same size. The size (or capacity) of the first and fourth metal line capacitors MET3CAP1 and MET3CAP2 is greater than the second and third metal line capacitors MET2CAP1 and MET2CAP2 (for example, by 0.05 μs). . The first and fourth metal line capacitors MET3CAP1 and MET3CAP2 are implemented using a smart card, that is, a metal line arranged on the uppermost layer of the chip, as shown in FIG. 2A, and the second and third metals. The line capacitors MET2CAP1 and MET2CAP2 are implemented using a metal line arranged in one of the remaining layers except for the top layer. As can be seen in FIG. 2A, the metal lines METAL3 and METAL 2 are insulated by an oxide film (eg, silicon oxide film) to be electrically insulated from each other.

The capacitance of each of the metal line capacitors implemented with the metal lines is, as is well known, determined by the following equation.

Here, A represents the area of the metal line used as the plate of the capacitor, L represents the distance between the metal lines formed on the same layer, Eox represents the dielectric constant of the silicon oxide film. In order to make the size (or capacity) of the first and fourth metal line capacitors MET3CAP1 and MET3CAP2 larger than the second and third metal line capacitors MET2CAP1 and MET2CAP2, The length of METAL3) is adjusted to be shorter than the length of the metal lines METAL2 formed in the underlying layer.

The operation of the decapsulation detection circuit according to the present invention is as follows.

If the protective layer on the chip surface is not removed, according to the previous assumption, since the size of each of the metal line capacitors MET3CAP1 and MET3CAP2 is larger than the size of each of the metal line capacitors MET2CAP1 and MET2CAP2, The voltage is relatively higher than the voltage at the ND2 node. This means that the output signal OUT of the comparator 160 is at a high level. The NMOS transistor MN3 is turned on by the high level output signal OUT, and as a result, the high level detection signal nDECAP is provided to the central processing unit of the smart card through the inverter INV. The high detection signal nDECAP means that the oxide film used as the protective film is not removed.

On the contrary, when the protective film covered on the chip surface is removed, the value of each metal line capacitor MET3CAP1 and MET3CAP2 is smaller than the value of each metal line capacitor MET2CAP1 and MET2CAP2. This is because the oxide film existing between the metal lines METAL3 (see FIG. 2B) is removed. That is, since the dielectric constant of air is' 1 'and the dielectric constant of the oxide film is' 3.9, the value of each metal line capacitor (MET2CAP1, MET2CAP2) is maintained while the value of each metal line capacitor (MET3CAP1, MET3CAP2) is maintained. Decreases to 1 / 3.9. Accordingly, the voltage of the ND1 node is lower than the voltage of the ND2, and the comparator 160 outputs a low level signal OUT. Accordingly, the NMOS transistor MN3 is turned off and the low level detection signal nDECAP is output through the inverter INV. That is, the central processing unit of the smart card recognizes that the protective film covered on the surface of the chip is removed according to the low level detection signal nDECAP, and performs a preset protection operation on the stored data.

In the above, the configuration and operation of the circuit according to the present invention has been shown in accordance with the above description and drawings, but this is only an example, and various changes and modifications can be made without departing from the spirit and scope of the present invention. Of course.

As described above, the de-encapsulation detection circuit can be implemented without increasing the chip manufacturing cost by using metal line capacitors whose capacitance varies depending on whether the protective film formed on the chip surface is removed.

Claims (8)

In a semiconductor integrated circuit having a plurality of metal lines sequentially formed on a semiconductor substrate: A first voltage divider having first and second capacitors and distributing a power supply voltage to output a first voltage; A second voltage divider having third and fourth capacitors, the second voltage divider dividing the power supply voltage to output a second voltage; Comparing the first voltage and the second voltage and outputs a comparison signal as the comparison result, Each of the first and fourth capacitors is formed of a metal line arranged on an uppermost layer of the plurality of metal lines; And each of the second and third capacitors is formed of one metal line of the remaining metal lines. The method of claim 1, And the first capacitor has the same size as the fourth capacitor, and the second capacitor has the same size as the third capacitor. The method of claim 2, And the first and second capacitors are connected in series between the power supply voltage and the ground voltage, and the first voltage is output from a connection node of the first and second capacitors. The method of claim 2, And the third and fourth capacitors are connected in series between the power supply voltage and the ground voltage, and the second voltage is output from a connection node of the third and fourth capacitors. A smart card of a multi-layer structure having a central processing unit, a general register file and an SRAM for a data buffer, an EPIROM for a data memory, a ROM for a program memory, and composed of a plurality of metal layers is located on the top layer of the multi-layer structure. A decapsulation detection circuit for detecting whether the protective film formed on the substrate is removed; The decapsulation detection circuit, A first voltage divider having first and second capacitors and distributing a power supply voltage to output a first voltage; A second voltage divider having third and fourth capacitors, the second voltage divider dividing the power supply voltage to output a second voltage; Comparing the first voltage and the second voltage and outputs a comparison signal as the comparison result, Each of the first and fourth capacitors is formed of a metal line arranged on an uppermost layer of the plurality of metal lines; And each of the second and third capacitors is formed of one metal line of the remaining metal lines. The method of claim 5, And the first capacitor has the same size as the fourth capacitor, and the second capacitor has the same size as the third capacitor. The method of claim 6, And the first and second capacitors are connected in series between the power supply voltage and the ground voltage, and the first voltage is output from a connection node of the first and second capacitors. The method of claim 6, And the third and fourth capacitors are connected in series between the power supply voltage and the ground voltage, and the second voltage is output from the connection node of the third and fourth capacitors.

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