KR100781442B1 - Method for removing edge bead on the wafer - Google Patents

Abstract

A method for eliminating a wafer edge bead is provided to prevent a particle contamination source generated at a wafer edge region by forming a sidewall of a lower interlayer dielectric to be contacted to an upper interlayer dielectric through a metal layer. A lower interlayer dielectric(110) is formed on a semiconductor substrate(100). The lower interlayer dielectric is removed as much as a first region from an end of a wafer edge. A conductive layer is formed on a contact hole of the lower interlayer dielectric is planarized by using a CMP process to form a contact on the contact hole at the same time when a conductive layer spacer(140a) is formed at a sidewall of the lower interlayer dielectric. A metal layer is formed on the lower interlayer dielectric. The metal layer is removed as much as a second region smaller than the first region from the end of the wafer edge. An upper interlayer dielectric(180) is formed on the metal layer and the semiconductor substrate.

Description

METHOD FOR REMOVING EDGE BEAD ON THE WAFER}

1A to 1G are process flowcharts sequentially illustrating a wafer edge bead removal process according to the prior art;

2a and 2b is a view showing a defect generated during the wafer edge bead removal process according to the prior art,

3A-3H are process flow diagrams sequentially illustrating a wafer edge bead removal process in accordance with the present invention.

<Description of the code | symbol about the principal part of drawing>

100 semiconductor substrate 110 lower interlayer insulating film PMD

120, 160: photoresist pattern 130: first region

140: conductive film 140a: conductive film spacer

150: metal film 170: second region

180: upper interlayer insulating film (IMD)

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor manufacturing method, and in particular, it is possible to prevent particle contaminants generated in the wafer edge region during wafer edge bead removal (EBR) and wafer edge exposure (WEE) processes. Wafer edge bead removal method.

In general, a method of manufacturing a semiconductor device is formed by repeating the deposition and patterning of a thin film, an ion implantation process, and a thin film etching several times. In the process of stacking and patterning a thin film many times, when the edge of the wafer becomes thick or unnecessary films are accumulated on the sidewall of the wafer, it becomes a source of particle generation.

Wafer edge bead removal (EBR) and wafer edge exposure (WEE) processes can generate photoresist particles in the wafer edge area when coating and patterning the photoresist, resulting in poor patterning in the cell. It refers to the process of removing the photoresist by about 1 mm to 3 mm at the end.

1A to 1G are process flowcharts sequentially illustrating a wafer edge bead removal process according to the prior art.

Referring to these figures, an example of a prior art wafer edge bead removal (EBR) process proceeds as follows.

First, as shown in FIG. 1A, a predetermined semiconductor structure layer (not shown) is formed on a silicon substrate as the semiconductor substrate 10. Here, the semiconductor structure layer may be a transistor, a memory cell, a capacitor, or the like.

An interlayer insulating film (PMD) 20 is formed to a thickness of about 3000 kPa to about 5000 kPa on the entire surface of the semiconductor substrate having the semiconductor structure layer. Here, the interlayer insulating film (PMD) 20 may be formed of an oxide of SiO 2 series having a low dielectric constant or an oxide containing impurities such as C, F, B, P, and In. For example, the BPSG ( It may be a Boron Phosphorus Silicate Glass (PSG), Phosphorus Silicate Glass (PSG), Un-doped Silicate Glass (USG), Fluorinated Silicate Glass (FSG), or SiO2 film, or an oxide film in which hydrogen, fluorine, or the like is bonded to SiO or SiO2. In addition, the interlayer insulating film (PMD) 20 may be formed of a single layer made of any one of the oxide films, or may be formed of a complex structure in which at least two layers of the films are stacked.

Then, the interlayer insulating film (PMD) 20 is planarized by a chemical mechanical polishing (CMP) process, a photolithography process is performed to coat the photoresist on the interlayer insulating film (PMD) 20, and then an exposure and development process. The photoresist pattern 30 is formed to open the wafer edge bead removal (EBR) / wafer edge exposure (WEE) region 40.

As shown in FIG. 1B, the interlayer insulating film (PMD) 20 exposed by the photoresist pattern is etched and removed to expose the semiconductor substrate 10 at the wafer edge, and then the photoresist pattern is removed by a process such as etching. .

In addition, a contact hole (not shown) is formed in an interlayer insulating film (PMD) 20 by an etching process such as reactive ion etching (RIE), and the conductive layer 50, for example, tungsten (W), is formed to be gap-filled in the contact hole. ), And the conductive film 50 on the surface of the interlayer insulating film (PMD) 20 is removed by a chemical mechanical polishing (CMP) process.

As shown in FIG. 1C, the edge of the interlayer dielectric (PMD) 20 along the wafer edge bead removal (EBR) / wafer edge exposure (WEE) region 40 line by a chemical mechanical polishing (CMP) process of the conductive film. Conductive film spacers 50a that are etch residues are formed on the sidewalls.

Subsequently, as shown in FIG. 1D, aluminum (Al), titanium (Ti), titanium nitride (TiN), or the like is deposited as the metal film 60 on the entire upper surface of the interlayer insulating film (PMD) 20.

As shown in FIG. 1E, the photoresist is coated on the metal layer 60 to expose the photoresist, followed by the exposure and development processes to remove the wafer edge bead (EBR) / wafer edge exposure (WEE) region ( A photoresist pattern 70 for opening 40 is formed.

Subsequently, as illustrated in FIG. 1F, the metal film of the wafer edge bead removal (EBR) / wafer edge exposure (WEE) region 40 exposed by the photoresist pattern is etched away and the other interlayer insulating film (PMD) 20 is removed. After exposing the semiconductor substrate 10 at the wafer edge by forming the metal film pattern 60a thereon, the photoresist pattern is removed by a process such as etching.

Then, an upper interlayer insulating film (IMD) 80 is deposited to a thickness of 5000 kPa to 10,000 kPa on the entire surface of the semiconductor substrate having the metal film pattern 60a. Here, the interlayer insulating layer (IMD) 80 may be formed of an oxide of SiO 2 series having a low dielectric constant, or may be made of HDP (High Density Plasma) oxide.

Then, as shown in FIG. 1G, the upper interlayer insulating film (IMD) 80 is planarized by a chemical mechanical polishing (CMP) process, and the multilayer wiring manufacturing process is continued on the flattened interlayer insulating film (IMD) 80. do.

The wafer edge bead removal (EBR) process according to the prior art removes the wafer edge bead after depositing the lower interlayer insulating film (PMD) 20, the metal film 60, the upper interlayer insulating film (IMD) 80, and the like. By removing the interlayer insulating film and the metal film of the (EBR) / wafer edge exposure (WEE) region 40, particle contamination caused by thickening of the edge of the wafer (i.e., semiconductor substrate) or by the accumulation of unnecessary films on the sidewall of the wafer is prevented.

However, in the conductive film chemical mechanical polishing (CMP) process gap-filled in the contact hole of the interlayer insulating film (PMD) 20, the interlayer insulating film (PMD) of the wafer edge bead removal (EBR) / wafer edge exposure (WEE) region 40 (20) Conductive film spacers 50a remain along the sidewalls of the lines. As a result, the adhesion between the conductive spacer 50a and the interlayer dielectric (IMD) 80 is bad during the chemical mechanical polishing (CMP) process of the subsequent interlayer dielectric (IMD) 80. A crack occurs due to the polishing stress of the (80), and eventually, the interlayer insulating film (IMD) 80 of the upper part is broken in the wafer edge bead removal (EBR) / wafer edge exposure (WEE) region 40 and the particles are broken. It acts as a pollution source 90 (FIG. 1G).

2A and 2B illustrate defects generated during the wafer edge bead removal process according to the prior art.

As shown in FIGS. 2A and 2B, as a result of analyzing the cause of particle defects found in the back end of the line (BEOL) process, the wafer edge bead removal (EBR) / wafer edge exposure (WEE) region of the wafer edge is analyzed. It can be seen that circles and various types of particles (a, b) occur in the line.

Therefore, the wafer edge bead removal (EBR) method according to the prior art has a conductivity of the wafer edge bead removal (EBR) / wafer edge exposure (WEE) region line during the chemical mechanical polishing (CMP) process of the upper interlayer insulating film (IMD). Cracks occur at the portions where the film spacers abut and are broken, which causes the broken interlayer insulating material to remain as particles, thereby lowering the semiconductor manufacturing yield.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems of the prior art, and thus, during the wafer edge bead removal (EBR) and wafer edge exposure (WEE) processes, the metal layer is less etched than the lower interlayer insulating layer in the wafer edge region. By providing the sidewall of the interlayer insulating film with the upper interlayer insulating film through a metal film, it provides a wafer edge bead removal method that can reduce the polishing stress of the upper interlayer insulating film in the chemical mechanical polishing process to prevent particle contamination generated in the wafer edge region in advance. It is.

In order to achieve the above object, the present invention provides a method for removing particles and beads in a wafer edge region, the method comprising: forming a lower interlayer insulating film on a semiconductor substrate, and removing the lower interlayer insulating film by a first region from a wafer edge end; Forming a conductive film in the contact hole of the lower interlayer insulating film and planarizing it by a chemical mechanical polishing process to form a contact in the contact hole, and forming a conductive film spacer on the sidewall of the lower interlayer insulating film, and Forming a film, removing the metal film by the second region smaller than the first region from the wafer edge end, and forming an upper interlayer insulating film on the metal film and the semiconductor substrate.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention.

3A-3H are process flow diagrams sequentially illustrating a wafer edge bead removal process in accordance with the present invention.

Referring to these figures, an example of a wafer edge bead removal (EBR) process according to the present invention proceeds as follows.

First, as shown in FIG. 3A, a predetermined semiconductor structure layer (not shown) is formed on a silicon substrate as the semiconductor substrate 100. Here, the semiconductor structure layer is a transistor, a memory cell, a capacitor, or the like.

A lower interlayer insulating film (PMD) 110 is formed to a thickness of about 3000 kPa to about 5000 kPa on the entire surface of the semiconductor substrate having the semiconductor structure layer. Here, the interlayer insulating layer (PMD) 110 may be formed of an oxide of SiO 2 series having a low dielectric constant or an oxide including impurities such as C, F, B, P, and In, for example, BPSG, PSG , USG, FSG, or SiO 2 film, or an oxide film in which hydrogen, fluorine, or the like is bonded to SiO or SiO 2. In addition, the interlayer insulating layer (PMD) 110 may be formed of a single layer formed of any one of the oxide layers, or may be formed of a complex structure in which at least two layers of the layers are stacked.

Then, the interlayer insulating film (PMD) 110 is planarized by a chemical mechanical polishing (CMP) process, a photolithography process is performed to coat the photoresist on the interlayer insulating film (PMD) 110, and then an exposure and development process is performed. A photoresist pattern 120 for opening one wafer edge bead removal (EBR) / wafer edge exposure (WEE) region 130 is formed. At this time, the photoresist pattern 120 is removed about 2 mm to 5 mm at the wafer edge end. That is, the distance of the first wafer edge bead removal (EBR) / wafer edge exposure (WEE) region 130 has a distance of about 2 mm to 5 mm at the wafer edge end.

As shown in FIG. 3B, the interlayer insulating film (PMD) 110 exposed by the photoresist pattern is etched and removed to expose the semiconductor substrate 100 at the wafer edge, and then the photoresist pattern is removed by a process such as etching. .

In addition, a contact hole (not shown) is formed in the interlayer insulating layer PMD 110 by an etching process such as RIE, and a conductive film 140, for example tungsten (W), is deposited to be gap-filled in the contact hole.

As shown in FIG. 3C, the conductive film is formed only in the contact hole of the interlayer insulating film (PMD) 110 by removing tungsten (W), which is a conductive film on the surface of the interlayer insulating film (PMD) 110, by a chemical mechanical polishing (CMP) process. Form a contact (not shown) to remain. Through the chemical mechanical polishing (CMP) process of the conductive film, an electrically conductive film spacer as an etching residue on the edge sidewall of the interlayer insulating film (PMD) 110 along the first wafer edge bead removal (EBR) / wafer edge exposure (WEE) region line. 140a) is formed.

Subsequently, as illustrated in FIG. 3D, aluminum (Al), titanium (Ti), titanium nitride (TiN), and the like are deposited as the metal film 150 on the entire upper surface of the interlayer insulating film (PMD) 110.

As shown in FIG. 3E, after the photoresist is coated on the metal film 150 to expose the photoresist, the exposure and development processes are performed to remove the second wafer edge bead (EBR) / wafer edge exposure (WEE). A photoresist pattern 160 is formed to open the region 170. In this case, the photoresist pattern 160 is removed smaller than the photoresist pattern for etching the interlayer insulating film (PMD) 110 in the range of about 2 mm to 5 mm at the edge of the wafer. That is, the distance of the second wafer edge bead removal (EBR) / wafer edge exposure (WEE) region 170 is about 1 mm to 5 mm at the wafer edge end, and the first wafer edge bead removal (EBR) / wafer edge exposure ( WEE) is smaller than the area, for example, has a range of 1 mm to 4 mm.

Subsequently, as shown in FIG. 3F, the metal film in the second wafer edge bead removal (EBR) / wafer edge exposure (WEE) region exposed by the photoresist pattern is etched away and the other interlayer insulating film (PMD) 110 is removed. After forming the metal film pattern 150a on the top and sidewalls of the conductive film spacer 140a to expose the semiconductor substrate 100 at the wafer edge, the photoresist pattern is removed by a process such as etching.

As shown in FIG. 3G, an upper interlayer insulating film (IMD) 180 is deposited to a thickness of about 5000 kPa to 10,000 kPa on the entire surface of the semiconductor substrate having the metal film pattern 150a. Here, the interlayer insulating layer (IMD) 180 may be formed of an SiO 2 series oxide having a low dielectric constant, or may be made of an HDP oxide.

Then, as illustrated in FIG. 3H, the upper interlayer dielectric (IMD) 180 is planarized by a chemical mechanical polishing (CMP) process.

Although not shown in the drawings, a photo process is performed to coat the photoresist on the upper interlayer insulating layer (IMD) 180, followed by an exposure and development process to remove the first wafer edge bead (EBR) / wafer edge exposure. A photoresist pattern for opening the (WEE) region is formed. At this time, the first wafer edge bead removal (EBR) / wafer edge exposure (WEE) region distance has a distance of about 2 mm to 5 mm at the edge of the wafer edge, so that the photoresist pattern is about 2 mm to about the edge of the wafer edge. 5 mm is removed.

The upper interlayer dielectric (IMD) 180 exposed by the photoresist pattern is etched and removed to expose the semiconductor substrate 100 at the wafer edge, and then the photoresist pattern is removed by a process such as etching.

Next, a via hole (not shown) is formed in the upper interlayer insulating film (IMD) 18 by an etching process such as RIE, and a conductive film such as tungsten (W) is deposited so as to be gap-filled in the via hole, and chemical mechanical polishing After the conductive film remains in the via hole of the upper interlayer insulating layer (IMD) 180 to form a contact (not shown) connecting to the lower metal by the CMP process, the metal layer is formed on the entire upper surface of the upper interlayer insulating layer (IMD) 180. For example, aluminum (Al), titanium (Ti), titanium nitride film (TiN), and the like are deposited and patterned to manufacture a multilayer wiring.

Accordingly, the present invention encloses the lower interlayer insulating film (PMD) 110 and the conductive film spacer 140a on its sidewalls in the wafer edge region during the wafer edge bead removal (EBR) and wafer edge exposure (WEE) processes for the metal film. Since the upper interlayer insulating layer (IMD) 180 is not directly in contact with the conductive layer spacer 140a, which is an etch residue, the upper interlayer insulating layer (IMD) during the chemical mechanical polishing process of the upper interlayer insulating layer (IMD) 180 is etched. The polishing stress of 180 may be reduced to prevent particle contamination occurring in the wafer edge region.

On the other hand, the present invention is not limited to the above-described embodiment, various modifications are possible by those skilled in the art within the spirit and scope of the present invention described in the claims to be described later.

As described above, in the wafer edge bead removal (EBR) and wafer edge exposure (WEE) processes, the metal film is less etched than the lower interlayer insulating film (PMD) in the wafer edge region, so that the sidewall of the lower interlayer insulating film is formed through the metal film. By forming the insulating layer in contact with the interlayer insulating layer, it is possible to reduce the generation of cracks due to the polishing stress of the upper interlayer insulating layer during the chemical mechanical polishing process of the upper interlayer insulating layer to prevent particle contamination generated in the wafer edge region.

Therefore, the present invention can prevent particle contamination in a product such as a CMOS image sensor can improve the sensitivity of the light in the region to receive the light, there is an effect that can significantly improve the semiconductor manufacturing yield.

Claims (6)

A method for removing particles and beads in a wafer edge region, Forming a lower interlayer insulating film on the semiconductor substrate, and removing the lower interlayer insulating film by the first region from the wafer edge end; Forming a conductive film in the contact hole of the lower interlayer insulating film and planarizing it by a chemical mechanical polishing process to form a contact in the contact hole, and simultaneously forming a conductive film spacer on the sidewall of the lower interlayer insulating film; Forming a metal film on the lower interlayer insulating film, and removing the metal film by a second area smaller than the first area from an edge of the wafer edge; Forming an upper interlayer insulating film on the metal film and the semiconductor substrate Wafer edge bead removal method comprising a. The method of claim 1, And the first region has a distance of 2 mm to 5 mm from the edge of the wafer edge. The method of claim 1, And the second region has a distance of 1 mm to 4 mm from the end of the wafer edge. The method of claim 1, The method, After forming the upper interlayer insulating film, Removing the upper interlayer insulating layer by a first region from a wafer edge end; Forming a conductive film in the via hole of the upper interlayer insulating film and planarizing it by a chemical mechanical polishing process to form a via in the via hole; Forming a metal film on the upper interlayer insulating film, and removing the metal film by a second area smaller than the first area from an edge of the wafer edge; Forming the interlayer insulating film Wafer edge bead removal method characterized in that it further comprises repeating the steps. The method of claim 4, wherein And the first region has a distance of 2 mm to 5 mm from the edge of the wafer edge. The method of claim 4, wherein And the second region has a distance of 1 mm to 4 mm from the end of the wafer edge.

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