KR20010008613A - Method for removing an edge bead of a wafer - Google Patents

Abstract

PURPOSE: A method for removing an edge bead of a wafer is provided to prevent polysilicon patterns in an edge bead removal(EBR) region and a scribe-line region from being delaminated, by leaving a polysilicon layer for a storage node contact plug or storage node electrode in the EBR region and the scribe-line region. CONSTITUTION: A step part is formed by etching a wafer(100) by the first distance from the edge of the wafer towards the center. After the first polysilicon layer(108) is formed on the wafer, the polysilicon layer is removed by the second distance from the edge of the wafer. After the first oxide layer is formed on the wafer and the first polysilicon layer, the first oxide layer is removed by the third distance from the edge of the wafer. After the second oxide layer(118) is formed on the wafer and the first oxide layer, the second oxide layer is eliminated by the fourth distance from the edge of the wafer. The second polysilicon layer is formed on the second oxide layer and the second polysilicon layer is eliminated by the fifth distance from the edge of the wafer. After the third oxide layer(122) is formed on the wafer and the second polysilicon layer, the third oxide layer is removed by the sixth distance from the edge of the wafer. The third polysilicon layer is formed on the third oxide layer and the third polysilicon layer is eliminated by the seventh distance from the edge of the wafer.

Description

{Method for removing an edge bead of a wafer}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method for removing an edge bed of a wafer which can reduce generation of particles in a DRAM device having a cylindrical capacitor electrode structure.

In general, a method of manufacturing a semiconductor device is formed by repeating the deposition and patterning of a thin film, an ion implantation process, and the like several times. In particular, in order to manufacture integrated circuit devices, a process of stacking multiple thin films, forming and patterning a photoresist film on each thin film, and etching a thin film using the patterned photoresist as a mask are performed several times. In the process of stacking and patterning a thin film several times, when the edge of the wafer becomes thick or unnecessary films are stacked on the sidewall of the wafer, it becomes a source of particle generation.

In particular, when a film is formed on a wafer by spin coating such as a photoresist film, a borophosphosilicate glass (BPSG), a tetraethylortho silicate (TEOS), and a phosphosilica glass (PSG), The same problems arise.

First, the spin coating method is a method of coating a film to have a uniform flatness on a wafer by centrifugal force by dropping a liquid material in a state in which the wafer is rotated at a very high speed. The spin coating method as described above has the following problems. That is, particles mixed with chemicals introduced into the coating apparatus or generated at the work bench in the apparatus adhere to the edges of the wafer and the wafer edges are contaminated with the particles. Particles attached to the wafer edge tend to contaminate the wafer as a whole, moving over the uncontaminated wafer center.

Second, there is a problem in that the edge of the wafer is abnormally thick by forming a bed (ring-shaped decoration) on the wafer edge. When the edge of the wafer becomes thick, when the wafer is loaded into the cassette for transferring the wafer, the edge of the wafer is broken and there is a problem of contaminating the upper surface of the wafer.

Therefore, in order to solve such a problem, conventionally, a thin film is formed on a wafer, and then the photosensitive film or thin film of the edge portion of the wafer is etched away to prevent the wafer edge from becoming thick and also the wafer edge is contaminated by the contamination of the wafer edge. There is a method to prevent the overall contamination, which is called the edge bead rinsing or edge bead removal (EBR) method, that is, the edge bed removal method.

In the conventional semiconductor device manufacturing method, in particular, in the DRAM device manufacturing method having a cylindrical capacitor, an EBR process will be described with reference to the accompanying drawings. In the drawing, only the EBR region is shown, and the memory cell manufacturing process is not shown.

First, as shown in Figure 1a, the wafer is etched away from the edge to about 5mm inward. The wafer edge etching process is performed simultaneously with the process of forming a device isolation region by a trench method in a semiconductor device manufacturing process.

That is, in order to form a device isolation region in manufacturing a DRAM device, an oxide film 102 and a nitride film 104 are sequentially formed on the wafer 100, and a photoresist film 106 is formed on the nitride film 104. The photoresist film of the portion to be the separation region is removed, and the photoresist film 106 is removed not only in the device isolation region but also near the wafer edge (up to about 5 mm from the edge).

Next, the trench is formed in the semiconductor substrate 100 using the photoresist layer 106 as a mask, and the semiconductor substrate 100 at the edge of the wafer is also etched to etch away the wafer edge by the depth of the trench. The stepped bottom portion 100a is formed.

Next, the photosensitive film 106, the nitride film 104, and the oxide film 102 are removed.

Next, a first polysilicon layer 108 for forming a gate electrode is formed on the upper surface of the semiconductor substrate 100. The first polysilicon layer 108 is also formed on the wafer edge, that is, the stepped bottom part 100a. In order to form a gate electrode with the first polysilicon layer 108, a photoresist layer is formed on the first polysilicon layer 108, and then the photoresist is patterned to form a photoresist pattern (not shown) in a shape corresponding to the gate electrode. Form.

At this time, the photoresist pattern for forming the gate electrode is removed up to 6 mm from the wafer edge. When the first polysilicon layer is etched using the photoresist pattern for forming the gate electrode as a mask, the gate electrode 108 is formed, and the polysilicon layer of the stepped bottom portion 100a is removed, and the stepped bottom portion 100a is formed. The first polysilicon layer sidewall spacers 110 are formed on sidewalls of the semiconductor substrate of the semiconductor device manufacturing region 100b at corner portions where the unetched portions of the wafer 100 meet.

Next, a first nitride film 112 is formed over the entire structure of the upper portion of the wafer 100, and anisotropic etching is performed to form first nitride film sidewall spacers (not shown) on both sidewalls of the gate electrode. A first nitride film sidewall spacer 112a is also formed on the sidewall of the first polysilicon layer sidewall spacer 112 of the edge portion to form the structure of FIG. 1B.

Next, a thick first oxide film 114 is formed over the entire structure of FIG. 1B. The first oxide film 114 is an interlayer insulating film for insulating a gate electrode and a conductive film to be formed later, that is, a node electrode of a bit line or a capacitor.

Next, after the photoresist is formed on the first oxide layer 114, a first bit line contact hole and a first storage node contact hole for forming a first bit line contact plug and a first storage node contact plug may be formed. A photosensitive film pattern is formed. In this case, the photoresist pattern for the first contact hole and the first storage node contact hole is removed up to about 4 mm from the wafer edge to expose the first oxide layer 114 at the wafer edge.

The first oxide layer 114 is etched using the first contact hole photoresist pattern to form a first bit line and a storage node contact hole (not shown), and simultaneously form the first oxide layer pattern 114. do. The first oxide layer pattern 114 is formed to have a sidewall 4 mm from the wafer edge.

Subsequently, a second polysilicon layer is formed on the upper surface of the semiconductor substrate, and then a first anisotropic etching is performed without a mask, thereby forming a first bit line contact plug and a first storage node contact plug in the first contact holes (not shown). And a second polysilicon layer sidewall spacer 116 on the sidewalls of the first oxide film 114 at the wafer edge.

Next, a second oxide film 118 is formed on the entire upper surface of the wafer, and a photoresist film is formed on the second oxide film 118. Next, the photoresist is patterned to form a photoresist pattern for a second bit line contact hole for forming a second bit line contact plug on the first bit line contact plug.

At this time, the photosensitive film is removed from the edge of the wafer to the inner portion of 3mm at the time of forming the photosensitive film pattern. Thereafter, the second oxide layer 118 is etched using the photoresist pattern as a mask to form a second bit line contact hole (not shown), and at the same time, the second oxide layer 118 extends from a wafer edge portion to a 3 mm portion inward of the wafer. ).

Next, a third polysilicon layer 120 is deposited on the entire structure of the semiconductor substrate 100. The third polysilicon layer 120 fills the inside of the second contact hole to form a second bit line contact plug. Next, a photoresist film is formed on the third polysilicon layer 120 and then patterned to form a photoresist pattern for forming a bit line. When the photoresist pattern is formed, the photoresist may be removed up to 6 mm from the edge of the wafer.

When the third polysilicon layer is etched using the bit line forming photoresist pattern as a mask, the bit line 120 is formed and at the side of the third oxide layer 118 near the edge of the wafer, the side of the third polysilicon layer is formed. The wall spacer 120a is formed.

A second nitride film is formed on the entire surface of the semiconductor substrate and then anisotropically etched to form a second nitride film sidewall spacer 121 on the sidewall of the bit line 120 to form the structure of FIG. 1C.

A thick third oxide film 122 is formed over the entire structure of FIG. 1C. Next, a photoresist film is formed on the top surface of the third oxide layer 122 and then patterned to form a photoresist pattern for forming a second storage node contact hole for a second storage node contact plug. At this time, the photoresist is patterned so that the photoresist is removed up to 2.5 mm from the wafer edge during patterning. Next, the third oxide layer 122 is etched using the third contact hole forming photoresist pattern as a mask to form a second storage node contact hole, and the third oxide layer is removed from the wafer edge to 2.5 mm inward. The third oxide film pattern 122 is formed.

A fourth polysilicon layer is formed on the entire surface of the semiconductor substrate and then anisotropically etched to form a second storage node contact plug in the second storage node contact hole. A fourth polysilicon layer sidewall spacer 124 is formed on the sidewalls of the wafer edge.

Next, a fourth oxide film 126 is formed on the entire surface of the structure on the semiconductor substrate to form the shape of the storage node electrode of the capacitor. Next, a photoresist layer is formed on the fourth oxide layer 126 and then patterned to form a photoresist pattern having an opening in a portion where the storage node electrode is to be formed.

At this time, the photoresist is patterned so that the photoresist is removed to a portion of about 1.5 mm from the wafer edge. Next, the fourth oxide layer 126 is etched using the photoresist pattern as a mask to form a trench for forming a storage node electrode, and at the same time, the fourth oxide layer 126 is etched away from the wafer edge to about 1.5 mm. .

Next, when a fifth polysilicon layer and a buffer oxide film are formed on the entire surface of the semiconductor substrate including the upper surface of the fourth oxide film 126 and the inside of the trench for forming the storage node electrode, the anisotropic etching is performed without a mask. The lower electrode of the capacitor of the fifth polysilicon layer remains in the trench, and the sidewall spacer 128 of the fifth polysilicon layer and the buffer oxide film are formed on the sidewall of the fourth edge 126 of the wafer. The sidewall spacers 130 remain to form the structure of FIG. 1D.

Subsequently, the buffer oxide film 130 and the fourth oxide film 126 are etched away to form a node electrode of the capacitor in the memory cell manufacturing region, and the edge portion of the wafer has a structure as shown in FIG. 1E.

However, the wafer edge bed removal process of the above process has the following problems. That is, as shown in FIG. 1E, when the fourth oxide film and the buffer oxide film are etched after forming the lower electrode of the capacitor, the fourth oxide film may be excessively etched, and thus the surface of the third oxide film 122 may be etched. The polysilicon sidewall spacers 124 and 128 attached to the wafer edge on the top surface of the third oxide film 122 are separated. The separated polysilicon sidewall spacers near the wafer edge are separated from the semiconductor device fabrication region inside the wafer to electrically short the adjacent capacitor lower electrodes or cause a subsequent process to become a source of contamination, causing process failure.

An object of the present invention for solving the above problems is to prevent the polysilicon sidewall spacers from falling off when the oxide film is removed from the edge bead removal (EBR) region near the wafer edge when fabricating the inner cylindrical capacitor lower electrode. The present invention provides a wafer edge bed treatment process that improves process stability in semiconductor device manufacturing and increases reliability and yield of device operation by solving a problem of causing a defect in a patterning process of a semiconductor device and an electrical malfunction of the device.

In addition, in order to achieve the object of the present invention, after depositing a polysilicon layer for forming a storage node contact plug, the polysilicon layer is left at an edge portion of the wafer to prevent falling of the polysilicon sidewall spacers at the edge portion of the wafer. It is to provide an edge bed processing process of a wafer that increases the reliability and yield of device operation.

1A to 1E are process flowcharts showing a wafer edge bed removal method according to the prior art.

2A to 2C are process flow charts illustrating a wafer edge bed removal method according to an embodiment of the present invention.

3A to 3C are process flow charts illustrating a wafer edge bed removal method according to another embodiment of the present invention.

* Explanation of Signs of Major Parts of Drawings *

100... wafer

100a... Wafer edge area

102. Oxide film

104. Nitride film

106. Photoresist

108. First polysilicon layer

110. First Polysilicon Layer Sidewall spacer

112. First nitride film

112a. First Nitride Film Sidewall spacer

114. First oxide film

116. Second Polysilicon Layer Sidewall spacer

118. Second oxide film

120... Third polysilicon layer, bit line

120a... Third Polysilicon Layer Sidewall spacer

121. Second Nitride Film Sidewall spacer

122... Third oxide film

124. Fourth Polysilicon Layer Sidewall spacer

126. Fourth oxide film

128... Fifth Polysilicon Layer Sidewall spacer

130... Buffer Oxide Sidewall spacer

201... 4th polysilicon layer

203... Photoresist pattern

205... Fourth oxide film

208. Fifth Polysilicon Layer Sidewall spacer

301... Fourth oxide film

303... Fifth Polysilicon Layer

305... Buffer oxide

307... Photoresist

The wafer edge bed processing method of the present invention for achieving the above object of the present invention comprises the steps of etching the wafer by the first distance from the edge of the wafer toward the center to form a stepped bottom; Forming a first polysilicon layer on the wafer and then removing the polysilicon layer from the edge of the wafer to a second distance; Forming a first oxide film on the upper surface of the wafer and on the first polysilicon layer, and then removing the first oxide film up to a third distance from an edge of the wafer; Forming a second oxide film on the upper surface of the wafer and on the first oxide film, and then removing the second oxide film from the edge of the wafer to a fourth distance; Forming a second polysilicon layer on the second oxide film and removing the second polysilicon layer from a wafer edge to a fifth distance; Forming a third oxide film on the upper surface of the wafer and on the second polysilicon layer, and then removing the third oxide film to a sixth distance from an edge of the wafer; Forming a third polysilicon layer on the third oxide film and removing the third polysilicon layer from a wafer edge to a seventh distance.

In the wafer edge bed processing method of the present invention for achieving the above object of the present invention, the first, second, third, fourth, fifth, sixth and seventh distance is 5mm, 6mm, 4mm, 3mm respectively. It is preferable that they are 6 mm, 2.5 mm, and 1.5 mm.

Hereinafter, with reference to the drawings will be described a preferred embodiment of the present invention. In addition, this embodiment does not limit the scope of the present invention, but is presented by way of example only.

Referring to the wafer edge bed processing method according to an embodiment of the present invention with reference to the accompanying drawings as follows.

First, the method according to the first embodiment will be described.

First, since the processes of FIGS. 1A to 1C proceed as in the prior art, description thereof will be omitted.

Next, as shown in FIG. 2A, a thick third oxide film 122 is formed on the entire structure of the semiconductor substrate 100. Next, a photoresist layer is formed on the top surface of the third oxide layer 122 and then patterned to form a photoresist pattern for forming a second storage node contact hole. In this case, when the photoresist pattern is formed, the photoresist is removed to 2.5 mm from the edge of the wafer to expose the third oxide layer 122. Next, the third oxide layer 122 is etched using the photoresist pattern as a mask to form a second storage node contact hole, and the third oxide layer is removed from the wafer edge to 2.5 mm inward to remove the third oxide layer pattern 122. ) To form the structure of FIG.

Next, as shown in FIG. 2 (b), the fourth polysilicon layer 201 for forming the second node contact plug is formed on the entire structure of FIG. 2A. Next, after forming the negative photosensitive film 203 on the fourth polysilicon layer, it is developed after exposure using a conventional scribe line mask so as to expose only the scribe line and the edge vicinity of the wafer.

As a result, the portion up to 1.5 mm from the edge of the wafer and the photosensitive film on the upper surface of the semiconductor element manufacturing region (memory cell region) are removed. That is, the photoresist pattern 203 remains on the upper surface of the scribe line and the upper surface of the fourth polysilicon layer 201 in the EBR region excluding 1.5 mm away from the wafer edge. Next, the photoresist layer pattern 203 is used as a mask, and the fourth polysilicon layer on the semiconductor substrate is etched to the entire surface, so that the plug of the fourth polysilicon layer (the second storage node contact plug) is formed only in the second storage node contact hole. The remaining fourth polysilicon layer is etched away.

Next, a fourth oxide film 205 for forming a storage node electrode of a capacitor is formed on the entire structure of FIG. 2B, and then a photoresist pattern for forming a storage node electrode is formed on the fourth oxide film. When the photoresist pattern is formed, a photoresist layer up to 2.5 mm from the edge of the storage node electrode and the wafer is removed.

The fourth oxide film 205 is etched using the photoresist pattern for forming the storage node electrodes as a mask to form a trench for forming the storage node electrodes, and at the same time, the fourth oxide film 205 from the edge of the wafer to 2.5 mm inward is formed. Etch it off. At this time, the fourth polysilicon layer 201 is exposed next to the fourth oxide film 205 from 1.5 mm to 2.5 mm from the wafer edge.

The fifth polysilicon layer for forming capacitor node electrodes and the buffer oxide film are sequentially formed on the entire surface of the structure including the inner wall surface of the trench and the top surface of the fourth oxide film 205. By etching, a fifth polysilicon layer sidewall spacer 208 is formed on the sidewalls of the fourth oxide film adjacent to the inside of the trench and the wafer edge to form the structure of FIG. 2C. In this case, the fifth polysilicon layer sidewall spacer 208 is formed on the top surface of the fourth polysilicon layer 201.

Subsequently, the fourth oxide film 205 and the buffer oxide film are sequentially removed to complete the wafer edge bed processing as shown in FIG. 2D. As a result, as shown in FIG. 2D, the fifth polysilicon layer sidewall spacer 208 remains undesorbed even after the removal of the fourth oxide film and the buffer oxide film. That is, the sidewall spacers remain due to the adhesive force between the fourth polysilicon layer 201 pattern remaining in the EBR region and the fifth polysilicon layer sidewall spacer 208. It is also preferable that the fourth polysilicon layer is formed of a polyside material so as to have higher adhesion to the fifth polysilicon layer sidewall spacer. Therefore, there is an effect of preventing particle contamination of the wafer.

Next, a wafer edge bed processing method according to a second embodiment of the present invention will be described.

In the wafer edge bed processing method according to the second embodiment of the present invention, the process of FIGS. 1A to 1C is performed before the process of FIG. 3A.

That is, next, a thick third oxide film 122 is formed over the entire structure structure of FIG. 1C. Next, a photoresist layer is formed on the top surface of the third oxide layer 122 and then patterned to form a photoresist pattern for forming a second storage node contact hole. At this time, the photoresist is removed up to 2.5 mm from the wafer edge. Next, the third oxide layer 122 is etched using the photoresist pattern as a mask to form a storage node contact hole, and the third oxide layer 122 is removed from the wafer edge to 2.5 mm inward. Form.

Subsequently, after forming the fourth polysilicon layer to form the storage node large plug, the entire anisotropic etching is performed to form the storage node contact plug in the second storage node contact hole, and at the same time, the third oxide layer 122 A fourth polysilicon layer sidewall spacer 124 is formed on the sidewalls. Next, a fourth oxide film 301 is formed over the entire structure on the semiconductor substrate. The fourth oxide layer is an oxide layer 301 for defining a storage node electrode of a capacitor.

After the photoresist is formed on the fourth oxide layer, the photoresist layer is patterned and the fourth oxide layer 301 is etched using the photoresist pattern to form a trench corresponding to the shape of the second storage node electrode and at the edge of the wafer. The fourth oxide film 301 up to 1.5 mm inward is etched away.

Next, a polysilicon layer for a node electrode of the capacitor, that is, a fifth polysilicon layer 303, is formed on the entire structure of FIG. 3A, and a buffer oxide film 305 is formed on the upper surface of the fifth polysilicon layer 303. do. Next, a photosensitive film 307 is formed on the buffer oxide film 305.

Preferably, the photoresist film is negative, so that only the scribe line and the EBR region are exposed to the negative photoresist, leaving the photoresist 307 only in the scribe line and the EBR region, and the photoresist in the semiconductor device manufacturing region (memory cell region) Pattern to be removed. In addition, the photoresist film is patterned to be removed from the edge of the wafer to about 1.0 mm inward to form the structure of FIG. 3B.

Next, the buffer oxide layer 305 and the fifth polysilicon layer 303 are etched using the photoresist pattern 307 as a mask, and only the fifth polysilicon layer is formed only in the storage node electrode region of the capacitor in the memory cell region. The fifth polysilicon layer 305 and the buffer oxide film 305 of the remaining portions are etched away.

Next, as shown in FIG. 3C, the buffer oxide film 305 and the fourth oxide film 301 are removed to complete the wafer edge bed processing method according to the second embodiment of the present invention. As shown in Fig. 3C, the fourth oxide film 301 in the memory cell region is removed, but in the EBR region, since the fifth polysilicon layer 303 covers the fourth oxide film 301, The sidewall spacers of the fourth oxide film 301 and the polysilicon layer are not separated from the oxide film. As a result, there is an effect of suppressing the generation of particles during the edge bed treatment process.

As described in the first and second embodiments of the present invention, by leaving the polysilicon layer for the storage node contact plug or the polysilicon layer for the storage node electrode in the EBR region and the scribe line region, It is possible to prevent the detachment of the polysilicon patterns. As a result, contamination due to particle generation during the semiconductor device manufacturing process is reduced, thereby increasing the yield of semiconductor device manufacturing.

Claims (2)

Forming a device isolation region at a predetermined portion of the semiconductor device fabrication region of the wafer and simultaneously etching the wafer by 0.5 mm from the wafer edge toward the center to form a stepped bottom; Depositing and patterning a first polysilicon layer in a semiconductor device fabrication region of a wafer to form a gate electrode and simultaneously etching away the 6 mm first polysilicon layer from an edge of the wafer; Forming a nitride film sidewall spacer on the gate electrode sidewalls; Forming the first oxide film on the entire structure obtained in the process, and then etching the first oxide film to form a first bit line contact hole and a first storage node contact hole, the first oxide film being 4 mm inward from a wafer edge inward. Etching to remove; Forming a second polysilicon layer to form the first bit line contact plug and the first storage node contact plug, and simultaneously forming a second polysilicon layer sidewall spacer on the sidewall side of the wafer edge of the first oxide layer; ; Forming and then patterning a second oxide film over the entire structure obtained in the step to form a second bit line contact hole, and simultaneously etching away the second oxide film up to 3 mm from an edge of the wafer; Forming a third polysilicon layer on the upper surface of the second oxide layer and the second bit line contact hole, and then patterning the same to form a bit line, and simultaneously etching away the third polysilicon layer to about 6 mm from a wafer edge; ; Forming and patterning a third oxide film on the resultant structure obtained in the above process, thereby forming a second storage node contact hole and etching the third oxide film from 2.5 mm inward from the edge of the wafer; Forming a fourth polysilicon layer in the second storage node contact hole to form a plug and simultaneously forming a fourth polysilicon layer sidewall spacer on the sidewall of the third oxide layer; Forming a fourth oxide film on the third oxide film, patterning the fourth oxide film to form a trench for forming a storage node electrode of the capacitor, and simultaneously removing the fourth oxide film from within the wafer edge by 1.5 mm; Forming a fifth polysilicon layer on the entire surface of the structure obtained in the process and then etching the polysilicon layer so that the polysilicon layer remains only in the trench inner wall and the EBR region; And etching the fourth oxide film. The method of claim 1, wherein the etching of the fifth polysilicon layer is performed. Forming a negative photosensitive film on the fifth polysilicon layer; Exposing and developing the negative photoresist film using a scribe line mask to form the photoresist pattern only on the scribe line and the EBR region; And etching the fifth polysilicon layer using the photosensitive film pattern as a mask.