KR100767356B1 - Thin film transistor and fabricating method thereof - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor substrate and a method for manufacturing the same. In order to cope with the wiring open problem and to improve the aperture ratio, the gate line is formed of a double line and the data line is formed of a double layer structure to obtain a redundancy effect. The electrode is superimposed on the data line to reduce the width of the black matrix blocking the pixel electrode and the data line. In detail, in the thin film transistor substrate according to the present invention, the first gate line having the first gate electrode, the second gate line having the second gate electrode and having a predetermined distance from the first gate line, and connecting the gate lines A gate line including a gate line connection part is formed and insulated from the gate line and connected to a data line and a data line defining a pixel cell region crossing the first gate line and the second gate line, the first gate A data line including a first source electrode and a second source electrode and a first drain electrode and a second drain electrode corresponding to the first source electrode and the second source electrode is formed on each of the electrode and the second gate electrode. It is. A first semiconductor layer constituting the first thin film transistor together with the first gate electrode, the first source electrode and the first drain electrode, and a second thin film transistor together with the second gate electrode, the second source electrode and the second drain electrode 2 semiconductor layers are formed, and a protective film covers data wiring, a 1st semiconductor layer, and a 2nd semiconductor layer. The protective layer is formed with a first contact hole exposing the first drain electrode and a second contact hole exposing the second drain electrode, and a second drain electrode through the first drain electrode and the second contact hole through the first contact hole. A pixel electrode connected to is formed.

Wiring open, repair, aperture ratio, redundancy, double line, double layer

Description

Thin film transistor substrate and its manufacturing method {THIN FILM TRANSISTOR AND FABRICATING METHOD THEREOF}

1 is a layout view of a thin film transistor substrate according to an embodiment of the present invention,

2 and 3 are cross-sectional views taken along cut lines II-II 'and III-III' of FIG. 1, respectively.

4A is a layout view of a thin film transistor substrate in a first step manufactured according to an embodiment of the present invention,

4B and 4C are cross-sectional views taken along cut lines IVb-IVb 'and IVc-IVc' in FIG. 4A, respectively.

FIG. 5A is a layout view of a thin film transistor substrate in the next step of FIG. 4A;

5B and 5C are cross-sectional views taken along cut lines Vb-Vb 'and Vb-Vb' in FIG. 5A, respectively.

FIG. 6A is a layout view of a thin film transistor substrate in a next step of FIG. 5A,

6B and 6C are cross-sectional views taken along cut lines VIb-VIb 'and VIc-VIc' in FIG. 6A, respectively.

7A and 7B are cross-sectional views of the substrate showing the next steps of FIGS. 6B and 6C;

FIG. 8A is a layout view of a thin film transistor substrate in a next step of FIG. 7A,                 

8B and 8C are cross-sectional views respectively taken along the cutting lines Xb-Xb 'and Xc-Xc' in FIG. 8A.

9A is a layout view of a thin film transistor substrate in the next step of FIG. 8A,

9B and 9C are cross-sectional views respectively taken along the cutting lines Xb-Xb 'and Xc-Xc' in FIG. 9A.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor substrate and a method of manufacturing the same, and more particularly, to a thin film transistor substrate used in a liquid crystal display device and a method of manufacturing the same.

In the liquid crystal display, a plurality of pixel cells are defined by crossing gate lines and data lines, and color filters corresponding to the pixel cells of the thin film transistor substrate and the lower substrate, which are lower substrates on which thin film transistors and pixel electrodes are formed, respectively, of the pixel cells. The liquid crystal material is injected between the color filter and the upper substrate on which the counter electrode corresponding to the pixel electrode is formed, and different electric potentials are applied to the pixel electrode and the counter electrode to form an electric field to change the arrangement of the liquid crystal molecules. In this way, the device expresses the image by adjusting the light transmittance.

In a general thin film transistor substrate, since the gate line and the data line are formed by a single wiring, repair is difficult in the event of a problem that an open defect occurs in the wiring. When the wiring is designed to be repairable, its design structure reduces the aperture ratio. In addition, since a black matrix must be formed in consideration of misalignment occurring in the process of bonding the thin film transistor substrate and the upper substrate thereof, a structure capable of reducing the reduction of the aperture ratio is required.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a thin film transistor substrate and a method of manufacturing the same, which can improve an opening ratio while coping with a wiring open problem.

In order to solve this problem, in the present invention, a gate line is formed as a double line, and a data line is formed as a double layer structure to obtain a redundancy effect, and the pixel electrode is overlapped with the data line to prevent the gap between the pixel electrode and the data line. Note reduces the width of the black matrix.

Specifically, in the thin film transistor substrate according to the present invention, the first gate line having the first gate electrode, the second gate line having the second gate electrode and having a predetermined distance therebetween, and connecting the gate lines A gate line including a gate line connection part is formed and insulated from the gate line and connected to a data line and a data line defining a pixel cell region crossing the first gate line and the second gate line, the first gate A data line including a first source electrode and a second source electrode and a first drain electrode and a second drain electrode corresponding to the first source electrode and the second source electrode is formed on each of the electrode and the second gate electrode. It is. A first semiconductor layer constituting the first thin film transistor together with the first gate electrode, the first source electrode and the first drain electrode, and a second thin film transistor together with the second gate electrode, the second source electrode and the second drain electrode 2 semiconductor layers are formed, and a protective film covers data wiring, a 1st semiconductor layer, and a 2nd semiconductor layer. The passivation layer has a first contact hole exposing the first drain electrode and a second contact hole exposing the second drain electrode, and is formed in the second drain electrode through the first drain electrode and the second contact hole through the first contact hole. A pixel electrode to be connected is formed.

Here, the data line may be formed in a double layer structure, wherein the data line and the data pad are formed so that the upper layer covers the lower layer, or only the first and second drain electrodes are formed so that the upper layer covers one end of the lower layer, and the other The portion may be formed in the same pattern of the upper layer and the lower layer.

The first and second semiconductor layers may be integrally connected. The semiconductor layer may be formed along the data line and the data pad, and further includes an ohmic contact layer having the same pattern as the data line between the data line and the semiconductor layer. can do.

The pixel electrode may sufficiently overlap the data line, and the passivation layer may be formed of silicon oxide or silicon nitride. In this case, an organic insulating layer may be further formed on the passivation layer to expose the contact hole formed in the passivation layer. In addition, the protective film may be formed of an organic insulating film.

And between the first and second gate lines parallel to these gate lines and not in contact with the gate line connecting portion, and corresponding to the sustain electrodes for the storage capacitors covered by the gate insulating film, and corresponding to the sustain electrodes for the storage capacitors on the insulating film. And a storage capacitor including a conductive pattern formed on the protective film and a contact hole formed in the protective film such that the pixel electrode is a passage connected to the conductive pattern for the storage capacitor. The conductor pattern may be formed of a material forming an upper layer of the data line.

The gate wiring further includes a gate pad formed at the end of the gate line connecting portion, the data wiring further includes a data pad formed at the end of the data line, the gate pad and the data pad are covered with a protective film, and the gate pad and the data pad are provided in the protective film. And includes more contact holes to expose. The display device may further include an auxiliary gate pad and an auxiliary data pad covering the gate pad and the data pad through the contact hole. In this case, the organic insulating layer may be formed to cover the pixel cell region except for the gate pad and the data pad.

The upper layer of the data line may be formed of ITO or IZO, and the pixel electrode may be formed of the same material as the upper layer of the data line.

In order to manufacture such a thin film transistor substrate, first, a first gate line having a first gate electrode on the substrate, a second gate line having a second gate electrode positioned at a predetermined distance from the first gate line, and these gates After forming a gate wiring including a gate line connecting portion connecting the lines, a gate insulating film covering the gate wiring is formed. Subsequently, the semiconductor material layer, the semiconductor material layer doped with an impurity, and the first conductive layer are successively deposited on the gate insulating layer, and then have a line portion crossing the first gate line and the second gate line by photolithography. And forming a triple layer pattern having a protrusion to overlap the second gate electrode. Subsequently, after the second conductive layer is deposited on the triple layer pattern and the gate insulating layer, the second conductive layer is photographed and intersected with the first gate line and the second gate line to be connected to a data line and a data line defining a pixel cell region. An upper data line including a first source electrode and a second source electrode positioned on each of the electrode and the second gate electrode, and a first drain electrode and a second drain electrode corresponding to the first source electrode and the second source electrode; After forming, the lower conductive data layer is formed by etching the first conductive layer of the triple layer pattern using the upper layer data wiring as a mask, and the resistive contact layer is formed by etching the semiconductor material layer doped with impurities of the triple layer pattern. Expose a portion of the material layer. After forming a protective film covering the entire surface of the substrate including the semiconductor material layer, after forming a first contact hole to expose the first drain electrode, a second contact hole to expose the second drain electrode, the first contact hole and the second A pixel electrode connected to the first drain electrode and the second drain electrode is formed through the contact hole.

Here, the gate wiring includes a gate pad connected to the gate line and receiving a scan signal from the outside and transmitting the scan signal to the gate line, and the data wiring is connected to the data line and a data pad transferring the image signal from the outside to the data line. And a contact hole formed to expose the data pad in the passivation layer and a contact hole formed to expose the gate pad in the passivation layer and the gate insulating layer, and the gate pad and the data pad through the contact holes in the same layer as the pixel electrode. And an auxiliary gate pad and an auxiliary data pad connected to each other.                     

At this time, it is preferable to form a protective film of silicon nitride or silicon oxide, and to form an organic insulating film which exposes the contact hole of the protective film on the protective film, and the protective film may be formed of an organic insulating film. The formation of the organic insulating layer may include applying the photosensitive resin to the entire surface by spin coating, and then removing the resin in the pad portion through exposure and development using an edge beam remover, or in a screen display unit in which a plurality of pixel regions are arranged. And printing the organic insulating layer.

Furthermore, a sustain electrode for sustain capacitors is further formed on the same layer of the gate wiring, and the gate insulating film covers the sustain capacitor sustain electrode, and corresponds to the sustain electrode for sustain capacitors on the gate insulation film. A capacitor conductor pattern for the capacitor is further formed, a protective film covers the conductor pattern for the storage capacitor, a contact hole for exposing the conductor pattern for the storage capacitor is formed in the protective film, and the pixel electrode is used for the storage capacitor through the contact hole. The conductor pattern for the storage capacitor may be formed of an upper layer data wiring forming material.

Next, a thin film transistor substrate and a manufacturing method thereof according to an embodiment of the present invention will be described with reference to the drawings.

1 is a layout view of a thin film transistor substrate according to an exemplary embodiment of the present invention, and FIGS. 2 and 3 are cross-sectional views illustrating the thin film transistor substrate shown in FIG. 1 along cut lines II-II 'and III-III', respectively. .

200-3000 kW made of a metal or conductor such as aluminum (Al) or aluminum alloy (Al alloy), molybdenum (Mo) or molybdenum-tungsten (MoW) alloy, chromium (Cr), tantalum (Ta), etc. on the insulating substrate 10 Gate wirings 21, 22, 23, 24, 25, and 26 having a thickness and a storage electrode 27 for a storage capacitor are formed.

The gate wirings 21, 22, 23, 24, 25, and 26 have the first gate electrode 25 and the first gate line 21 and the second gate electrode 26 extending in the horizontal direction in the horizontal direction. A second gate line 22 extending in parallel with the first gate line 21 at predetermined intervals, and a gate line connecting portion 23 and a gate line connecting the gate lines 21 and 22 to one; The gate pad 24 is connected to the end of the connecting portion 23.

The storage electrode 27 for the storage capacitor is positioned in parallel with the gate lines 21 and 22 between the first gate line 21 and the second gate line 22, and is not in contact with the gate line connecting portion 23. It is formed so as not to.

The storage electrode 27 for the storage capacitor overlaps with the conductive pattern 67 for the storage capacitor connected to the pixel electrode 91 to be described later to form a storage capacitor to improve charge storage capability of the pixel. It may not be formed when the storage capacitance generated by the overlap of the gate lines 21 and 22 is sufficient.

The gate wirings 21, 22, 23, 24, 25, and 26 may be formed in a single layer as shown in the drawing, but may also be formed in a double layer or a triple layer. In the case of forming more than two layers, it is preferable that one layer is made of a material having a low resistance and the other layer is made of a material having good contact properties with other materials, especially ITO or IZO, which is used as a pixel electrode. In the case where the pixel electrode is formed of ITO, materials having good contact properties with ITO include chromium (Cr), molybdenum (Mo), titanium (Ti), tantalum (Ta), and the like, and Al＼Cr (or Al alloy). Examples thereof include a double layer of or a double layer of Al＼Mo.

Since the gate line in the present invention is formed of a double line, the redundancy effect can be obtained. When a defect occurs in which one gate line is opened, the gate signal may be transmitted to the other gate line, and thus, there is no need to perform a separate repair operation or design a wiring structure for the repair.

As described above, the present invention is advantageous in preparing a gate line open defect as compared to a thin film transistor substrate employing a single gate line.

On the substrate 10, a gate insulating film 30 having a thickness of 1500 to 4000 μs made of an insulating material such as silicon nitride or silicon oxide is formed on the gate wirings 21, 22, 23, 24, 25, and 26 and the storage electrode 27 for the storage capacitor. )

On the gate insulating film 30, a semiconductor layer 41 having a thickness of 800 to 1500 Å made of a semiconductor material such as hydrogenated amorphous silicon is formed.

The semiconductor layer 41 not only covers the first gate electrode 25 portion of the first gate line 21 and the second gate electrode 26 portion of the second gate line 22 but also the data line (to be described later) 71 and the data pad 72, and extend in the vertical direction to intersect the first gate line 21 and the second gate line 22. As shown in FIG.

On the semiconductor layer 41, a lower wiring 601 having a thickness of 1500 to 2500 Å made of a conductive material such as chromium or chromium alloy, molybdenum or molybdenum alloy, aluminum alloy such as aluminum-neodymium (Al-Nd) alloy, and chromium or chromium Double-layer data wiring 61, 62, 63, 64, 65, 66 consisting of a 500-1500 Å thick upper wiring 602 made of a conductive material such as an alloy, molybdenum or molybdenum alloy, or a transparent conductive material such as ITO or IZO. ) Is formed.

The data lines 61, 62, 63, 64, 65, and 66 extend in the vertical direction to intersect the first gate line 21 and the second gate line 22 to define the pixel region, and the data. The data pad 62 connected to the end of the line 61, the first source electrode 63 and the first source protruding from the data line 61 and positioned on the first gate electrode 25 to constitute the first thin film transistor. A first drain electrode 65 corresponding to the electrode 63, a second source electrode 64 which also protrudes from the data line 61 and is positioned on the second gate electrode 26 to form a second thin film transistor; And a second drain electrode 66 corresponding to the second source electrode 64.

At this time, the data line 61 and the data pad 62 have a width wider than that of the lower layer 601 so that the upper layer 602 sufficiently covers the lower layer 601 so that the upper layer 602 can sufficiently cover the lower layer 601. It may be formed to have. In the first drain electrode 65 and the second drain electrode 66, the lower layer 601 is disposed only on the semiconductor layer 41, and the upper layer 602 covers one end of the lower layer 601 to protrude into the pixel region. It is formed to be. In the figure, the pattern for the lower layer 601 of the data lines 61, 62, 63, 64, 65, and 66 is not shown, and only the pattern for the upper layer 602 is shown. Alternatively, the data line 61 and the data pad 62 may be formed such that the upper layer 602 and the lower layer 601 have the same width.

As described above, since the data line is formed in a double layer structure, the redundancy effect can be obtained. Therefore, it is not necessary to perform a separate repair operation to prepare for a data wiring open failure, and there is no need for a separate wiring formation for a repair.

In addition, in the exemplary embodiment of the present invention, since two thin film transistors exist in one pixel region, it is easy to charge the pixel region in a large display device and to facilitate the repair of defects in adjacent pixel regions. There is this.

In addition, the conductive capacitor conductor 67 for the storage capacitor is formed on the gate insulating film 30 at a portion corresponding to the storage electrode 27 for the storage capacitor.

On the other hand, between the semiconductor layer 41 and the lower layer 601 of the data wirings 61, 62, 63, 64, 65, and 66 in contact therewith, a resistive contact layer having a thickness of 500 to 800 Å made of hydrogenated amorphous silicon doped with impurities. (51, 52, 53) are interposed.

In addition, a protective film 70 having a thickness of 500 to 1000 GPa made of an insulating material such as silicon nitride or silicon oxide is used to expose the data lines 61, 62, 63, 64, 65, 66, the exposed portion of the semiconductor layer 41, and the storage capacitor. The storage sustain electrode 67 is covered.

On the passivation layer 70, an organic insulating layer 90 having a thickness of 2.5 μm to 3.0 μm is formed of an organic insulating material such as BCB, acryl series, or thermosetting resin. In this case, the organic insulating layer 90 may be formed only in a display area in which a plurality of pixel areas in which a screen is displayed are arranged except for a pad part in which the data pad 62 and the gate pad 24 are located.

The protective film 70 and the organic insulating film 80 have a first contact hole 71 exposing the first drain electrode 65, a second contact hole 72 exposing the second drain electrode 66, and a conductor for a storage capacitor. A third contact hole 73 exposing the pattern 67 is formed. In the passivation layer 70, a fourth contact hole 74 exposing the data pad 62 is formed, and a fifth contact hole 75 exposing the gate pad 24 is formed together with the gate insulating layer 30. have.

On the organic insulating layer 80, the first drain electrode 65, the second drain electrode 55, and the storage medium are formed through the first contact hole 71, the second contact hole 72, and the third contact hole 73. The pixel electrode 91 which is simultaneously connected to the conductor pattern 67 for a capacitor is formed.

The pixel electrode 91 is connected to the conductor pattern 67 for the storage capacitor to transmit an image signal to the conductor pattern 67. In the conventional case, the storage electrode 27 for the storage capacitor overlaps the pixel electrode 91 to form a storage capacitor. However, as shown in the drawing, the storage capacitor conductor is disposed between the storage electrode 27 and the pixel electrode 91. When the pattern 77 is interposed, since the thickness of the dielectric film interposed between the two conductive layers becomes thinner, there is an advantage in that the holding capacitance can be increased by that much.

On the other hand, in the present invention, since the organic insulating film 80 having a low dielectric constant is formed thick between the pixel electrode 91 and the data line 61, the overlap between the pixel electrode 91 and the data line 61 is caused. Parasitic capacity is not large. Accordingly, the pixel electrode 91 may be formed to overlap the data line 61, thereby reducing the width of the black matrix for preventing light leakage between the pixel electrode 91 and the data line 61. It is possible to improve the aperture ratio.

In addition, in the same layer as the pixel electrode 91, the auxiliary data pad 92 covering the data pad 62 through the fourth contact hole 74 and the gate pad 75 through the fifth contact hole 75 are covered. An auxiliary gate pad 93 is formed.

In the embodiment of the present invention, the case where the protective film 70 and the organic insulating film 80 are formed together is taken as an example. However, the organic insulating film 80 is formed without the protective film 70 being formed, and the organic insulating film 80 is formed. It is also possible to propose a structure in which contact holes 71, 72, 73, 74, and 75 are formed at.

Next, a method of manufacturing a substrate for a liquid crystal display according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 4A to 13C.

First, as shown in FIGS. 4A, 4B, and 4C, aluminum (Al) or aluminum alloy, molybdenum (Mo), or molybdenum-tungsten (MoW) alloy, and chromium (Cr) are disposed on the insulating substrate 10. And depositing a metal layer such as tantalum (Ta) by a method such as sputtering and dry or wet etching using a mask to form the gate wirings 21, 22, 23, 24, 25, and 26 and the storage electrode 27 for the storage capacitor. To form.

The gate wirings 21, 22, 23, 24, 25, and 26 have the first gate electrode 25 and the first gate line 21 and the second gate electrode 26 extending in the horizontal direction in the horizontal direction. A second gate line 22 extending in parallel with the first gate line 21 at predetermined intervals, and a gate line connecting portion 23 and a gate line connecting the gate lines 21 and 22 to one; And a gate pad 24 connected to the end of the connection portion 23.

Next, as shown in FIGS. 5A, 5B, and 5C, a gate insulating film 30 made of an insulating material such as silicon nitride or silicon oxide, a semiconductor layer made of hydrogenated amorphous silicon, or a hydrogenated amorphous silicon doped with impurities The semiconductor layer doped with the impurity formed was continuously deposited to a thickness of 2,500 to 4,000 Å, 800 to 1500 Å, and 500 to 800 각각 by chemical vapor deposition, followed by chromium or chromium alloy, molybdenum or molybdenum alloy, and aluminum-neodymium. The first conductor layer 601 made of a conductive material such as aluminum alloy (Al-Nd) is deposited to a thickness of 1,500 kPa to 3,000 kPa by a method such as sputtering.

Subsequently, the first conductor layer, the semiconductor layer doped with impurities, and the semiconductor layer are photo-etched to cross the first and second gate lines 21 and 22 and extend in the vertical direction, and the first and second gate electrodes 25 are formed. , To form a triple layer pattern 300 protruding in the horizontal direction so as to overlap the 26.

At this time, the semiconductor layer located at the lowermost layer of the triple layer pattern 300 becomes the semiconductor pattern 41 of the thin film transistor substrate and is completed in this step.

The first conductor layer 601, which is the uppermost layer in the triple layer pattern 300, becomes the lower layer wiring 601 of the double layer data wirings 61, 62, 63, 64, 65, and 66 in the process described later. Compared with the completed pattern of, it has the same shape as the data line and the data pad, except that the source electrode and the drain electrode are not separated and are integrally formed.

The semiconductor layer 50 doped with intermediate impurities in the triple layer pattern 300 becomes an ohmic contact layer through a subsequent process and has the same pattern as the first conductor layer 601.

Next, as shown in Figs. 6a, 6b and 6c, after depositing a second conductive layer made of a conductive material such as chromium or chromium alloy, molybdenum or molybdenum alloy, or a transparent conductive material such as IZO or ITO by sputtering The upper layer wiring 602 of the data wirings 61, 62, 63, 64, 65, and 66 and the conductive capacitor pattern 67 for the storage capacitor are formed by patterning by a photolithography process using a mask.

The upper layer wiring 602 of the data wirings 61, 62, 63, 64, 65, and 66 may include a data line 61, a data pad 62, a first source electrode 63, a first drain electrode 65, An upper layer of the second source electrode 64 and the second drain electrode 66 is formed. At this time, one end of the upper layer 602 of the first drain electrode 65 and the second drain electrode 66 is formed in contact with the triple layer pattern 300, and the other end thereof is formed to protrude into the pixel region.

At this time, as shown in the figure so that the upper layer wiring 602 covers the lower layer wiring 601 in the data line 61 and the data pad 62, the width of the upper layer wiring 602 is lower than that of the lower layer wiring 601. It is desirable to pattern larger than the width.

The capacitor pattern 67 for the storage capacitor is formed on the gate insulating film 30 on the storage electrode 27 for the storage capacitor.

 Next, as shown in FIGS. 7A and 7B, the upper conductive lines 602 of the data lines 61, 62, 63, 64, 65, and 66 are used as masks to form the first conductive layer of the triple layer pattern 300 at the bottom thereof. The layer 601 and the semiconductor layer 50 doped with impurities are etched.

In this process, the first source layer 63 and the first drain electrode 65, which were integrally formed with the first conductive layer 601 of the triple layer pattern 300, are separated. Likewise, the second source electrode 64 may be separated. And the second drain electrode 66 are separated to become the lower wiring 601 of the data wirings 61, 62, 63, 64, 65, 66. The lower wiring 601 of the data wiring includes a data line 61, a data pad 62, a first source electrode 63, a first drain electrode 65, a second source electrode 64, and a second drain electrode ( 66).

In the completed data wirings 61, 62, 63, 64, 64, 65, 66, the pattern of the data lines 61 and the data pads 62 is formed so that the upper layer 602 sufficiently covers the lower layer 601. It is advantageous to pattern so that the width of 602 is wider than the width of lower layer 601.

In the first and second drain electrodes 65 and 66, since the lower layer 602 is formed by etching a triple layer pattern, the lower layer 602 is disposed on the semiconductor layer 41 with a width smaller than that of the upper layer 601.

In this process, the semiconductor layer 50 doped with impurities is also etched in the same shape as the lower layer 601 of the data lines 61, 62, 63, 64, 65, and 66 to form the ohmic contact layers 51, 52, and 53. ) The ohmic contact layer 51 contacts the data line 61, the data pad 61, the first source electrode 63, and the lower layer 601 of the second source electrode 64, and the ohmic contact layer 52 is formed on the ohmic contact layer 52. The lower layer 601 of the first drain electrode 65 is contacted, and the ohmic contact layer 53 is in contact with the lower layer 601 of the second drain electrode 66.

Next, as shown in FIGS. 8A, 8B, and 8C, an insulating material such as silicon nitride or silicon oxide covering the data wirings 61, 62, 63, 64, 65, 66, and the conductive pattern 67 for the storage capacitor is next. A protective film 70 is formed.

Subsequently, the first contact hole 71 and the upper layer 602 of the second drain electrode 66, which expose the upper layer 602 of the first drain electrode 65, are exposed to the passivation layer 70 by a photolithography process using a mask. A fourth contact hole 74 is formed which exposes the exposed second contact hole 72, the third contact hole 73 which exposes the conductor pattern 67 for the holding capacitor, and the upper layer 602 of the data pad 62. The fifth contact hole 75 exposing the gate pad 24 is formed together with the gate insulating film 30.

Next, an organic insulating layer 80 having a low dielectric constant and excellent planarization characteristics is formed on the passivation layer 70. In this case, the organic insulating layer 80 is formed to be removed from the pad portion, and then patterned to expose the first and second contact holes 71 and 72 exposing the first and second drain electrodes 65 and 66. Can be.

In forming the organic insulating film 80 in the present invention, first, a photosensitive resin is applied to the entire surface of the substrate by spin coating, followed by exposure and development using an edge beam remover or the like. There is a method of removing only the organic insulating film 80 of the pads 24 and 62 through the process, and second, a method of printing the organic insulating film 80 only on the screen display unit in which a plurality of pixel areas are arranged.

As described above, the process of forming the protective film 70, forming the first and second contact holes 71 and 72, and then forming the organic insulating film 80 has been presented. 70 and the organic insulating film 80 are sequentially formed, and then the organic insulating film 80 and the protective film 70 are sequentially etched to form the first and second contact holes 71 and 72 and the other contact holes 73 and 74. , 75). In addition, the process of forming the protective film 70 may be abbreviate | omitted and only the organic insulating film 80 may be formed in a board | substrate.

Next, as illustrated in FIGS. 9A, 9B, and 9C, IZO or ITO may be stacked and a photolithography process using a mask may be performed to pass through the first, second, and third contact holes 71, 72, and 73. A pixel electrode 91 connected to the upper layer 602 of the first drain electrode 65, the upper layer 602 of the second drain electrode 66, and the conductive pattern 67 for the storage capacitor is formed, and at the same time, a fourth And an auxiliary data pad 92 and an auxiliary gate pad 93 connected to the upper layer 602 of the data pad 62 and the gate pad 24 through the fifth contact holes 74 and 75, respectively.

In this case, when the upper layer 602 of the first and second drain electrodes 65 and 66 and the storage capacitor conductor pattern 67 contacting the pixel electrode 91 are formed of a transparent conductive material such as ITO or IZO. In this case, since the contact structure of the two layers is ITO＼ITO or IZO＼IZO, the contact resistance with the pixel electrode 91 can be sufficiently lowered.

In this case, the pixel electrode 91 may be formed to overlap the data line 61. In this case, the width of the black matrix for blocking the light leakage area between the pixel electrode 91 and the data line 61 may be set. It can be reduced, and the aperture ratio can be improved.

As described above, in the present invention, the gate line may be formed as a double line to prevent wiring defects due to the opening of the gate line, and the high opening ratio may be secured because a separate repair structure is not required. In addition, since the data lines are formed in a double layer, data open failure can be prevented and a high opening ratio can be secured because a separate repair structure is not required. In addition, since the pixel electrode can be superimposed on the data line, the width of the black matrix which prevents light leakage between the pixel electrode and the data line can be reduced, thereby ensuring a high opening ratio.

Claims (24)

A gate pad formed on the substrate, First and second gate lines branching from the gate pad, A data line insulated from and intersecting the first gate line and the second gate line, A first thin film transistor connected to the first gate line and the data line, A second thin film transistor connected to the second gate line and the data line; A pixel electrode connected to the first and second thin film transistors Including, And the data line has a double layer structure. delete The method of claim 1, And the data line is formed such that an upper layer covers a lower layer. The method of claim 1, The first and second thin film transistors may include first and second gate electrodes connected to the first and second gate lines, respectively. First and second semiconductor layers respectively overlapping the first and second gate electrodes, First and second source electrodes connected to the data lines and overlapping the first semiconductor layer and the second semiconductor layer, respectively; First and second drain electrodes overlapping the first and second semiconductor layers and facing the first and second source electrodes, respectively; The first and second drain electrodes have a double layer structure, and an upper layer is formed to cover one end of a lower layer. The method of claim 4, wherein And the first and second semiconductor layers are integrally connected. The method of claim 5, The thin film transistor substrate of claim 1, wherein the first and second semiconductor layers are integrally formed along the data line. The method of claim 6, And a resistive contact layer having the same pattern as the data line and the drain electrode, between the data line and the drain electrode and the first and second semiconductor layers. The method of claim 1, The thin film transistor substrate of which the pixel electrode overlaps the data line. The method of claim 1, The semiconductor device may further include a passivation layer formed between the first and second thin film transistors and the pixel electrode. The passivation layer is a thin film transistor substrate formed of silicon oxide or silicon nitride. delete The method of claim 1, The semiconductor device may further include a passivation layer formed between the first and second thin film transistors and the pixel electrode. The protective film is a thin film transistor substrate is an organic insulating film. The method of claim 1, Parallel to these gate lines between the first and second gate lines, A storage electrode for a storage capacitor formed separately from the gate line; And a conductive capacitor conductor pattern overlapping the storage electrode for the storage capacitor and the insulating layer therebetween, And the conductive pattern for the storage capacitor is electrically connected to the pixel electrode. The method of claim 12, The conductive capacitor pattern for the storage capacitor is formed of a material forming an upper layer of the data line. The method of claim 9 or 11, Is formed on the protective film, And a second gate pad connected to the gate pad through a contact hole formed in the passivation layer. delete According to claim 1, The thin film transistor substrate of which the upper layer of the data line and the pixel electrode are formed of ITO or IZO. Forming a gate pad and first and second gate lines protruding from the gate pad on a substrate, Forming a gate insulating layer covering the gate pad and the first and second gate lines; A semiconductor material layer, a semiconductor material layer doped with an impurity, and a first conductive layer are successively deposited on the gate insulating layer, and then line-etched to cross the first gate line and the second gate line by photolithography, and the first gate Forming a triple layer pattern having a protrusion so as to overlap the electrode and the second gate electrode, After depositing a second conductive layer on the triple layer pattern and the gate insulating layer, a photo line is formed to cross the first gate line and the second gate line to define a pixel cell region, the data line being connected to the data line. A first source electrode and a second source electrode positioned on each of the first gate electrode and the second gate electrode, and a first drain electrode and a second drain electrode corresponding to the first source electrode and the second source electrode; Forming an upper data line; Etching the first conductive layer of the triple layer pattern using the upper data wiring as a mask to form a lower data wiring; The resistive contact layer is formed by etching the semiconductor material layer doped with impurities of the triple layer pattern using the lower data wiring as a mask until the semiconductor material layer is exposed. Forming a protective film covering an entire surface of the substrate including the semiconductor material layer, Forming a first contact hole exposing the first drain electrode and a second contact hole exposing the second drain electrode in the passivation layer, Forming a pixel electrode connected to the first drain electrode and the second drain electrode through the first contact hole and the second contact hole; Method of manufacturing a thin film transistor substrate comprising a. The method of claim 17, The upper layer and the lower layer data lines are connected to the data line and include a data pad receiving an image signal from the outside and transferring the image signal to the data line. Further forming a third contact hole formed in the passivation layer to expose the data pad and a fourth contact hole formed in the passivation layer and the gate insulating layer to expose the gate pad, And forming an auxiliary gate pad and an auxiliary data pad connected to the gate pad and the data pad through the third and fourth contact holes in the same layer as the pixel electrode. The method of claim 18, The protective film is formed of silicon nitride or silicon oxide, And forming an organic insulating layer on the passivation layer to expose the first to fourth contact holes of the passivation layer. The method of claim 18, And the protective film is formed of an organic insulating film. The method according to claim 19 or 20, The formation of the organic insulating layer may include applying a photosensitive resin to the entire surface by spin coating, and then removing the resin of the gate pad and the data pad portion through exposure and development using an edge beam remover. Manufacturing method. The method of claim 19, The forming of the organic insulating layer may include printing the organic insulating layer only on a screen display unit in which a plurality of pixel regions are arranged. The method of claim 17, A sustain electrode for a storage capacitor is further formed between the first gate line and the second gate line on the same layer of the gate line; The gate insulating film covers the storage electrode for the storage capacitor, A capacitor pattern is further formed on a portion of the gate insulating layer corresponding to the storage electrode for the storage capacitor, The protective film covers the conductive pattern for the storage capacitor, Forming a fifth contact hole in the protective film that exposes the conductive pattern for the storage capacitor; And manufacturing the thin film transistor substrate to connect the pixel electrode to the conductive pattern conductor for the storage capacitor through the fifth contact hole. 24. The method of manufacturing a thin film transistor substrate according to claim 23, wherein the conductor pattern for capacitor is formed of the upper data wiring formation material.

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