KR100763759B1 - Connecting method of power metal line in semiconductor devices - Google Patents
Connecting method of power metal line in semiconductor devices Download PDFInfo
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- KR100763759B1 KR100763759B1 KR1020010075537A KR20010075537A KR100763759B1 KR 100763759 B1 KR100763759 B1 KR 100763759B1 KR 1020010075537 A KR1020010075537 A KR 1020010075537A KR 20010075537 A KR20010075537 A KR 20010075537A KR 100763759 B1 KR100763759 B1 KR 100763759B1
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- 239000002184 metal Substances 0.000 title claims abstract description 51
- 239000004065 semiconductor Substances 0.000 title claims abstract description 11
- 238000000034 method Methods 0.000 title claims abstract description 9
- 239000011229 interlayer Substances 0.000 claims abstract description 35
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 34
- 239000010410 layer Substances 0.000 claims abstract description 26
- 239000004020 conductor Substances 0.000 claims abstract description 8
- 238000005530 etching Methods 0.000 claims abstract description 7
- 238000000151 deposition Methods 0.000 claims abstract description 5
- 238000004519 manufacturing process Methods 0.000 abstract description 2
- 239000012212 insulator Substances 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 238000001000 micrograph Methods 0.000 description 2
- 238000013016 damping Methods 0.000 description 1
- 230000018109 developmental process Effects 0.000 description 1
- 230000012447 hatching Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5226—Via connections in a multilevel interconnection structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
- H01L21/0274—Photolithographic processes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
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Abstract
반도체 소자 제조 공정에서 다층의 전력을 공급하는 금속선을 서로 연결하는 방법에 관한 것으로, 그 목적은, 전력금속선 연결용 홀 내에서 발생하는 저항을 최소화하는 데 있다. 이를 위해 본 발명에서는, 하층의 전력금속선 상에 층간 절연막을 증착하고 층간 절연막 상부에 감광막을 도포하는 단계, 감광막 상에 다수의 홀이 형성된 레티클 또는 마스크를 위치시키고 임계시간 이상으로 노광한 후 현상함으로써 홀 패턴이 서로 연결된 감광막 패턴을 형성하는 단계, 감광막 패턴을 마스크로 층간절연막을 식각하여 하층의 전력금속선을 노출시키는 단계, 감광막 패턴을 제거하고 층간 절연막의 식각된 부분을 도전성 물질로 충진하는 단계를 순차적으로 수행함으로써, 상층의 전력금속선과 하층의 전력금속선 사이부분에 원기둥 형상의 층간절연막을 형성하고 원기둥 층간절연막을 제외한 나머지 부분에 도전성 물질을 형성한다.The present invention relates to a method of connecting metal wires for supplying multilayer power to each other in a semiconductor device manufacturing process, and an object thereof is to minimize resistance generated in a hole for power metal wire connection. To this end, in the present invention, by depositing an interlayer insulating film on the power metal line of the lower layer and applying a photoresist film on the interlayer insulating film, by placing a reticle or mask formed with a plurality of holes on the photoresist film and exposed after a threshold time or more, Forming a photoresist pattern in which the hole patterns are connected to each other, etching the interlayer insulating layer using the photoresist pattern as a mask to expose a lower power metal line, removing the photoresist pattern, and filling the etched portion of the interlayer insulating layer with a conductive material By sequentially performing, a cylindrical interlayer insulating film is formed between the upper power metal wire and the lower power metal wire, and a conductive material is formed in the remaining portions except the cylindrical interlayer insulating film.
전력금속선, 홀, overetching Power metal wire, hall, overetching
Description
도 1은 종래 방법에서 감광막 패턴 형성 이후 형성된 전력금속선 연결용 홀을 관측한 현미경 사진이다. 1 is a photomicrograph of observing a hole for power metal wire connection formed after the photosensitive film pattern is formed in the conventional method.
도 2a 및 도 2b는 본 발명에 따라 각각 층간 절연막의 식각 전과 식각 후의 전력금속선 연결용 홀을 도시한 모식도이다.2A and 2B are schematic views illustrating holes for connecting power metal lines before and after etching of an interlayer insulating layer, respectively, according to the present invention.
도 3a는 본 발명에 따라 형성된 전력금속선 연결용 홀을 관측한 현미경 사진이며, 도 3b는 도 3a를 확대한 사진이다.Figure 3a is a micrograph observing the hole for power metal wire connection formed in accordance with the present invention, Figure 3b is an enlarged photo of Figure 3a.
본 발명은 반도체 제조 방법에 관한 것으로, 더욱 상세하게는 다층 금속에서 각 금속 층간에 전력을 공급하는 전력금속선(power matal line)을 연결하는 방법에 관한 것이다.BACKGROUND OF THE
일반적으로 반도체 소자는 반도체 기판 상에 다수의 금속층 및 절연체층이 적층되어 이루어져 있으며, 하부의 금속층 및 상부의 금속층에는 컨택홀(contact hole) 또는 비아홀(via hole) 등이 형성되고, 홀의 내부는 도전성 물질로 충진됨으 로써 상부 및 하부의 금속층이 서로 연결된다.In general, a semiconductor device includes a plurality of metal layers and insulator layers stacked on a semiconductor substrate, and contact holes or via holes are formed in the lower metal layer and the upper metal layer, and the inside of the hole is conductive. Filling the material connects the upper and lower metal layers to each other.
반도체 소자에 전력을 공급하는 전력금속선 역시 상층의 전력금속선 및 하층의 전력금속선 간에 형성된 연결 홀을 통해, 다른 높이에 형성된 트랜지스터와 같은 반도체 소자에 전력을 공급하게 된다.The power metal wire for supplying power to the semiconductor device also supplies power to semiconductor devices such as transistors formed at different heights through connection holes formed between the upper power metal wire and the lower power metal wire.
종래에는 전력금속선 연결용 홀을 일반적인 컨택홀 또는 비아홀 형성과 동일한 방법으로 사진식각하여 형성한다.Conventionally, the power metal wire connection hole is formed by photolithography in the same manner as the general contact hole or via hole formation.
도 1은 종래 방법에서 감광막 패턴 형성 이후 형성된 전력금속선 연결용 홀을 관측한 현미경 사진으로서, 하부 전력 금속선의 상부의 층간 절연막을 증착하고 층간 절연막 상부에 감광막을 도포한 후 전력금속선 연결용 홀 형성을 위한 마스크 패턴을 통해 감광막을 노광 현상한 후의 상면을 도시한 것이다. 이에 도시된 바와 같이, 각각의 전력금속선 연결용 홀(1)은 층간절연막에 의해 격리되도록 독립적으로 형성되어 있으며, 홀(1)의 주변에는 감광막 슬롭(slop)(2)이 남아있다.1 is a microscope photograph of a power metal wire connection hole formed after the formation of the photosensitive film pattern according to the conventional method. The hole is formed by depositing an interlayer insulating film on the upper portion of the lower power metal line and applying a photosensitive film on the interlayer insulating film. The upper surface after exposing and developing a photosensitive film | membrane through the mask pattern for the figure is shown. As shown in the drawing, each power metal
이러한 상태에서 전력금속선 연결선 홀을 형성하기 위해 감광막 패턴을 통해 드러난 층간 절연막을 식각할 경우 감광막의 습롭에 의해 인접하는 홀 패턴이 서로 연결되거나 위치에 따라 홀 패턴의 사이즈(size)가 달라지게 되므로 다수의 홀 패턴이 높은 밀도로 형성된 전력금속선 연결 영역에서의 균일도가 불량하게 된다.In this state, when the interlayer insulating layer exposed through the photoresist pattern is etched to form the power metal wire connecting hole, adjacent hole patterns are connected to each other due to the damping of the photoresist, or the size of the hole pattern varies depending on the position. The uniformity in the power metal line connection region where the hole pattern is formed at a high density becomes poor.
또한 이와 같은 종래의 전력금속선 연결용 홀에서는 홀 내에서 발생하는 저항이 불가피하므로, 이로 인한 전력의 손실을 최소화할 필요가 있다.In addition, since the resistance generated in the hole is inevitable in the conventional power metal wire connection hole, it is necessary to minimize the loss of power.
본 발명은 상기한 바와 같은 문제점을 해결하기 위한 것으로, 그 목적은 전 력금속선 연결용 홀 내에서 발생하는 저항을 최소화하는 데 있다. The present invention is to solve the above problems, the object is to minimize the resistance generated in the hole for power metal wire connection.
상기한 바와 같은 목적을 달성하기 위하여, 본 발명에서는 하층의 전력금속선 상에 층간 절연막을 증착하고 층간 절연막 상부에 감광막을 도포하는 단계, 감광막 상에 다수의 홀이 형성된 레티클 또는 마스크를 위치시키고 임계시간 이상으로 노광한 후 현상함으로써 홀 패턴이 서로 연결된 감광막 패턴을 형성하는 단계, 감광막 패턴을 마스크로 층간절연막을 식각하여 하층의 전력금속선을 노출시키는 단계, 감광막 패턴을 제거하고 층간 절연막의 식각된 부분을 도전성 물질로 충진하는 단계를 순차적으로 수행함으로써, 상층의 전력금속선과 하층의 전력금속선 사이부분에 원기둥 형상의 층간절연막을 형성하고 원기둥 층간절연막을 제외한 나머지 부분에 도전성 물질을 형성한다.In order to achieve the object as described above, in the present invention, the step of depositing an interlayer insulating film on the power metal line of the lower layer and applying a photoresist film on top of the interlayer insulating film, placing a reticle or mask formed with a plurality of holes on the photoresist film and the threshold time Forming a photoresist pattern in which the hole patterns are connected to each other by exposing and developing the photoresist layer; etching the interlayer insulating layer using the photoresist pattern as a mask to expose the power metal line in the lower layer; removing the photoresist pattern and removing the etched portion of the interlayer insulating layer. By sequentially filling the conductive material, a cylindrical interlayer insulating film is formed between the upper power metal wire and the lower power metal wire, and a conductive material is formed in the remaining portions except the cylindrical interlayer insulating film.
이하, 본 발명에 따른 반도체 소자의 전력금속선 연결 방법에 대해 상세히 설명한다.Hereinafter, a method of connecting power metal lines of a semiconductor device according to the present invention will be described in detail.
먼저, 하층의 전력금속선 상부에 상층의 전력금속선과의 전기적 절연을 위한 층간 절연막을 증착한 후 층간 절연막 상부에 감광막을 도포한다. 그리고, 감광막의 상부에 다수의 홀 패턴이 형성된 레티클(reticle) 또는 마스크를 위치시키고, 그 레티클 또는 마스크를 통해 감광막을 노광함으로써 레티클 또는 마스크에 형성된 홀 패턴을 감광막에 전사시킨다. 그리고, 홀 패턴이 전사된 감광막을 현상함으로써 층간 절연막 상부에 전력금속선 연결용 홀 형성을 위한 감광막 패턴을 형성한다. First, an interlayer insulating film is deposited on the lower power metal wire to electrically insulate the upper power metal wire, and then a photosensitive film is coated on the interlayer insulating film. Then, a reticle or mask on which a plurality of hole patterns are formed is placed on the photoresist film, and the hole pattern formed on the reticle or mask is transferred to the photoresist film by exposing the photoresist film through the reticle or mask. The photoresist film on which the hole pattern is transferred is developed to form a photoresist pattern for forming a power metal wire connection hole on the interlayer insulating film.
감광막의 노광시에는 임계시간보다 긴 시간동안 노광함으로써 감광막의 현상시 형성되는 감광막 패턴 상의 각각의 홀이 서로 연결되도록 한다. 이 때 임계시간이란, 홀의 경계 부분인 이웃하는 홀 사이의 최근접 거리가 현상되어 홀들이 서로 연결되어 버리는 노광시간을 가리킨다.When the photosensitive film is exposed, the exposure is performed for a time longer than the threshold time so that the respective holes on the photosensitive film pattern formed during the development of the photosensitive film are connected to each other. At this time, the critical time refers to an exposure time when the closest distance between neighboring holes, which are boundary portions of the holes, is developed and the holes are connected to each other.
일반적으로 전력금속선 연결용 홀은 밀도가 매우 높아서 보통 홀 간의 거리가 150 nm 이하로 작으므로 임계시간 이상의 노광에 의해 현상시 감광막 상의 홀 패턴이 서로 연결되기가 쉽다. 도 2a 및 도 2b는 본 발명에 따라 각각 층간 절연막의 식각 전과 식각 후의 전력금속선 연결용 홀을 도시한 모식도이다. 이들 도면에 도시된 바와 같이, 임계시간 이상의 노광에 의해 형성된 감광막 패턴을 통해 층간 절연막을 식각하면 홀(10)을 통해 노출되는 부분 뿐만 아니라 홀(10)의 경계 부분 역시 식각되며, 도 2a에는 식각되는 영역을 빗금으로 표시하였다. 이로 인해 홀이 서로 연결되는 것이 가능하다.In general, since the holes for power metal wire connection have a very high density, the distance between the holes is usually 150 nm or less, so that the hole patterns on the photosensitive film are easily connected to each other when developed by exposure over a critical time. 2A and 2B are schematic views illustrating holes for connecting power metal lines before and after etching of an interlayer insulating layer, respectively, according to the present invention. As shown in these figures, when the interlayer insulating film is etched through the photoresist pattern formed by the exposure of the threshold time or more, not only the portion exposed through the
임계시간 이상의 노광에 의해 감광막 패턴을 형성하는 방법 외에, 홀 크기가 확대된 레티클 또는 마스크를 사용하여 층간 절연막 상부의 감광막을 노광 현상함으로써 동일한 효과를 얻을 수도 있는데, 이에 대한 설명은 다음과 같다. In addition to the method of forming the photoresist pattern by exposure over the critical time, the same effect may be obtained by exposing and developing the photoresist on the interlayer insulation layer using a reticle or mask having an enlarged hole size.
레티클 또는 마스크에서 홀 간의 거리가 일정할 때, 홀의 크기가 어떤 값 이상으로 커지면 노광 후 형성된 감광막 패턴에서 독립된 홀을 얻지 못하고 홀의 경계 부분이 현상되어 홀들이 서로 연결되는데, 이 때 그 값을 홀 크기의 임계값이라고 정의한다. 그러면, 레티클 또는 마스크에서 임계값 이상의 크기를 가지도록 홀 패턴을 형성하고, 이러한 레티클을 사용하여 노광하면 결과적으로 형성되는 감광막 패턴에서는 홀들이 서로 연결되는 것이다.When the distance between holes in a reticle or mask is constant, if the size of the hole becomes larger than a certain value, the independent hole is not obtained in the photoresist pattern formed after exposure, and the hole boundary is developed so that the holes are connected to each other. It is defined as the threshold of. Then, the hole pattern is formed to have a size greater than or equal to a threshold value in the reticle or mask, and the holes are connected to each other in the resulting photoresist pattern when exposed using the reticle.
이와 같이 홀들이 서로 연결된 감광막 패턴을 사용하여 층간절연막을 식각하여 하층 전력금속선이 노출되도록 하면, 이웃하는 홀(10) 사이의 대각선 방향으로 일정부분이 원기둥 형상으로 식각되지 않고 남으며, 층간 절연막의 전력금속선 연결 영역에는 원기둥 절연체(20)가 남게된다.As such, when the interlayer insulating layer is etched using the photoresist pattern in which the holes are connected to each other to expose the lower power metal line, a portion of the
도 3a는 본 발명에 따라 형성된 전력금속선 연결용 홀을 관측한 현미경 사진이고 도 3b는 도 3a를 확대한 사진으로서, 이들 도면에는 이웃하는 홀 사이의 대각선 방향으로 남아있는 원기둥 절연체(20)가 도시되어 있다. 3A is a micrograph of a power metal wire connection hole formed in accordance with the present invention, and FIG. 3B is an enlarged view of FIG. 3A, which shows a
다음, 감광막 패턴을 제거하고 도전성 물질을 충진시킴으로써, 상층의 전력금속선과 하층의 전력공급선을 연결하는 공정을 완료한다.Next, the photoresist pattern is removed and the conductive material is filled, thereby completing the process of connecting the upper power metal line and the lower power supply line.
상술한 바와 같이, 본 발명에서는 상층과 하층의 전력금속선을 연결할 때, 홀이 서로 연결되도록 식각하여 절연체를 원기둥 형상으로 남기므로, 결과적으로 상층의 전력공급선과 하층의 전력공급선을 연결하는 면적이 종래의 홀에 비해 훨씬 넓어지는 효과가 있으며, 따라서 저항이 감소되는 효과가 있다. As described above, in the present invention, when the upper and lower power metal wires are connected, the insulators are left in a cylindrical shape by etching so that the holes are connected to each other, and as a result, the area connecting the upper power supply line and the lower power supply line is conventional. Compared to the hole of the effect is much wider, and thus the effect of reducing the resistance.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0653449A (en) * | 1992-07-31 | 1994-02-25 | Nec Corp | Semiconductor device |
| JPH0955423A (en) * | 1995-08-15 | 1997-02-25 | Sony Corp | Connecting structure of multilayer interconnection |
| KR20000000886A (en) * | 1998-06-05 | 2000-01-15 | 윤종용 | Semiconductor memory device having low metal wire resistance |
| JP2000232103A (en) * | 1999-02-10 | 2000-08-22 | Sony Corp | Semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0653449A (en) * | 1992-07-31 | 1994-02-25 | Nec Corp | Semiconductor device |
| JPH0955423A (en) * | 1995-08-15 | 1997-02-25 | Sony Corp | Connecting structure of multilayer interconnection |
| KR20000000886A (en) * | 1998-06-05 | 2000-01-15 | 윤종용 | Semiconductor memory device having low metal wire resistance |
| JP2000232103A (en) * | 1999-02-10 | 2000-08-22 | Sony Corp | Semiconductor device |
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