KR100869029B1 - Method of lowing dielectric constant in ild made with low-k material and ild thereby - Google Patents
Method of lowing dielectric constant in ild made with low-k material and ild thereby Download PDFInfo
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- KR100869029B1 KR100869029B1 KR1020070066400A KR20070066400A KR100869029B1 KR 100869029 B1 KR100869029 B1 KR 100869029B1 KR 1020070066400 A KR1020070066400 A KR 1020070066400A KR 20070066400 A KR20070066400 A KR 20070066400A KR 100869029 B1 KR100869029 B1 KR 100869029B1
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- 238000000034 method Methods 0.000 title claims abstract description 55
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- 238000005137 deposition process Methods 0.000 abstract description 3
- 230000035699 permeability Effects 0.000 abstract 4
- 230000015572 biosynthetic process Effects 0.000 abstract 1
- 239000002184 metal Substances 0.000 description 7
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- 239000012212 insulator Substances 0.000 description 6
- 238000010586 diagram Methods 0.000 description 3
- 239000004020 conductor Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 238000013508 migration Methods 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 239000011148 porous material Substances 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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Abstract
Description
본 발명은 층간유전체의 유전상수를 낮추는 방법 및 그에 의해 만들어진 층간유전체에 관한 것으로서, 상세하게는 금속배선 사이의 저유전율 물질로 이루어진 층간유전체를 원기둥 형태로 만들어서 층간유전체의 유전상수를 낮추 면서 현재의 CMP (chemical-mechanical polishing) 공정을 그대로 사용할 수 있는 저유전율 물질로 이루어진 층간유전체의 유전상수를 낮추는 방법 및 그에 의해 만들어진 층간유전체에 관한 것이다.The present invention relates to a method for lowering the dielectric constant of an interlayer dielectric, and to an interlayer dielectric made by the same. Specifically, the interlayer dielectric made of a low dielectric constant material between metal wirings is formed in a cylindrical form to reduce the dielectric constant of the interlayer dielectric. The present invention relates to a method for lowering the dielectric constant of an interlayer dielectric made of a low dielectric constant material capable of using a chemical-mechanical polishing (CMP) process as it is, and an interlayer dielectric made thereby.
절연체의 유전상수(k)는 전기장의 영향에서 전위 전기에너지를 저장하는 데에서의 효과성을 말한다. 말하자면 커패시터처럼 물질을 절연시키는 능력을 나타낸다. 가장 낮은 유전상수는 1.0으로서 공기이다. 높은 k 값은 좀더 큰 전기에너지를 저장한다. The dielectric constant (k) of an insulator refers to its effectiveness in storing potential electrical energy under the influence of an electric field. That is to say, the ability to insulate materials like a capacitor. The lowest dielectric constant is 1.0, which is air. High k values store more electrical energy.
낮은 k값의 유전체는 더 적은 전기장을 저장하고 금속도체의 성능속도를 증가하면서 충전시간이 더 적게 걸리기 때문에 유전체의 상수 값k를 낮추는 것은 인접한 도체 사이의 정전용량의 손실을 감소시킨다. 따라서 현재 k를 낮추기 위한 다양한 연구가 진행되고 있다. Lower dielectric constants, k, reduce the loss of capacitance between adjacent conductors because low k dielectrics store less electric field and take less charging time, increasing the performance speed of metal conductors. Therefore, various researches are currently underway to lower k.
90nm이하의 공정에서는 RC 지연를 감소시키기 위해 금속은 구리를 사용하고 층간유전체(ILD, inter-layer dielectric)는 저유전율(low-k) 물질 (k<3.0)을 사용하고 있다. 도 1은 종래의 일반적인 구리배선의 형성과정을 도시한 개략도이다. 도 1(a)에서 보는 바와 같이, 하부 구리배선(1)의 상부에 구리확산방지막(2)을 형성하고, 층간유전체(3)를 증착시킨다. 이후 사진식각공정으로 원하는 부분에 콘택과 트렌치를 형성하고 구리를 증착시킨후, CMP에 의해 과도하게 증착된 구리를 제거하여 도 1(a)와 같은 상부 구리배선(4)을 형성한다. 다음으로 상기 상부 구리배선(4)의 상부에 구리확산방지막(5)을 형성하고, 다시 층간유전체(6)를 형성하는 과정을 거치면서 도 1(b)와 같은 형상이 되도록 한다. 이후의 과정은 상기된 과정의 반복이다.In processes below 90nm, metals use copper to reduce RC delay, and low-k materials (k <3.0) are used for inter-layer dielectrics (ILDs). 1 is a schematic diagram illustrating a process of forming a conventional general copper wiring. As shown in FIG. 1A, a copper
한편 45nm이하의 공정에서는 유전상수를 더욱 낮출 필요성이 있으므로 층간유전체로 1~10nm의 기공이 형성된 초저유전율(ultra low-k) 물질(k<2.5)을 사용하거나, 금속배선을 전부 형성한 후에 층간유전체를 높은 온도에서 분해시키는 방법을 사용한다. On the other hand, in the process below 45nm, it is necessary to lower the dielectric constant even more. Therefore, use an ultra low-k material (k <2.5) having pores of 1 to 10nm as interlayer dielectric or after forming all metal wirings. A method of decomposing the dielectric at high temperatures is used.
그러나, 45nm이하의 공정에서는 유전상수를 더욱 낮추기 위하여 초저유전율 물질을 사용하거나, 금속배선을 전부 형성한 후에 층간유전체를 높은 온도에서 분해시키는 방법은 모두 기계적 강도가 좋지 못하여 후속 금속배선을 형성할 때 CMP에 어려움이 있다.However, in the process below 45nm, the method of using a very low dielectric constant material to further lower the dielectric constant or decomposing the interlayer dielectric at high temperature after forming all the metal wirings is not good in mechanical strength. There is a difficulty in CMP.
본 발명은 상기된 문제점을 해결하기 위하여 발명된 것으로서, RC 지연을 방지하기 위하여 기계적으로 약한 기공이 많은 초저유전율 물질을 사용하는 대신에 저유전율 물질을 사용하면서도, 유전상수를 초저유전율 수준으로 낮출 수 있는 저유전율 물질로 이루어진 층간유전체의 유전상수를 낮추는 방법 및 그에 의해 만들어진 층간유전체를 제공함에 그 목적이 있다.The present invention has been invented to solve the above-described problems, while using a low dielectric constant material instead of using a mechanically weak pores with very low dielectric constant to prevent RC delay, the dielectric constant can be lowered to a very low dielectric constant level. It is an object of the present invention to provide a method for lowering the dielectric constant of an interlayer dielectric made of a low dielectric constant material, and an interlayer dielectric made thereby.
본 발명에 의한 저유전율 물질로 이루어진 층간유전체의 유전상수를 낮추는 방법은, 저유전율 물질을 사용한 층간유전체에서 구리배선이 형성될 부분에 트렌치를 형성하고, 구리를 증착시킨 후에 CMP에 의해 과도하게 증착된 구리를 제거하고, 상부에 구리확산방지막을 증착시켜서 구리배선을 완성하는 다마신 공정에 있어서, 상기 CMP 완료 후에 사진 식각공정에 의해 상기 구리배선 사이의 층간유전체가 다수의 원기둥과 상기 다수의 원기둥 사이의 빈공간으로 이루어질 수 있도록 상기 층간유전체를 다수의 원기둥의 형태로 식각하는 원기둥 형성 단계를 추가로 포함한 다.In the method of lowering the dielectric constant of an interlayer dielectric made of a low dielectric constant material according to the present invention, a trench is formed in a portion where a copper wiring is to be formed in an interlayer dielectric using a low dielectric constant material, and the copper is deposited excessively by CMP after depositing copper. In the damascene process of removing the copper and depositing a copper diffusion barrier on the top to complete the copper wiring, the interlayer dielectric between the copper wiring is formed by a photolithography process after completion of the CMP. It further includes a column forming step of etching the interlayer dielectric in the form of a plurality of cylinders to be made of the empty space therebetween.
본 발명의 다른 바람직한 특징에 의하면, 상기 원기둥 형성단계가 상기 구리확산방지막을 증착시킨 이후에 실시된다.According to another preferred feature of the present invention, the cylinder forming step is performed after depositing the copper diffusion preventing film.
본 발명의 다른 바람직한 특징에 의하면, 상기 원기둥 형성 단계는 상기 구리배선이 밀집하여 RC를 감소시킬 필요가 있는 층간유전체에 대해서만 실시한다.According to another preferred feature of the present invention, the column forming step is performed only for the interlayer dielectric in which the copper wiring is dense and needs to reduce RC.
본 발명의 다른 바람직한 특징에 의하면, 상기 사진 식각공정에서 포토레지스트로 네거티브 포토레지스트를 사용한다.According to another preferred feature of the present invention, a negative photoresist is used as the photoresist in the photolithography process.
본 발명의 다른 바람직한 특징에 의하면, 상기 원기둥이 형성된 층간유전체 부분에서 상기 원기둥이 차지하는 공간 비율이 10~90% 이다.According to another preferred feature of the invention, the space ratio of the cylinder in the interlayer dielectric portion in which the cylinder is formed is 10 to 90%.
상기 원기둥과 상기 빈공간을 포함하는 층간유전체의 전체 공간에서 상기 원기둥이 차지하는 공간 비율이 0.01~90%이다.The ratio of the space occupied by the cylinder in the total space of the interlayer dielectric including the cylinder and the void is 0.01 to 90%.
본 발명의 다른 바람직한 특징에 의하면, 상기 다수의 원기둥 사이의 상기 빈공간을 스핀 코팅 또는 증착공정으로 초저유전율물질로 채운다.According to another preferred feature of the present invention, the void space between the plurality of cylinders is filled with an ultra low dielectric constant material by spin coating or deposition.
본 발명의 다른 바람직한 특징에 의하면, 상기 다수의 원기둥 사이의 빈 공간을 초저유전율 물질로 채운 후에 CMP에 의해 평탄화하는 단계를 포함한다.According to another preferred feature of the invention, the method comprises the step of flattening by CMP after filling the void space between the plurality of cylinders with an ultra low dielectric constant material.
본 발명에 의한 층간유전체는 반도체 소자의 층간유전체에 있어서, 상기 층간유전체는 저유전체 물질로 만들어진 다수의 원기둥과 상기 다수의 원기둥 사이의 빈공간으로 이루어져 있다.In the interlayer dielectric according to the present invention, in the interlayer dielectric of a semiconductor device, the interlayer dielectric is composed of a plurality of cylinders made of a low dielectric material and an empty space between the plurality of cylinders.
본 발명에 의한 다른 층간유전체는 상기 빈공간이 초저유전체 물질로 채워진 다.In another interlayer dielectric according to the present invention, the empty space is filled with an ultra low dielectric material.
본 발명에 의한 다른 층간유전체는 상기 반도체 소자에서 구리배선이 밀집하여 RC를 감소시킬 필요가 있는 부분의 층간유전체에만 상기 다수의 원기둥이 형성되어 있다.In the other interlayer dielectric according to the present invention, the plurality of cylinders are formed only in the interlayer dielectric of the portion where the copper wiring is dense in the semiconductor device and the RC needs to be reduced.
본 발명에 의하여, 층간유전체 물질로서 저유전율 물질을 사용하면서도 유전상수를 낮추어서 초저유전율정도의 유전상수의 효과를 낼 수 있으므로, 별도로 다공성의 초저유전율을 이용한 공정을 개발할 필요가 없으며, 에어 갭과 같은 효과를 낼 수 있으며, 기존의 CMP 공정을 사용할 수 있으며, 금속배선간의 캐패시턴스의 조절이 용이해지는 효과가 있다. According to the present invention, it is possible to reduce the dielectric constant while using a low dielectric constant material as the interlayer dielectric material, and thus to have an effect of the dielectric constant of the ultra low dielectric constant. Therefore, there is no need to develop a process using a porous ultra low dielectric constant separately, such as an air gap. The effect can be made, the existing CMP process can be used, and the capacitance between metal wirings can be easily adjusted.
이하 예시도면에 의거하여 본 발명의 일실시예에 대한 구성 및 작용을 상세히 설명한다. 다만, 아래의 실시예는 본 발명이 속한 기술분야에서 통상의 지식을 가진 자가 본 발명을 충분히 이해할 수 있도록 제공되는 것이지, 본 발명의 범위가 다음에 기술되는 실시예에 의해 한정되는 것은 아니다.Hereinafter, the configuration and operation of an embodiment of the present invention will be described in detail with reference to the accompanying drawings. However, the following examples are provided to enable those skilled in the art to fully understand the present invention, but the scope of the present invention is not limited by the embodiments described below.
도 2 내지 도 7는 본 발명에 의한 저유전율 물질로 이루어진 층간유전체의 유전상수를 낮추는 방법인 원기둥 형성단계를 도시한 도면이다.2 to 7 is a view showing a column forming step that is a method of lowering the dielectric constant of an interlayer dielectric made of a low dielectric constant material according to the present invention.
도 2와 같이 다마신 공정에 의해 구리배선(10)사이에 층간유전체(12)가 형성되어 있다. 이는 다마신 공정에 의해 층간유전체(12)에 트렌치를 형성하고 여기에 구리를 증착시킨 후에 CMP에 의해 과도하게 증착된 구리를 제거함으로서 도 2와 같은 형상이 얻어진다. 이는 도 1(a)에서 A부분만 도시한 것이다.As shown in FIG. 2, an interlayer dielectric 12 is formed between the
다음으로 상기 층간유전체(12)를 원기둥으로 식각하기 위한 사진 식각 공정을 진행하기 위하여 그 위에 포토레지스트(14)를 도포하여 도 3와 같은 형상이 되도록 한다. Next, in order to proceed with the photolithography process for etching the interlayer dielectric 12 into a cylinder, a
다음으로 노광공정과 현상공정을 거쳐서 도 4(a) 내지 도 4(b)와 같은 형상의 포토레지스트(14')만 남긴다. 여기서 포토레지스트의 종류에 대해서는 특별한 제한은 없지만, 네거티브 포토레지스트를 사용하면 노광공정에서 노광되지 않은 부분만 녹게 되어 도 4(a) 내지 도 4(b)와 같은 형상을 비교적 쉽게 만들 수 있다. 도 4(a)는 사시도이고, 도 4(b)는 위에서 본 평면도이다. Next, only the photoresist 14 'having a shape as shown in Figs. 4A to 4B is left through the exposure step and the developing step. The type of photoresist is not particularly limited. However, when the negative photoresist is used, only the unexposed portion is melted in the exposure process, thereby making the shape as shown in FIGS. 4 (a) to 4 (b) relatively easy. Fig. 4A is a perspective view and Fig. 4B is a plan view from above.
다음으로 상기 포토레지스트(14')를 마스크로 하여 식각공정을 진행하여 층간유전체가 도 5(a) 내지 도 5(b)와 같이 원기둥의 형상이 되도록 한다. 이렇게 층간유전체(12')를 원기둥으로 만듬으로서, 상기 원기둥 사이에는 빈 공간이 형성되므로 유전상수는 더욱 낮아지게 된다. 이 때 유전상수는 초저유전율 물질 정도까지 낮아질 수 있다. 도 5(a)는 사시도이고, 도 5(b)는 위에서 본 평면도이다.Next, an etching process is performed using the photoresist 14 'as a mask so that the interlayer dielectric is shaped like a cylinder as shown in FIGS. 5 (a) to 5 (b). By thus making the interlayer dielectric 12 'into a cylinder, a dielectric constant is further lowered because an empty space is formed between the cylinders. In this case, the dielectric constant may be lowered to an extremely low dielectric constant material. Fig. 5A is a perspective view and Fig. 5B is a plan view from above.
여기서 원기둥의 크기와 갯수는 공정에서 필요로 하는 유전상수에 맞추어서 조절될 수 있다. 상기 원기둥이 형성된 층간유전체 부분에서 상기 원기둥이 차지하는 공간 비율이 10~90%이어야 한다. 원기둥이 차지하는 공간비율이 10% 미만이면, 빈공간이 너무 많아서 기계적인 강도가 떨어지는 문제점이 있으며, 90%를 초과하면 빈공간이 너무 적어서 유전상수가 거의 낮아지지 않는 문제점이 있다.Here, the size and number of cylinders can be adjusted to the dielectric constant required by the process. The space ratio occupied by the cylinder in the interlayer dielectric portion in which the cylinder is formed should be 10 to 90%. If the space ratio occupied by the cylinder is less than 10%, there is a problem that the mechanical strength is lowered because there are too many empty spaces, and if there is more than 90%, there is a problem that the dielectric constant is hardly lowered because the empty space is too small.
또한 유전상수를 낮출 필요가 없는 부분의 층간유전체에 대해서는 상기된 원기둥을 형성할 필요가 없다.In addition, it is not necessary to form the above-described cylinder for the interlayer dielectric in a portion where the dielectric constant does not need to be lowered.
이후의 공정은 통상의 구리금속배선을 형성하는 것과 동일하게 상부에 구리확산방지막을 형성하고, 층간절연체를 증착시키는 과정을 거치면 된다. Subsequent processes may be performed by forming a copper diffusion barrier on the top and depositing an interlayer insulator in the same manner as the conventional copper metal wiring.
이러한 과정을 거쳐서 완성된 층간유전체는 저유전체 물질로 만들어진 다수의 원기둥과 상기 다수의 원기둥 사이의 빈공간으로 이루어진 구조이다.The interlayer dielectric completed through such a process is composed of a plurality of cylinders made of a low dielectric material and a void space between the plurality of cylinders.
본 발명의 다른 실시예에 의하면, 상기 원기둥 층간유전체(12')를 형성한 이후에 상기 원기둥 사이의 빈 공간을 초저유전율 물질로 채우는 단계가 추가될 수 있다. 도 5에서의 빈공간을 초저유전율 물질로 채우기 위하여 초저유전율물질(16)을 도 6와 같이 상부에 스핀코팅하거나 또는 CVD등의 통상적인 증착공정을 통하여 상기 빈공간을 초저유전율물질로 채울 수 있다.According to another embodiment of the present invention, after forming the
또한 초저유전율물질로 빈공간을 채우기 위하여 스핀코팅하거나 또는 CVD등의 통상적인 증착공정을 사용하면 과도하게 증착된 초저유전율 물질을 제거하기 위한 CMP 공정이 추가될 수도 있다. 이러한 과정을 거치게 되면, 도 7(a) 내지 도 7(b)와 같이, 구리배선(10)사이의 층간절연체는 저유전율 물질로 이루어진 원기둥(12')이고, 상기 원기둥 사이의 빈 공간은 초저유전율 물질(16)로 채워지게 된다. 따라서 층간절연체의 유전상수는 저유전율 물질만 사용할 때보다 낮아지게 된다. 이 때 유전상수는 초저유전율 물질 정도까지 낮아질 수 있다. 도 7(a)는 사시도이고, 도 7(b)는 평면도이다.In addition, a CMP process may be added to remove an overly deposited ultra low dielectric constant material by spin coating to fill an empty space with an ultra low dielectric constant material or by using a conventional deposition process such as CVD. Through this process, as shown in FIGS. 7A to 7B, the interlayer insulator between the
상기된 설명은 다마신 공정에서 층간유전체(12)에 트렌치를 형성하고 여기에 구리를 증착시킨 후에 CMP에 의해 과도하게 증착된 구리를 제거한 이후에 층간유전체를 원기둥으로 만드는 과정에 대하여 설명하였다. 그러나 상기 공정은 다마신 공정에서 CMP에 의해 과도하게 증착된 구리를 제거하고 상부에 구리확산방지막을 형성한 이후에 본 발명에 의하여 층간유전체를 원기둥으로 만드는 원기둥 형성단계를 진행하여도 된다.The above description has described a process of making the interlayer dielectric into a cylinder after forming a trench in the
이러한 과정을 거쳐서 완성된 층간유전체는 저유전체 물질로 만들어진 다수의 원기둥과 상기 다수의 원기둥 사이의 공간이 초저유전체 물질로 채워진 구조이 다.The interlayer dielectric completed through such a process has a structure in which a plurality of cylinders made of a low dielectric material and a space between the plurality of cylinders are filled with an ultra low dielectric material.
또한 상기 원기둥 형성단계에 의한 층간유전체에 다수의 원기둥과 다수의 원기둥 사이의 빈공간을 만드는 것은 구리배선이 밀집하여 RC를 감소시킬 필요가 있는 부분의 층간유전체에 대해서만 실시할 수도 있다. 이러한 과정을 거쳐서 완성된 층간유전체는 RC를 감소시킬 필요가 있는 부분은 원기둥과 빈공간으로 이루어져 있고, RC를 감소시킬 필요가 없는 부분은 원기둥이 없는 일반적인 형태의 층간유전체로 이루어지게 된다.In addition, the empty space between the plurality of cylinders and the plurality of cylinders in the interlayer dielectric by the column forming step may be performed only for the interlayer dielectric of the portion where the copper wiring is concentrated to reduce the RC. The interlayer dielectric completed through such a process consists of a cylinder and an empty space in which the RC needs to be reduced, and a portion of the interlayer dielectric in which the RC does not need to be reduced consists of a general type of interlayer dielectric without a cylinder.
본 발명에 의한 방법은 층간유전체가 저유전율물질이 지탱하고 있기 때문에 초저유전상수 (초low-k) 값을 보이면서도 기존의 CMP(chemical mechanical polishing) 공정을 그대로 사용할 수 있고 EM(electro-migration), SM(stress-migration) 등의 신뢰성을 포함하여 에어갭(air gap)보다 장점이 훨씬 많은 발명이다.In the method according to the present invention, since the interlayer dielectric is supported by a low dielectric constant material, an existing CMP (chemical mechanical polishing) process can be used as it is while showing an ultra low dielectric constant (ultra low-k) value, and an electro-migration (EM) method. This invention is much more advantageous than an air gap, including reliability such as stress-migration (SM).
도 1은 종래의 일반적인 구리배선의 형성과정을 도시한 개략도,1 is a schematic diagram showing a process of forming a conventional general copper wiring,
도 2 내지 도 7는 본 발명에 의한 저유전율 물질로 이루어진 층간유전체의 유전상수를 낮추는 방법을 도시한 도면이다.2 to 7 are diagrams showing a method of lowering the dielectric constant of an interlayer dielectric made of a low dielectric constant material according to the present invention.
<도면의 주요 부분에 대한 주요 부호의 설명><Description of the main symbols for the main parts of the drawings>
10 : 구리배선 12 : 층간절연체10
12' : 원기둥 형상의 층간절연체 14 : 포토레지스트 12 ': cylindrical interlayer insulator 14: photoresist
14' : 원기둥 형상의 포토레지스트 16 : 초저유전율 물질14 ': cylindrical photoresist 16: ultra-low dielectric constant material
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| KR20030044693A (en) * | 2001-11-30 | 2003-06-09 | 아남반도체 주식회사 | Connecting method of power metal line in semiconductor devices |
| KR20050045270A (en) * | 2003-11-10 | 2005-05-17 | 삼성전자주식회사 | Method of forming a cu interconnection selectively forming a cu plating layer |
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| KR20030044693A (en) * | 2001-11-30 | 2003-06-09 | 아남반도체 주식회사 | Connecting method of power metal line in semiconductor devices |
| KR20050045270A (en) * | 2003-11-10 | 2005-05-17 | 삼성전자주식회사 | Method of forming a cu interconnection selectively forming a cu plating layer |
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