KR100758222B1 - Voltage peak detector with self-clock generator - Google Patents

Abstract

A sine-wave voltage peak detector having a self-clock generator is provided to precisely detect a peak value of sine-wave voltage regardless of the change of frequency by generating the correspondent sample clock. A sine-wave voltage peak detector having a self-clock generator(10) is composed of a sine-wave voltage source(Vi); a first buffer(21) receiving and buffering the sine-wave voltage from a plus terminal of the sine-wave voltage source; a first switch(30) connected with the output side of the first buffer in series and switched according to the control of the clock generator; a second buffer(22) receiving and buffering a signal switched in the first switch; a first capacitor(C1) having one terminal connected between the first switch and the second buffer and the other terminal coupled with a minus power voltage terminal; a second switch(40) connected with the output side of the second buffer in series and switched according to the control of the clock generator; a third buffer(23) outputting a peak value of the detected sine-wave voltage by receiving and buffering a signal switched in the second switch; a second capacitor(C2) having one terminal connected between the second switch and the third buffer and the other terminal coupled with a minus power voltage terminal; and the clock generator receiving the sine-wave voltage from the plus terminal of the sine-wave voltage source and controlling the switching operations of the first and second switches by generating self-clock.

Description

Voltage Peak Detector with Self-Clock Generator

1 is a voltage detector and waveform diagram of a conventional sample and hold method.

2 is a voltage detector and waveform diagram using a conventional rectifier and a low pass filter.

3 is a conceptual diagram of a sinusoidal voltage maximum detector having its own clock generator according to an embodiment of the present invention.

4 is a circuit diagram illustrating a specific embodiment of FIG. 3.

5 is a waveform diagram of each point of FIG. 4.

6 is a view showing another embodiment of SW1, SW2 in FIG.

Explanation of symbols on the main parts of the drawings

10: clock generator

21: first buffer

22: second buffer

23: third buffer

30: first switch

31: first NMOS

32: first PMOS

33: first NMOS / PMOS

40: second switch

41: second NMOS

42: second PMOS

43: second NMOS / PMOS

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a voltage detector, and in particular, by generating a clock using a sinusoidal power supply voltage waveform, a maximum value is automatically detected without needing to separately synchronize a clock and a sample section, A sinusoidal voltage maximum detector with its own clock generator that generates a sample clock correspondingly even when the frequency of the waveform changes so that it is suitable for accurately detecting the maximum value of the sinusoidal voltage regardless of the frequency change. It is about.

1 is a voltage detector and waveform diagram of a conventional sample and hold method.

As shown in FIG. 1, the sinusoidal voltage (waveform Vi of FIG. 1) is detected through the switch SW1 to charge the capacitor C1 to detect the maximum value. As in the SW1 CTL waveform of FIG. 1, the SW1 CTL signal is "ON" in the high section to charge the capacitor, and the switch SW1 is "OFF" to maintain the value. .

However, such a conventional method requires a separate synchronization circuit for turning the switch SW1 "OFF" to exactly "OFF" at the maximum value of the sine wave, and it is not easy to construct an accurate synchronization circuit. The furnace is very complicated and difficult to realize. In addition, if the frequency of the input voltage (Vi) is changed or the phase is changed in the circuit which is synchronized once, the maximum value cannot be detected and there is a problem that all the circuits must be newly synchronized.

2 is a voltage detector and waveform diagram using a conventional rectifier and a low pass filter.

Here, reference numeral 1 is a rectifier and 2 is a low pass filter (LPF).

Thus, as shown in FIG. 2, the full-wave rectifier 1 is connected to the input power supply voltage Vi, and the full-wave rectified voltage is smoothed through the low pass filter 2 to obtain a maximum value.

However, although the conventional method as shown in FIG. 2 can cope with the frequency change, it becomes impossible to obtain an accurate maximum value as the low pass filter continues charging / discharging.

Accordingly, the present invention has been proposed to solve the above-mentioned conventional problems, and an object of the present invention is to automatically generate a maximum value without the need for separate clock and sample intervals through clock generation using a sinusoidal power supply voltage waveform. Provides a sinusoidal voltage maximum detector with its own clock generator that detects and generates a sample clock correspondingly even when the frequency of the power supply voltage waveform changes, so that the sinusoidal voltage can be detected accurately regardless of the frequency change. It is.

In order to achieve the above object, the sinusoidal voltage maximum detector having its own clock generator according to an embodiment of the present invention,

A sinusoidal voltage source; A first buffer configured to receive and buffer a sinusoidal voltage from a + terminal of the sinusoidal voltage source; A first switch connected in series with an output of the first buffer and switching under control of a clock generator; A second buffer configured to receive and buffer the signal switched by the first switch; A first capacitor connected between the first switch and the second buffer, and the other terminal connected to a power supply voltage negative terminal; A second switch connected in series with the output of the second buffer and switching under control of the clock generator; A third buffer receiving the buffered signal from the second switch and outputting the detected sinusoidal voltage maximum value; A second capacitor connected between the second switch and the third buffer, and the other terminal connected to a power supply negative terminal; And a clock generator configured to receive a sinusoidal voltage from the + terminal of the sinusoidal voltage source and generate a self clock to control switching operations of the first switch and the second switch.

Hereinafter, an embodiment of the present invention as described above, according to the spirit of the sine wave voltage maximum value detector having its own clock generator will be described with reference to the drawings.

3 is a conceptual diagram of a sinusoidal voltage maximum detector having its own clock generator according to an embodiment of the present invention.

As shown therein, the sinusoidal voltage source Vi; A first buffer (Buffer1) 21 for receiving and buffering a sinusoidal voltage from the + terminal of the sinusoidal voltage source Vi; A first switch (SW1) 30 connected in series with the output of the first buffer 21 and switching under the control of the clock generator 10; A second buffer 22 which receives and buffers the signal switched by the first switch (SW1) 30; A first capacitor C1 connected between the first switch 30 and the second buffer 22 and the other terminal connected to a power supply voltage negative (-) terminal (GND, ground); A second switch (SW2) 40 connected in series with the output of the second buffer 22 and switching under the control of the clock generator 10; A third buffer (23) for receiving the buffered signal from the second switch (SW2) 40 and outputting the maximum value of the detected sinusoidal voltage; A second capacitor C2 connected between one terminal between the second switch 40 and the third buffer 23 and the other terminal connected to a negative power supply terminal (GND); A clock generator 10 receiving a sinusoidal voltage from the + terminal of the sinusoidal voltage source Vi and generating a clock to control switching operations of the first switch SW1 and the second switch SW2; Characterized in that configured.

4 is a circuit diagram illustrating a specific embodiment of FIG. 3.

As shown therein, the clock generator 10 includes: a multiplier for receiving a sinusoidal voltage from a + terminal of the sinusoidal voltage source Vi and outputting a sinusoidal wave whose frequency is a multiple; A first inverter (INV1) for inverting the phase of the sine wave of the multiples output from the multiplier; A second inverter (INV2) for reversing the output of the first inverter (INV1); A third inverter (INV3) for reversing the output of the second inverter (INV2); A fourth inverter (INV4) for receiving a sinusoidal voltage from the + terminal of the sinusoidal voltage source (Vi) and inverting the phase; A fifth inverter (INV5) for reversing the output of the fourth inverter (INV4); A first AND product AND1 for receiving the outputs of the third inverter INV3 and the fifth inverter INV5 and performing an AND operation to control a switching operation of the second switch 40; And a second logical AND device AND2 for receiving the outputs of the second inverter INV2 and the fifth inverter INV5 and performing logical AND operation to control the switching operation of the first switch 30. It is characterized by.

The multiplier is characterized by consisting of an analog multiplier.

6 is a view showing another embodiment of SW1, SW2 in FIG.

As shown therein, the first switch SW1 30 has a gate connected to the second AND product AND2 in the clock generator 10 and a source connected to the output terminal of the first buffer 21. And a drain having a first NMOS 31 connected to an input terminal of the second buffer 22, and the second switch SW2 40 has a gate of a first logical multiplication element (i) in the clock generator 10. And a second NMOS 41 connected to an AND1), a source connected to an output terminal of the second buffer 22, and a drain connected to an input terminal of the third buffer 23.

In addition, the first switch SW1 30 has a gate connected to the second AND product AND2 in the clock generator 10, a drain connected to an output terminal of the first buffer 21, and a source of the first switch SW1 30. It is composed of a first PMOS 32 connected to the input terminal of the second buffer 22, the second switch (SW2) 40, the gate is connected to the first logical AND (AND1) in the clock generator 10 And a drain connected to an output terminal of the second buffer 22 and a source configured to a second PMOS 42 connected to an input terminal of the third buffer 23.

In addition, the first switch (SW1) 30 is connected to the gate of the NMOS is connected to the output of the second logical AND (AND2) in the clock generator 10 and the gate of the PMOS is the second in the clock generator 10 The NMOS source and the PMOS drain are connected to the output terminal of the first buffer 21, and the NMOS drain and the PMOS source are connected to the phase inverted output of the AND product AND2. A first NMOS / PMOS 33 connected to an input terminal, and the second switch SW2 40 has a gate of an NMOS connected to an output of the first AND product AND1 in the clock generator 10. A gate of the PMOS is connected to the phase-inverted output of the first AND product AND1 in the clock generator 10, and a source of the NMOS and a drain of the PMOS are connected to an output terminal of the second buffer 22. Characterized in that the drain and the source of the PMOS consist of a second NMOS / PMOS 43 connected to the input of the third buffer 23. It shall be.

A preferred embodiment of the sinusoidal voltage maximum value detector having its own clock generator according to the present invention configured as described above will be described in detail with reference to the accompanying drawings. In the following description of the present invention, detailed descriptions of well-known functions or configurations will be omitted if it is determined that the detailed description of the present invention may unnecessarily obscure the subject matter of the present invention. In addition, terms to be described below are terms defined in consideration of functions in the present invention, which may vary according to intention or precedent of a user or an operator, and thus, the meaning of each term should be interpreted based on the contents throughout the present specification. will be.

First, the present invention automatically detects the maximum value without generating a synchronization between the clock and the sample interval by generating a clock using a sinusoidal power supply voltage waveform, and generates a sample clock correspondingly even when the frequency of the power supply voltage waveform changes. This is to accurately detect the maximum value of sinusoidal voltage regardless of the frequency change.

Thus, in the present invention, there is a sinusoidal voltage source Vi having an arbitrary size and frequency as shown in FIG. 3, and the first buffer 21, which is the voltage Buffer1 at the voltage source plus (+) terminal, is connected, and then the first switch ( SW1) is connected in series, and is connected to one terminal of the capacitor C1 through the first switch SW1, and the other terminal of the capacitor C1 is connected to the power supply voltage negative terminal GND. In addition, at the connection point of the first switch SW1 and the capacitor C1, the second buffer 22 which is the voltage Buffer2 is connected, and then the second switch SW2 is connected. The other end of the second switch SW2 is connected with the capacitor C2 and the third buffer 23 which is the voltage Buffer3. The other terminal of capacitor C2 is connected to GND. On the other hand, the input power supply voltage Vi is connected to the clock generator 10 at the plus (+) terminal, and the outputs C and D of the clock generator 10 are connected to SW1 and SW2, respectively, to become control signals of SW1 and SW2, respectively.

As shown in FIG. 4, when the power supply voltage Vi passes through Buffer1 and SW1 is “ON” in FIG. 4, the same voltage waveform as that of the input voltage Vi is applied to the capacitor C1, and as shown in ① of FIG. The same waveform appears, and when SW1 is "OFF", the Vi voltage at the moment of "OFF" is held in capacitor C1. Subsequently, when SW2 is turned "ON" through Buffer2, the voltage of node ① is charged to capacitor C2. When SW2 is "OFF", the voltage of node ① at the moment of being "OFF" is maintained at capacitor C2 as shown in ② of FIG. This voltage is expressed as Vo through Buffer3.

Meanwhile, the input power supply voltage Vi is connected to a clock generator 10 to generate signals C and D for controlling SW1 and SW2. Detailed operations thereof will be described with reference to FIGS. 4 and 5.

4 shows an embodiment of a sinusoidal voltage detector with a clock generator of the present invention.

First, when the power supply voltage Vi passes through the inverters INV4 and INV5, it becomes a square wave having the same frequency and phase as the input voltage Vi, as shown by the waveform A shown in FIG. In addition, when the input voltage Vi passes through a multiplier shown in FIG. 4, a sinusoidal wave having a frequency of 2 times is output. It becomes a square wave twice.

)이 되며, A파형과

파형을 제1 논리곱 소자(AND1)를 통과하면 파형 D (=

)가 되며, 이는 도 5에 보인 파형도 D와 같다. 또한 파형 B와 A를 제2 논리곱 소자(AND2)를 통과시키면 파형 C(=

)가 되며 이는 도 5에 보인 파형 C와 같다.If the waveform of B passes the inverter INV3, the waveform of B waveform has 180 ° phase difference.

) And A waveform

When the waveform passes through the first AND product AND1, the waveform D (=

), Which is the same as the waveform diagram D shown in FIG. In addition, when waveforms B and A pass through the second AND product AND2, waveforms C (=

), Which is the same as waveform C shown in FIG.

The generated C and D waveforms become the control signals of the switches SW1 and SW2 described above, and the operations including the same are as follows.

In FIG. 5, SW1 is “ON” in the section where the applied power supply voltage Vi passes through Buffer1 and waveform C is High, and the waveform of node ① follows Vi as it is in the waveform of ① in FIG. 5. In the next C low section, the voltage at the moment when SW1 is " OFF " is maintained (waveform 1 in FIG. 5).

Subsequently, in the period where D is high, SW2 is "ON" and follows the waveform ①, and when D is low, the waveform of node ① at this moment is maintained. Therefore, as indicated by the waveform ② of FIG. 5, the voltage of the node ② maintains the maximum value of the input voltage Vi and is output to Vo through Buffer3.

On the other hand, in the embodiment of the present invention, the multiplier may use an analog multiplier, and as in the embodiment of the present invention, the NMOS may be implemented alone or as in the other embodiments of SW1 and SW2 of FIG. 6. It can also be implemented using.

,

를 각각 SW1, SW2에 가함으로써 구현시킨다.When using PMOS, waveforms C and D are inverted

,

Is implemented by adding to SW1 and SW2, respectively.

,

와 C, D의 신호를, C는 SW1의 NMOS 게이트에

는 SW1의 PMOS 게이트에,

는 SW2의 PMOS 게이트에 D는 SW2의 NMOS 게이트에 각각 연결하며 구현할 수 있다.Also, when SW1 and SW2 are implemented as PMOS and NMOS pairs, the signal required when using PMOS is

,

And the signals of C and D, C to the NMOS gate of SW1

On the PMOS gate of SW1,

Is connected to the PMOS gate of SW2 and D is connected to the NMOS gate of SW2, respectively.

The advantage of implementing SW1 and SW2 as NMOS and PMOS pairs is that the "ON" resistance of SW1 and SW2 is smaller, which reduces the loss due to the switch resistance, thus making the switching operation less sensitive to the magnitude of the input signal Vi. .

As such, the present invention automatically detects the maximum value without generating a synchronization between the clock and the sample interval by generating a clock using the sinusoidal power supply voltage waveform, and generates a sample clock correspondingly even when the frequency of the power supply voltage waveform changes. In this way, the maximum value of the sinusoidal voltage is accurately detected regardless of the frequency change.

As described above, the sinusoidal voltage maximum detector having its own clock generator according to the present invention does not use a separate clock generator externally to detect the maximum value of the sinusoidal voltage, and thus, has no difficulty of synchronizing with the waveform. The voltage can be used to accurately detect the maximum value through the clock generator synchronized with the maximum value of the power supply voltage. This allows additional adjustment or addition when the frequency of the power supply voltage is changed or when the power supply voltage with different frequency is detected. A frequency-independent sinusoidal voltage maximum detector that can be used without circuits can be implemented.

In general, a perfect direct-current voltage can be obtained without the need for a low-pass filter added for the smoothing of the output waveform at the subsequent stage of the maximum detector.

Although the above has been described as being limited to the preferred embodiment of the present invention, the present invention is not limited thereto and various changes, modifications, and equivalents may be used. Therefore, the present invention can be applied by appropriately modifying the above embodiments, it will be obvious that such application also belongs to the scope of the present invention based on the technical idea described in the claims below.

Claims (6)

A sinusoidal voltage source; A first buffer configured to receive and buffer a sinusoidal voltage from a + terminal of the sinusoidal voltage source; A first switch connected in series with an output of the first buffer and switching under control of a clock generator; A second buffer configured to receive and buffer the signal switched by the first switch; A first capacitor connected between the first switch and the second buffer, and the other terminal connected to a power supply voltage negative terminal; A second switch connected in series with the output of the second buffer and switching under control of the clock generator; A third buffer receiving the buffered signal from the second switch and outputting the detected sinusoidal voltage maximum value; A second capacitor connected between the second switch and the third buffer, and the other terminal connected to a power supply negative terminal; A clock generator for receiving a sinusoidal voltage from a + terminal of the sinusoidal voltage source and generating a self clock to control switching operations of the first switch and the second switch; Sinusoidal voltage maximum detector having its own clock generator, characterized in that configured to include. The method according to claim 1, The clock generator, A multiplier for receiving a sinusoidal voltage from a + terminal of the sinusoidal voltage source and outputting a sine wave whose frequency is a multiple; A first inverter for reversing the sine wave of the multiples output from the multiplier; A second inverter for phase inverting the output of the first inverter; A third inverter for phase inverting the output of the second inverter; A fourth inverter configured to receive a sinusoidal voltage from a + terminal of the sinusoidal voltage source and to reverse the phase; A fifth inverter for reversing the output of the fourth inverter; A first logical AND element that receives the outputs of the third inverter and the fifth inverter and performs an AND operation to control a switching operation of the second switch; A second logical AND element configured to receive an AND operation of the outputs of the second inverter and the fifth inverter to control a switching operation of the first switch; Sine wave voltage maximum value detector having its own clock generator, characterized in that configured to include. The method according to claim 2, The multiplier, A sine wave voltage maximum detector with its own clock generator, characterized by an analog multiplier. The method according to any one of claims 1 to 3, The first switch includes a first NMOS gate connected to a second AND product in the clock generator, a source connected to an output terminal of the first buffer, and a drain connected to an input terminal of the second buffer, The second switch is characterized in that it is composed of a second NMOS gate is connected to the first AND device in the clock generator, the source is connected to the output terminal of the second buffer, the drain is connected to the input terminal of the third buffer Sinusoidal voltage maximum detector with a clock generator. The method according to any one of claims 1 to 3, The first switch includes a first PMOS having a gate connected to a second AND product in the clock generator, a drain connected to an output terminal of the first buffer, and a source connected to an input terminal of the second buffer, The second switch is characterized in that the gate is connected to the first AND device in the clock generator, the drain is connected to the output terminal of the second buffer and the source is composed of a second PMOS connected to the input terminal of the third buffer Sinusoidal voltage maximum detector with a clock generator. The method according to any one of claims 1 to 3, The first switch has a gate of the NMOS connected to the output of the second AND device in the clock generator and a gate of the PMOS connected to the phase inverted output of the second AND device in the clock generator. A drain is connected to an output terminal of the first buffer and a drain of the NMOS and a source of PMOS are composed of a first NMOS / PMOS connected to an input terminal of the second buffer, The second switch has a gate of the NMOS connected to the output of the first AND device in the clock generator and a gate of the PMOS connected to the phase inverted output of the first AND device in the clock generator, the source of the NMOS and the PMOS. And a second NMOS / PMOS having a drain connected to an output terminal of the second buffer and a drain of an NMOS and a source of PMOS connected to an input terminal of the third buffer.

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