TWI523435B - Analog-to-digital converting device - Google Patents

Description

Analog digital converter

The present invention relates to a device, and more particularly to an analog digital conversion device.

With the booming digital era and the rise of electronic digital products, how to convert analog signals into digital signals required by electronic products is particularly important, so analog digital converters are an integral part of circuit design. The main function of the conventional analog-to-digital conversion device is to convert the analog signal received by it into a digital signal, and the conventional analog-to-digital conversion device comprises a comparator and a continuous approximation temporary circuit electrically connected to the comparator, the comparator Comparing the voltage magnitudes of the plurality of positive and negative phase analog signals received therefrom, and generating respective plurality of comparison signals corresponding thereto, the continuous approximation temporary storage circuit receiving the comparison signals from the comparator, and A digital signal having a plurality of bits is generated.

However, when the voltage difference between the positive phase and the negative phase analog signal received by the comparator is small, the comparator may be delayed in generating the corresponding comparison signals, that is, the comparator is metastable. The meta-stability situation, which causes the continuous approximation temporary circuit to delay generating the digital signal, resulting in the conversion speed of the conventional analog digital conversion device. Very slow.

Accordingly, it is an object of the present invention to provide an analog digital conversion device that can increase the conversion speed.

Therefore, the analog-to-digital conversion device of the present invention receives a positive phase input voltage and a negative phase input voltage, and accordingly generates a digital signal having N bits, N ≧ 3 , and N is a positive integer, and includes a capacitor array circuit a comparator, a metastable detection module, and a continuous approximation temporary storage circuit.

The capacitor array circuit sequentially operates in N comparison periods, and receives the normal phase input voltage, the negative phase input voltage, a positive phase control signal, and a negative phase control signal, and the positive phase and negative phase control signals have P bits, P=N+1, and in each comparison period, the capacitor array circuit determines one of the positive phase input voltages to be decremented according to the logic level of each bit of the normal phase control signal Amplitude to generate a positive phase output voltage, the capacitor array circuit determining a magnitude of the negative phase input voltage to be decremented according to a logic level of each bit of the negative phase control signal to generate a negative phase output voltage .

The comparator is electrically connected to the capacitor array circuit to sequentially receive the positive and negative phase output voltages generated by the capacitor array circuit in each comparison period, and according to the positive phase and the negative phase in each comparison period The difference in output voltage is used to generate a comparison signal, and a comparison end signal is output while the comparison signal is being generated.

The metastable detection module is electrically connected to the comparator to sequentially receive the comparison end signal generated by the comparator in each comparison period. And generating a detection signal indicating whether metastability occurs according to the comparison end signal.

The continuous approximation temporary storage circuit is electrically connected to the comparator to sequentially receive the comparison signal from the comparator in each comparison period, and is electrically connected to the metastable detection module to be sequentially received in each comparison period. The detection signal from the metastable detection module.

When the detection signal indicates a metastable state, the continuous approximation temporary storage circuit determines a logic level of the bit element to be adjusted by the positive phase control signal and the negative phase control signal according to the detection signal. Wherein, each bit of the positive phase control signal and the negative phase control signal has a predetermined initial logic level, and the N comparison periods include first to Nth comparison periods, the positive in the first comparison period The bit to be adjusted of the phase and negative phase control signals is the first and second bits, and the bits to be adjusted of the positive and negative phase control signals in the second comparison period are the third and fourth bits The correspondingly adjusted bits of the positive phase and negative phase control signals in the third to (N-1)th comparison periods are fifth to Pth bits, respectively.

The continuous approximation temporary storage circuit performs a logic operation to generate the digital signal having N bits according to the normal phase control signal and a comparison signal generated by the comparator in the Nth comparison period.

11‧‧‧Capacitor array circuit

111‧‧‧First switch

112‧‧‧Second switch

12‧‧‧ comparator

13‧‧‧ Metastable Detection Module

131‧‧‧Delay circuit

132‧‧‧ phase detection circuit

14‧‧‧Continuous approximation temporary storage circuit

15‧‧‧Signal generation circuit

C1~C7‧‧‧first capacitor

G1~G7‧‧‧First reverse gate

C1~c7‧‧‧second capacitor

G1~g7‧‧‧second reverse gate

P1~p7‧‧‧ bits

N1~n7‧‧‧ bits

Other features and effects of the present invention will be apparent from the following description of the drawings, wherein: FIG. 1 is a circuit diagram illustrating a preferred embodiment of the analog-to-digital conversion device of the present invention; Figure 2 is a circuit diagram showing a capacitor array circuit of the preferred embodiment.

Referring to FIG. 1 and FIG. 2, a preferred embodiment of the analog-to-digital conversion apparatus of the present invention receives a positive phase input voltage and a negative phase input voltage, and accordingly generates a digital signal having N bits, N≧3, and N is a positive integer. In this embodiment, for convenience of explanation, N=6 is taken as an example, and the six bits of the digital signal are respectively bit B1 to B6, but are not limited thereto. The analog-to-digital conversion device includes a capacitor array circuit 11, a comparator 12, a metastable detection module 13, a continuous approximation temporary storage circuit 14, and a signal generation circuit 15.

The capacitor array circuit 11 sequentially operates in six (ie, N=6) comparison periods (ie, first to sixth comparison periods), and receives the normal phase input voltage, the negative phase input voltage, and a positive phase. a control signal, a negative phase control signal and a sampling signal, and sampling the positive phase input voltage and the negative phase input voltage according to the sampling signal, and the positive phase and negative phase control signals have seven (ie, P= N+1=7) bits, each of the positive phase control signal and the negative phase control signal has a predetermined initial logic level. In this embodiment, the seven bits of the positive phase control signal are the first to seventh bits p1~p7, respectively, and the seven bits of the negative phase control signal are the first to seventh bits n1~ N7, the preset initial logic level of each bit p1~p7, n1~n7 is a low logic level.

In each comparison period, the capacitor array circuit 11 determines the positive according to the logic level of each bit p1~p7 of the positive phase control signal. The phase input voltage is decremented by a magnitude to generate a positive phase output voltage V1. The capacitor array circuit 11 determines the negative phase input voltage according to the logic level of each bit n1~n7 of the negative phase control signal. Decreasing a magnitude to generate a negative phase output voltage V2, and the capacitor array circuit 11 includes a first and second switches 111, 112, seven first capacitors C1 C C7, and seven first back gates G1 ~ G7, seven second capacitors c1~c7 and seven second gates g1~g7.

The first switch 111 has a first end for receiving the positive phase input voltage, and a second end for outputting the positive phase output voltage V1 during each comparison period, and is controlled to be turned on or off by the sampling signal. Each of the first capacitors C1 C C7 has a first end electrically connected to the second end of the first switch 111 and a second end. Each of the first anti-gates G1 G G7 has a first end, a second end, and a third end, and the second ends of the first anti-gates G1 G G7 respectively The third terminals of the first and second gates G1 G G7 are respectively electrically connected to the first capacitors C1 C C7 to C7 respectively corresponding to the corresponding positive phase control signals. The second ends of the first and second gates G1 G G7 are outputted at the third end according to the reset signal and the bit in the positive phase control signal corresponding thereto. Logic signal. Wherein, each positive phase output voltage V1 is related to the voltage across the first capacitors C1 C C7.

The second switch 112 has a first end for receiving the negative phase input voltage, and a second end for outputting the negative phase output voltage V2 during each comparison period, and is controlled to be turned on or off by the sampling signal. Each of the second capacitors c1 c c7 has a second end electrically connected to the second end of the second switch 112 One end, and one second end. Each of the second anti-gates g1 to g7 has a first end, a second end, and a third end receiving the reset signal, and the second ends of the second anti-gates g1 to g7 respectively Receiving the corresponding n-ths n1 to n7 of the corresponding negative phase control signals, the third ends of the second anti-gates g1 to g7 are respectively electrically connected to the respective second capacitors c1 to c7 The second end, and each of the second anti-gates g1~g7 outputs a second at the third end according to the reset signal and the corresponding bit in the negative phase control signal received Logic signal. Wherein, each negative phase output voltage V2 is related to the voltage across the second capacitors c1 c c7.

In this embodiment, an initial logic level of the reset signal is the preset initial logic level. The capacitance values of the capacitors C1, C2, c1, and c2 are 8C, and the capacitance values of the capacitors C3 to C5 and c3 to c5 are 4C, and the capacitance values of the capacitors C6 and c6 are 2C, and the capacitors C7 and c7. The capacitance value is 1C, where C is a unit capacitance value, but is not limited thereto.

The comparator 12 is electrically connected to the capacitor array circuit 11 and has first to third input terminals and first and second output terminals. The first input terminal receives a uniform energy signal in each comparison period, and the second And the third input terminal sequentially receives the positive and negative phase output voltages V1 and V2 generated by the capacitor array circuit 11 in each comparison period, and the comparator 12 is configured according to the enable signal in each comparison period. The comparison of the positive and negative phase output voltages V1, V2 is started to obtain the difference between the positive and negative phase output voltages V1, V2, and according to the difference between the positive phase and the negative phase output voltages V1, V2 Generating a comparison signal and outputting the comparison signal at its second output, and generating and outputting at the first output thereof while generating the comparison signal A comparison end signal. In this embodiment, the comparator 12 performs six comparisons and generates six comparison signals CS1~CS6 and six comparison end signals, respectively. When the difference between the positive phase output voltage V1 and the corresponding negative phase output voltage V2 is greater than zero, the logic level of the comparison signals CS1~CS6 corresponding to the output of the comparator 12 is one. High logic level. When the difference between the positive phase output voltage V1 and the corresponding negative phase output voltage V2 is less than zero, the logic level of the comparison signals CS1~CS6 corresponding to the output of the comparator 12 is a low logic. Level.

It should be noted that, in this embodiment, a comparison time required by the comparator 12 to generate the comparison end signal in each comparison period is inverted with respect to each positive phase output voltage V1 and each negative phase output voltage. The difference ΔV of V2 (ie, ΔV=V1-V2) is positively correlated with a common mode voltage Vcm (ie, ).

The metastable detection module 13 is electrically connected to the comparator 12 to sequentially receive the comparison end signal generated by the comparator 12 in each comparison period, and generate an indication according to the comparison end signal whether or not the sub-station is generated. A meta-stability detection signal, and the metastable detection module 13 includes a delay circuit 131 and a phase detection circuit 132.

The delay circuit 131 receives the enable signal in each comparison period and delays the enable signal for a predetermined time to generate a delayed signal.

The phase detecting circuit 132 is electrically connected to the comparator 12 and the delay circuit 131 to sequentially receive the comparison end signal generated by the comparator 12 in each comparison period, and sequentially receive the delay circuit 131. The delayed signal generated in a comparison period is compared in each comparison period to compare whether the phase of the comparison end signal is behind the phase of the delayed signal.

In detail, when the phase detecting circuit 132 detects that the phase of the comparison end signal is behind the phase of the delayed signal, the detection signal generated by the phase detecting circuit 132 indicates that metastability occurs. When the phase detecting circuit 132 detects that the phase of the comparison end signal leads the phase of the delayed signal, the detection signal generated by the phase detecting circuit 132 indicates that metastability does not occur.

The continuous approximation temporary memory circuit 14 receives a conversion start signal, and is electrically connected to the comparator 12 to sequentially receive the comparison signals CS1 to CS6 from the comparator 12 in the comparison periods, and electrically connect the metastable signals. The phase detecting circuit 132 of the state detecting module 13 sequentially receives the detecting signal from the phase detecting circuit 132 in each comparison period. The continuous approximation temporary storage circuit 14 generates the enable signal according to the conversion start signal, and outputs the enable signal to the delay circuit 131 and the comparator 12.

When the detection signal corresponding to each comparison period indicates metastability, the continuous approximate temporary storage circuit 14 determines the logic of the positive phase control signal and the bit to be adjusted by the negative phase control signal according to the detection signal. Level. When the detection signal corresponding to each comparison period indicates no metastable state, the continuous approximation temporary storage circuit 14 determines the logic of the bit to be adjusted by the positive phase control signal and the negative phase control signal according to the comparison signal. Bit. The continuous approximation temporary storage circuit 14 outputs the adjusted positive phase control signal and the negative phase control signal to the capacitor array circuit 11. In this embodiment, the bit of the positive phase and the negative phase control signal to be adjusted in the first comparison period It is the first and second bits p1, p2, n1, and n2. The bits to be adjusted of the positive and negative phase control signals in the second comparison period are the third and fourth bits p3, p4, n3, n4. The correspondingly adjusted bits of the positive phase and negative phase control signals in the third to fifth (ie, N-1=5) comparison periods are the fifth to seventh (ie, P=7) bits, respectively. Yuan p5~p7, n5~n7.

The continuous approximation temporary storage circuit 14 performs an addition logic operation on the normal phase control signal and the comparison signal CS6 generated by the comparator 12 in the sixth (ie, N=6) comparison period to generate the six bits. The digital signal of the elements B1 to B6, and outputs a conversion end signal while generating the digital signal.

The signal generating circuit 15 receives a clock signal, and generates the sampling signal and the conversion start signal, and uses the sampling signal and the conversion start signal to trigger the capacitor array circuit 11 and the continuous approximation temporary storage respectively. Circuit 14. The signal generating circuit 15 receives the conversion end signal from the continuous approximation temporary storage circuit 14, and generates a next sampling signal required for the next sampling by the capacitance array circuit 11 based on the conversion end signal and the clock signal.

In detail, the initial logic level of the reset signal is the preset initial logic level (ie, the low logic level), and the first and second inverse gates G1~G7, g1~g7 are The initial logic level of each logic signal output is a high logic level. When the first and second switches 111 and 112 are turned on by the sampling signal, the capacitor array circuit 11 starts sampling and holding to store the positive phase input voltage and the negative phase input voltage received by the capacitor array circuit 11 respectively. First and second capacitors C1~C7, c1~c7, and according to The first positive and negative phase output voltages V1, V2 are generated. The comparator 12 compares the first positive and negative phase output voltages V1, V2 to produce a first comparison signal CS1 while outputting a first comparison end signal.

Then, the phase detecting circuit 132 generates a first detection signal according to the first comparison end signal and the first delay signal, and the continuous approximation temporary storage circuit 14 is based on the first detection signal or the first The comparison signal CS1 generates the bits p1, p2, n1, and n2 of the positive and negative phase control signals to adjust the second positive phase output voltage V1 and the second negative output of the capacitor array circuit 11 for the next time. The magnitude of the phase output voltage V2 to reduce the common mode voltage Vcm (ie, The size of the comparator is simultaneously increased by the comparison speed of the comparator 12. The analog-to-digital conversion apparatus repeatedly performs the above operation to cause the continuous approximation temporary storage circuit 14 to generate the bits p1 to p7, n1 to n7 of the positive and negative phase control signals. Finally, the continuous approximation temporary storage circuit 14 generates the digital signal according to the bits p1~p7 of the positive phase control signal and the comparison signal CS6, and simultaneously generates and outputs the conversion end signal to the signal generating circuit 15 for performing The next analog analog digit conversion.

Referring to the following Tables 1, 2, in this embodiment, the analog-to-digital conversion apparatus performs a six-bit analog-to-digital conversion of the difference ΔV (-63 ≦ ΔV ≦ 63). The normal phase output voltage V1 is equal to the sum of the common mode voltage Vcm and the difference ΔV half (i.e., V1 = Vcm + ΔV/2), and the negative phase output voltage V2 is equal to the difference between the common mode voltage Vcm and the difference ΔV half. (ie, V2 = Vcm - ΔV / 2). The initial value of the common mode voltage Vcm is half of a predetermined reference voltage Vref (ie, Vcm=Vref/2), and the predetermined reference voltage Vref is equal to 63V, but is not limited thereto.

Tables 1 and 2 show that the initial difference ΔV is equal to 63 V, and the analog-to-digital conversion device performs six conversion comparisons as an example to illustrate how the analog-to-digital conversion device performs analog-to-digital conversion.

Compare one:

The difference ΔV is equal to 63V, and the magnitude of the positive phase output voltage V1 is greater than the magnitude of the negative phase output voltage V2. Therefore, the logic level of the comparison signal CS1 output by the comparator 12 is a high logic level. And because the difference ΔV is large, the phase of the first comparison end signal generated by the comparator 12 leads the phase of the first delayed signal (ie, the detection signal indicates that no metastable state has occurred). The continuous approximation temporary storage circuit 14 directly adjusts the logic level of the bits p1 and p2 of the positive phase control signal to a high logic level according to the comparison signal CS1, and the negative phase control signal The logic levels of the bits n1, n2 are different from the logic levels of the bits p1, p2 of the positive phase control signal, and the logic levels of the bits n1, n2 of the negative phase control signal are Low logic level.

Comparison two:

The capacitor array circuit 11 adjusts the magnitude of the positive phase output voltage V1 outputted by the comparison two according to the bits p1 and p2 of the normal phase control signal to compare the positive phase output voltage V1 outputted by the second phase. The size is reduced by a first adjustment value D1 (D1=Vref/2) compared to the magnitude of the output of the positive phase output voltage V1, and the magnitude of the negative phase output voltage V2 outputted by the comparison 2 is maintained. change. At this time, the difference ΔV is equal to 63/2V, the logic level of the comparison signal CS2 is a high logic level, and the phase of the second comparison end signal generated by the comparator 12 leads the phase of the second delayed signal. The continuous approximation temporary storage circuit 14 directly adjusts the logic levels of the bits p3 and p4 of the positive phase control signal to a high logic level according to the comparison signal CS2, and the bits of the negative phase control signal The logic levels of n3 and n4 are different from the logic levels of the bits p3 and p4 of the positive phase control signal, and the logic levels of the bits n3 and n4 of the negative phase control signal are low logic levels.

Compare three:

The phase detecting circuit 132 stops determining whether a metastable condition occurs, and the capacitor array circuit 11 adjusts the positive phase output voltage V1 of the output of the third phase according to the bits p1~p4 of the normal phase control signal. The size is such that the magnitude of the positive phase output voltage V1 outputted by the comparison of the three outputs is reduced by the magnitude of the positive phase output voltage V1 outputted by the comparison two Second, the value D2 is adjusted (D2 = Vref / 4), and the magnitude of the negative phase output voltage V2 outputted by the comparison three remains unchanged. At this time, the difference ΔV is equal to 63/4V, the logic level of the comparison signal CS3 is a high logic level, and the continuous approximation temporary memory circuit 14 uses the bit p5 of the positive phase control signal according to the comparison signal CS3. The logic level is adjusted to a high logic level, and the logic level of the bit n5 of the negative phase control signal is different from the logic level of the bit p5 of the positive phase control signal, the negative phase control signal The logic level of bit n5 is a low logic level.

Compare four:

The capacitor array circuit 11 adjusts the magnitude of the positive phase output voltage V1 outputted by the comparison four according to the bits p1~p5 of the normal phase control signal to compare the positive phase output voltage V1 of the four outputs. The size is reduced by a third adjustment value D3 (D3=Vref/8) compared to the magnitude of the positive phase output voltage V1 outputted by the comparison three, and the magnitude of the negative phase output voltage V2 outputted by the comparison four is maintained. change. At this time, the difference ΔV is equal to 63/8V, the logic level of the comparison signal CS4 is a high logic level, and the continuous approximation temporary memory circuit 14 is the bit p6 of the positive phase control signal according to the comparison signal CS4. The logic level is adjusted to a high logic level, and the logic level of the bit n6 of the negative phase control signal (which is different from the bit p6 of the positive phase control signal) is a low logic level.

Compare five:

The capacitor array circuit 11 adjusts the magnitude of the positive phase output voltage V1 outputted by the comparison five according to the bits p1~p6 of the normal phase control signal to compare the magnitude of the positive phase output voltage V1 output by the five outputs. The fourth adjustment value D4 (D4=Vref/16) is reduced by the magnitude of the positive phase output voltage V1 outputted by the comparison four, and the magnitude of the negative phase output voltage V2 outputted by the comparison five remains unchanged. At this time, the difference ΔV is equal to 63/16V, the logic level of the comparison signal CS5 is a high logic level, and the continuous approximation temporary memory circuit 14 is the bit p7 of the positive phase control signal according to the comparison signal CS5. The logic level is adjusted to a high logic level, and the logic level of the bit n7 of the negative phase control signal (which is different from the bit p7 of the positive phase control signal) is a low logic level.

Compare six:

The capacitor array circuit 11 adjusts the magnitude of the positive phase output voltage V1 outputted by the six comparators according to the bits p1~p7 of the normal phase control signal to compare the positive phase output voltage V1 of the six outputs. The size is reduced by a fifth adjustment value D5 (D5=Vref/32) compared to the magnitude of the positive phase output voltage V1 outputted by the five outputs, and the magnitude of the negative phase output voltage V2 outputted by the six outputs is maintained. . At this time, the difference ΔV is equal to 63/32V, and the logic level of the comparison signal CS6 is a high logic level.

Referring to Table 3 below, after the analog-to-digital conversion device performs six conversion comparisons, the continuous approximation temporary storage circuit 14 performs the addition logic operation on the bits p1~p7 of the positive phase control signal and the comparison signal CS6. To calculate the bits B1 B B6 of the digital signal, and the continuous approximation temporary storage circuit 14 generates and outputs the conversion end signal to the signal generating circuit 15 to generate the sampling signal again, and performs the next analog digital position. Conversion.

table 3:

Referring to Tables 4 and 5 below, which shows that the initial difference ΔV is equal to 1V, and the analog-to-digital conversion device performs six conversion comparisons as an example, how the analog-to-digital conversion device performs analog-to-digital conversion.

Compare one:

The difference ΔV is equal to 1V. Since the difference ΔV is small, the phase of the first comparison end signal generated by the comparator 12 lags behind the phase of the first delayed signal (ie, the detection signal indicates metastable occurrence). In this case, regardless of whether the logic level of the comparison signal CS1 output by the comparator 12 is a high or low logic level, the continuous approximation temporary storage circuit 14 directly directs the positive phase according to the first detection signal. The logic levels of the bits p1 and n1 of the negative phase control signal are adjusted to a low logic level, and the logic levels of the bits p2 and n2 of the positive and negative phase control signals are adjusted to a high logic level. Bit, but not limited to this.

Comparison two:

The capacitor array circuit 11 adjusts the magnitudes of the positive and negative phase output voltages V1 and V2 outputted by the comparison two according to the bits p1, p2, n1, and n2 of the positive and negative phase control signals. The magnitudes of the positive and negative phase output voltages V1, V2 outputted by the comparison two are respectively reduced by a first adjustment value d1 from the magnitude of the positive and negative phase output voltages V1, V2 outputted by the comparison one ( D1=Vref/4). At this time, the difference ΔV is equal to 1V, and since the difference ΔV is small, the phase of the second comparison end signal generated by the comparator 12 lags behind the phase of the second delayed signal (ie, the metastable state occurs). The continuous approximation temporary storage circuit 14 directly adjusts the logic levels of the bits p3 and n3 of the positive and negative phase control signals to a low logic level according to the second detection signal, and the positive phase and The logic levels of the bits p4, n4 of the negative phase control signal are adjusted to a high logic level, but are not limited thereto.

Compare three:

The capacitor array circuit 11 adjusts the magnitudes of the positive and negative phase output voltages V1 and V2 outputted by the comparison three according to the bits p1 to p4 and n1 to n4 of the positive and negative phase control signals. Comparing the magnitudes of the positive and negative phase output voltages V1 and V2 outputted by the three outputs to the magnitudes of the positive and negative phase output voltages V1 and V2 outputted by the comparison two are respectively reduced by a second adjustment value d2 ( D2=Vref/8). At this time, although the difference ΔV is constant, the common mode voltage Vcm (Vcm=63/8) is small, the comparison speed of the comparator 12 can be improved, and the metastable condition is improved, so the continuous approximation is temporarily stored. The circuit 14 directly adjusts the logic level of the bit p5 of the positive phase control signal to a high logic level according to the comparison signal CS3, and sets the logic level of the bit n5 of the negative phase control signal (and the positive The logic level of the bit p5 of the phase control signal is different) is adjusted to a low logic level.

Compare four:

The capacitor array circuit 11 adjusts the magnitude of the positive phase output voltage V1 outputted by the comparison four according to the bits p1~p5 of the normal phase control signal to compare the positive phase output voltage V1 of the four outputs. The size is reduced by a third adjustment value d3 (d3=Vref/8) compared to the magnitude of the positive phase output voltage V1 outputted by the comparison three, and the magnitude of the negative phase output voltage V2 outputted by the comparison four is maintained. change. At this time, the difference ΔV is equal to -55/8V, the logic level of the comparison signal CS4 is a low logic level, and the continuous approximation temporary memory circuit 14 is the bit p6 of the positive phase control signal according to the comparison signal CS4. The logic level is adjusted to a low logic level, and the logic level of the bit n6 of the negative phase control signal (which is different from the logic level of the bit p6 of the positive phase control signal) is adjusted to a high logic level. Bit.

Compare five:

The capacitor array circuit 11 adjusts the magnitude of the negative phase output voltage V2 outputted by the five signals according to the bits n1~n6 of the negative phase control signal to compare the magnitude of the negative phase output voltage V2 output by the five outputs. The fourth adjustment value d4 (d4=Vref/16) is reduced by the magnitude of the negative phase output voltage V2 outputted by the comparison four, and the magnitude of the positive phase output voltage V1 outputted by the comparison five is unchanged. At this time, the difference ΔV is equal to -47/16V, the logic level of the comparison signal CS5 is a low logic level, and the continuous approximation temporary memory circuit 14 is the bit p7 of the positive phase control signal according to the comparison signal CS5. The logic level is adjusted to a low logic level, and the logic level of the bit n7 of the negative phase control signal (which is different from the logic level of the bit p7 of the positive phase control signal) is adjusted to a high logic level. Bit.

Compare six:

The capacitor array circuit 11 adjusts the magnitude of the negative phase output voltage V2 outputted by the six signals according to the bits n1~n7 of the negative phase control signal to compare the negative phase output voltage V2 of the six outputs. The size is reduced by a fifth adjustment value d5 (d5=Vref/32) compared to the magnitude of the negative phase output voltage V2 outputted by the five outputs, and the magnitude of the positive phase output voltage V1 of the six outputs is maintained unchanged. . At this time, the difference ΔV is equal to -31/32V, and the logic level of the comparison signal CS6 is a low logic level.

It should be noted that since the common mode voltage after the comparison 2 is small enough to improve the metastable condition, the comparison three to the fifth can directly generate the corresponding positive and negative corresponding to the comparison signals CS3 to CS5. The bits p5~p7, n5~n7 of the phase control signal.

Referring to Table 6 below, the continuous approximation temporary memory circuit 14 performs the addition logic operation on the bits p1~p7 of the normal phase control signal and the comparison signal CS6 to calculate the bit B1 of the digital signal. ~B6.

It should be noted that the phase detecting circuit 132 generates the detection signal for determining whether a metastable condition occurs when the comparator 12 performs the first two comparisons. When the detection signal indicates that metastability has not occurred, the continuous approximation temporary storage circuit 14 directly generates the pixels p1~p7, n1~n7 of the positive and negative phase control signals according to the comparison signals CS1~CS5. . When the detection signal indicates that a metastable state occurs, the continuous approximation temporary storage circuit 14 directly adjusts the logic levels of the bits p1, p3, n1, and n3 of the positive and negative phase control signals to a low logic level. Bits, and adjust the logic levels of the bits p2, p4, n2, n4 of the positive and negative phase control signals to a high logic level (or the bits of the positive and negative phase control signals) The logic levels of p1, p3, n1, and n3 are adjusted to a high logic level, and the logic levels of the bits p2, p4, n2, and n43 of the positive and negative phase control signals are adjusted to a low logic level. And generating the normal phase and negative phase control signals of the normal bits p5~p7, n5~n7 according to the comparison signals CS3~CS5 for analog digital conversion.

In summary, by using the phase detecting circuit 132 to perform phase detection on the delay circuit 131 and the delay signals generated by the comparator 12 and the comparison end signals, it can be determined whether the comparator 12 is hair In the case of a metastable state, the continuous approximation register circuit 14 can adjust the bits p1~p4, n1~n4 of the positive and negative phase control signals when the comparator 12 is in a metastable state. The logic level is used to reduce the magnitude of the common mode voltage Vcm of the comparator 12 to increase the comparison speed of the comparator 12, and at the same time, the conversion speed of the analog-to-digital conversion device is increased, so that the present invention can be achieved. The purpose.

The above is only the preferred embodiment of the present invention, and the scope of the present invention is not limited thereto, that is, the simple equivalent changes and modifications made by the patent application scope and patent specification content of the present invention, All remain within the scope of the invention patent.

11‧‧‧Capacitor array circuit

12‧‧‧ comparator

13‧‧‧ Metastable Detection Module

131‧‧‧Delay circuit

132‧‧‧ phase detection circuit

14‧‧‧Continuous approximation temporary storage circuit

15‧‧‧Signal generation circuit

Claims (9)

An analog-to-digital conversion device receives a positive phase input voltage and a negative phase input voltage, and accordingly generates a digital signal having N bits, N≧3, and N is a positive integer, and includes: a capacitor array circuit And sequentially operating in the N comparison periods, and receiving the normal phase input voltage, the negative phase input voltage, a positive phase control signal, and a negative phase control signal, the positive phase and the negative phase control signal each having P bits Yuan, P=N+1, and in each comparison period, the capacitor array circuit determines an amplitude of the positive phase input voltage to be decremented according to a logic level of each bit of the normal phase control signal, Generating a positive phase output voltage, the capacitor array circuit determining a magnitude of the negative phase input voltage to be decremented according to a logic level of each bit of the negative phase control signal to generate a negative phase output voltage; And electrically connecting the capacitor array circuit to sequentially receive the positive and negative phase output voltages generated by the capacitor array circuit in each comparison period, and output the positive phase and the negative phase according to each comparison period Voltage difference Generating a comparison signal, and outputting a comparison end signal while generating the comparison signal; a metastable detection module electrically connecting the comparator to sequentially receive the comparator generated in each comparison cycle The comparison end signal, and according to the comparison end signal, a detection signal indicating whether a metastable state is generated; and a continuous approximation temporary storage circuit, electrically connecting the comparators to sequentially connect Receiving the comparison signal from the comparator in each comparison period, electrically connecting the metastable detection module to sequentially receive the detection signal from the metastable detection module in each comparison period When the detection signal indicates a metastable state, the continuous approximation temporary storage circuit determines a logic level of the bit element to be adjusted by the positive phase control signal and the negative phase control signal according to the detection signal; wherein, the positive Each of the phase control signal and the negative phase control signal has a predetermined initial logic level, the N comparison periods including first to Nth comparison periods, the positive and negative phases in the first comparison period The bit to be adjusted of the control signal is the first and second bits; the bit to be adjusted of the positive and negative phase control signals in the second comparison period is the third and fourth bits; the third The correspondingly adjusted bits of the positive phase and negative phase control signals in the (N-1)th comparison period are fifth to Pth bits, respectively; the continuous approximate temporary storage circuit is based on the positive phase control signal and the Comparing a comparison signal generated by the comparator in the Nth comparison period Logical operation to generate the digital signal having N bits. The analog-to-digital conversion device of claim 1, wherein when the detection signal indicates no metastable state, the continuous approximation temporary storage circuit determines that the positive phase control signal and the negative phase control signal are to be adjusted according to the comparison signal. The logical level of the bit. The analog-to-digital conversion device of claim 1, wherein the continuous approximation temporary storage circuit performs an addition logic operation on the positive phase control signal and the comparison signal generated by the comparator in the Nth comparison period. The analog-to-digital conversion device of claim 1, wherein the metastable detection module comprises: a delay circuit, receiving a uniform energy signal in each comparison period, and delaying the enable signal by a preset time And generating a delay signal; and a phase detecting circuit electrically connecting the comparator and the delay circuit to sequentially receive the comparison end signal generated by the comparator in each comparison period, and sequentially receiving the The delay circuit generates the delayed signal generated in each comparison period, and compares whether the phase of the comparison end signal lags behind the phase of the delayed signal in each comparison period; when the phase of the comparison end signal lags behind the phase of the delayed signal The detection signal generated by the phase detecting circuit indicates that metastability occurs. The analog digital conversion device of claim 4, further comprising: a signal generating circuit, receiving a clock signal, and generating a sampling signal and a conversion starting signal, and combining the sampling signal and the conversion starting signal The trigger array circuit and the continuous approximate temporary storage circuit are respectively triggered. The analog-to-digital conversion device of claim 5, wherein the capacitor array circuit further receives the sampling signal from the signal generating circuit, and samples the normal phase input voltage and the negative phase input voltage according to the sampling signal; Wherein, the continuous approximation temporary storage circuit receives more from the signal production Generating the conversion start signal, and generating the enable signal according to the conversion start signal, and outputting the enable signal to the delay circuit and the comparator, and the comparator is further based on each comparison period The enable signal begins to compare the positive and negative phase output voltages to obtain a difference between the positive and negative phase output voltages. The analog-to-digital conversion device of claim 6, wherein the continuous approximation temporary storage circuit outputs a conversion end signal while generating the digital signal. The analog-to-digital conversion device of claim 7, wherein the signal generating circuit further receives the conversion end signal from the continuous approximation temporary storage circuit, and generates the capacitance array circuit according to the conversion end signal and the clock signal. The next sampled signal required for the next sample. The analog-to-digital conversion device of claim 5, wherein N=6, P=7, and the capacitor array circuit comprises: a first switch having a first end receiving the positive phase input voltage, and a first Outputting a second end of the positive phase output voltage for each comparison period, and being turned on or off by the sampling signal; seven first capacitors, each of the first capacitors having an electrical connection to the second of the first switches a first end of the end, and a second end; seven first anti-gates, each of the first anti-gates having a first end, a second end, and a third end receiving a reset signal The second ends of the first NAND gate respectively receive the corresponding bits of the corresponding positive phase control signal, and the third ends of the first NAND gates Electrically connecting the second ends of the first capacitors corresponding to the respective ones, and each of the first and second gates is in accordance with the reset signal and the corresponding one of the positive phase control signals received by the reset signal a third end thereof outputs a first logic signal; a second switch has a first end receiving the negative phase input voltage, and a second end outputting the negative phase output voltage in each comparison period, and is subjected to The sampling signal is controlled to be turned on or off; seven second capacitors each having a first end electrically connected to the second end of the second switch, and a second end; and seven second counters And a second gate having a first end, a second end, and a third end receiving the reset signal, wherein the second ends of the second anti-gates respectively receive the respective Corresponding to the bits of the negative phase control signal, the third ends of the second anti-gates are electrically connected to the second ends of the second capacitors respectively corresponding to each, and each second And the gate is based on the reset signal and the corresponding one of the negative phase control signals received in the gate Terminal, a second logic output signal; wherein an initial logic level of the reset signal for the preset initial logical level.