JP3099312B2 - Phase detection circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase detection circuit for reading a phase difference between AC waves such as AC voltage and current waveforms into a microprocessor.

[0002]

2. Description of the Related Art As a conventional phase detection circuit, for example, there are circuits shown in FIGS. In FIG. 4, the AC voltage waveform v and the AC current waveform i
The waveforms are shaped into small positive and negative rectangular waves ID ₁ and VD ₁ by i and 1v, and are shaped into large rectangular waves ID ₂ and VD ₂ only by the positive electrode by the second comparison circuits 2 i and 2 v. Among, VD to the ID ₁ by the first comparator circuit 1i according to the second comparative circuit 1v
And _two third comparator circuit 3a in the AC waveform v, a rectangular wave D ₁ that is proportional to i of the phase, the phase clock signal DC takes the AND between the rectangular wave D ₁ and the clock signal CL at the AND circuit 10a And the signal DC is counted up by the advance counter 11a. Then, the rise detection circuit 6
The latch signal LA made by the rise of the rectangular wave VD ₂ at a latches the count value of the counter 11a.
The counter 11a is reset by a reset signal RE obtained by delaying the latch signal LA by the delay circuit 13a. When the AC current waveform i is ahead of the AC voltage waveform v by this series of circuit operations, the latch circuit 12a latches the phase difference with an accuracy proportional to the clock frequency, and C
It can be read by PU9.

The waveforms in FIGS. 5 (1) to 5 (7) are AC i
Is ahead of v, the rectangular waves ID ₁ and VD ₂ are obtained, the phase difference D ₁ is obtained, and the A of the clock signals CL and D ₁ is obtained.
Each waveform is obtained by taking ND, latching the clock count with a latch signal LA, and then resetting the counter 11a with a reset signal RE.

However, when the AC waveform i is behind the AC waveform v, the count value is smaller than the phase difference, and the phase difference varies depending on the delay time of the reset signal.
Thus, VD ₁ by the first comparator circuit 1 v, to give the ID ₂ by the second comparator circuit 2i, seek waveform corresponding to the phase difference by the third comparator circuit 3b, the clock signal at the AND circuit 10b The AND operation is performed to count by the delay counter 11b and latch by the latch circuit 12b. The first and second comparison circuits 1v and 2i are opposite to the circuits 1i and 2v to obtain the phase difference of the delay signal. ing. Then, the determination of the advance or the delay is made by adopting the larger one of the latch circuits 12a and 12b.

[0005]

As described above, in the phase detection circuit shown in FIG.
1a, 11b or the latch circuits 12a, 12b
When they are large in scale and coexist with a circuit for A / D converting the magnitude of the signal and reading it into the CPU 9, the apparatus becomes large and expensive.

In view of the above problems, the present invention provides a phase detection circuit capable of detecting a phase difference in the same way as A / D-converting a signal magnitude and reading it into a CPU so that the apparatus is not large and expensive. Aim.

[0007]

In order to achieve the above-mentioned object, the present invention outputs a DC high voltage only when one of two types of AC waveform signals has a positive polarity, and outputs a zero voltage when the polarity is negative and zero. A first comparison circuit, a second comparison circuit that outputs the other AC waveform signal as a positive or negative DC low voltage according to each of the positive and negative polarities,
A third comparing circuit for comparing the magnitude of each output waveform of the first comparing circuit and the second comparing circuit; and a negative voltage when the output of the second comparing circuit is larger than the comparison output of the third comparing circuit. An integrating circuit for inverting and integrating and discharging at a positive voltage; a peak hold circuit for detecting a rise of the third comparing circuit to peak hold the output voltage of the integrating circuit; And an A / D converter that converts the data into an A / D converter.

The present invention also provides a first comparison circuit which outputs a DC high voltage only when one of two types of AC waveform signals has a positive polarity and outputs a zero voltage when the polarity is negative and zero, and a second comparison circuit which outputs the other AC waveform signal. A second comparator for outputting a positive or negative DC low voltage according to each of the positive and negative polarities; a DC positive voltage is output when the output of the second comparator is greater than the output of the first comparator; and a zero voltage is output otherwise. A fourth comparison circuit, and a pulse obtained at the rising edge of the first comparison circuit or the second comparison circuit.
The gist of the present invention is to include a peak hold circuit for peak holding the output voltage of the comparison circuit, and an A / D converter for converting an analog output of the peak hold circuit into digital.

The gist of the present invention is that a circuit for integrating the positive voltage output from the fourth comparison circuit and performing A / D conversion is provided.

[0010]

[Function] The two types of AC waveforms are divided into a high voltage positive polarity and a low voltage positive / negative polarity, and all the comparison circuits are used as a circuit for comparing the magnitudes thereof. The phase difference and the lead / lag can be taken out, and can be easily read at an arbitrary timing by the microprocessor after the A / D conversion.

[0011]

An embodiment of the present invention will now be described with reference to FIGS. In FIG. 1, a second comparison circuit 20 to which an AC current waveform i is input shapes the AC waveform i into a low positive and negative rectangular wave ID, and a first comparison circuit 21 to which an AC voltage waveform v is input is , The AC waveform v is a positive high rectangular wave VD
Is to be formatted.

Further, the comparison circuits 22 and 23 include a comparison circuit 2
ID and VD, which are the outputs of 0 and 21, respectively, are input to perform magnitude comparison. As the third comparison circuit 22, the output ID of the second comparison circuit 20 is larger than the output VD of the first comparison circuit 21. Only when a negative voltage is output, a positive / negative rectangular wave DS is obtained.

The fourth comparing circuit 23 generates a DC positive voltage D when the positive / negative rectangular wave which is the output waveform of the second comparing circuit 20 is larger than the positive rectangular wave which is the output waveform of the first comparing circuit 21. In this case, a zero voltage output is obtained.

The integrating circuit 24 inverts and integrates the output DS of the third comparing circuit 22 with a negative voltage, and discharges the output DS to zero voltage when the voltage is positive. Further, a rising detection circuit 25 for detecting a positive rising of the output DS of the third comparison circuit 22.
, And a hold signal SP is obtained from the rise detection circuit 25.

In the peak hold circuit 26, the integration circuit 2
4 is peak-held by the hold signal SP to obtain an output signal DH. On the other hand, the output D of the fourth comparison circuit 23 is held by the peak hold circuit 27 to obtain the output signal LD. The hold signal at this time is obtained by the rise detection circuit 28 for detecting the rise of the positive / negative rectangular wave ID of the second comparison circuit 20.

The outputs DH and LD of the peak hold circuits 26 and 27 are A / D-converted by an A / D converter 28 together with another analog signal lv, and the digital signal is converted by the CPU.
30 is input. The A / D converter 29 is started at an arbitrary timing, and a digital value is read into the CPU 30.

FIG. 2 shows a waveform when the AC current waveform i leads the AC voltage waveform v by 30 ° in the configuration shown in FIG. The waveform (1) is an original current or voltage waveform i, v, and the output ID of the second comparison circuit 20 and the first
The output VD of the comparison circuit 21 is the waveform (2). A waveform (3) is an output DS of the third comparison circuit 22 for performing a magnitude comparison between the output ID and VD, and a negative voltage corresponding to a phase difference is output. The waveform (4) is the inversion integral value SD of the negative voltage by the integration circuit 24. On the other hand, the rising signal of the output DS which is the waveform (3) is detected, and the hold signal SP is shown by the waveform (5).
As a result, the peak of the signal SD of the waveform (4) corresponding to the phase difference is held, and the signal DH as the output waveform (6) is obtained.
That is, the phase difference DH is obtained.

On the other hand, the output voltage D of the fourth comparison circuit 23 is
As shown in the waveform (7), since it is obtained only when the output ID is larger than the output VD, an ID advanced output D is obtained. Then, the output D is obtained as shown by a waveform (8) using the hold signal IP at the rise of the ID, and the peak hold signal LD is obtained as shown by a waveform (9).

Thus, the peak hold signals DH and LD
Is read into the CPU as a digital value by the A / D converter 29, the digital value of this signal DH becomes a value proportional to the phase difference between the AC waveforms i and v, and the digital value of the signal LD becomes When the waveform i is ahead of v and lags behind, the count is zero.

Next, FIG. 3 shows a case where the AC voltage waveform v is ahead of the AC current waveform i. In the waveform (1), the ID and VD of the waveform (2) are obtained and ID> VD. As a result, the negative voltage DS shown in the waveform (3) is output. Thereafter, the output SD shown in the waveform (4) is obtained by inversion integration by the integration circuit 24.
To obtain a peak hold output DH (waveform (6)) corresponding to the phase difference by the hold signal SP.

On the other hand, the output D obtained only when the output ID is larger than the output VD is obtained as the output of the fourth comparison circuit 23 as shown in a waveform (7). However, since the ID is delayed from the VD, the waveform (8) is obtained. Is different from the output D, and the output of the peak hold circuit 27 shown in the waveform (9) remains at zero potential.

That is, while the phase difference DH is obtained,
i becomes later than v and LD becomes zero potential. In the above description, the lead and lag between the AC waveforms are detected based on the presence / absence of the peak hold output LD. However, a circuit that detects and latches the rising time of VD and may detect it. Further, although the inversion integration of the positive and negative rectangular waves of the output DS is performed, the same applies to a circuit that converts the phase difference into an analog level by integrating the positive rectangular waves of the output D.

[0023]

As described above, according to the present invention, it is possible to obtain the phase difference and the advance / delay of the AC waveform iv without using a clock generator, a counter, a latch circuit and the like as in the prior art.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a waveform diagram in a state where an AC waveform i is advanced by 30 °.

FIG. 3 is a waveform diagram in a state where an AC waveform i is delayed by 45 °.

FIG. 4 is a block diagram of a conventional example.

FIG. 5 is a waveform diagram in a conventional example.

[Explanation of symbols]

 Reference Signs List 20 second comparison circuit 21 first comparison circuit 22 third comparison circuit 23 fourth comparison circuit 24 integration circuit 25, 28 rising detection circuit 26, 27 peak hold circuit 29 A / D converter 30 CPU

Claims (3)

(57) [Claims] 1. A first comparison circuit for outputting a DC high voltage only when one of two types of AC waveform signals has a positive polarity and outputting a zero voltage when negative and zero, and the other AC waveform signal having a positive and negative polarity. A second comparator circuit that outputs a positive or negative direct current low voltage, a third comparator circuit that compares the magnitude of each output waveform of the first comparator circuit and the second comparator circuit, and a comparison output of the third comparator circuit. And an integration circuit for inverting and integrating the negative voltage when the output of the second comparison circuit is larger and discharging with a positive voltage, and further detecting the rising of the third comparison circuit to peak the output voltage of the integration circuit. A phase detection circuit comprising: a peak hold circuit that holds the signal; and an A / D converter that converts an analog output of the peak hold circuit into a digital signal. 2. A first comparison circuit for outputting a DC high voltage only when one of two types of AC waveform signals has a positive polarity, and outputting a zero voltage when negative and zero, and the other AC waveform signal having a positive and negative polarity. A second comparison circuit for outputting a positive or negative DC low voltage in response to the second comparison circuit; and a fourth comparison circuit for outputting a DC positive voltage when the output of the second comparison circuit is larger than the output of the first comparison circuit and outputting a zero voltage otherwise. A peak hold circuit for peak-holding the output voltage of the fourth comparison circuit with a pulse obtained at the rising edge of the first comparison circuit or the second comparison circuit; and converting an analog output of the peak hold circuit to digital. An A / D converter, and a phase detection circuit. 3. The phase detection circuit according to claim 2, further comprising a circuit for integrating the positive voltage output from the fourth comparison circuit and performing A / D conversion.