KR960019223A - Data Extraction Circuit of Digital Magnetic Recording & Reproduction System - Google Patents

Data Extraction Circuit of Digital Magnetic Recording & Reproduction System Download PDF

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Publication number
KR960019223A
KR960019223A KR1019940028730A KR19940028730A KR960019223A KR 960019223 A KR960019223 A KR 960019223A KR 1019940028730 A KR1019940028730 A KR 1019940028730A KR 19940028730 A KR19940028730 A KR 19940028730A KR 960019223 A KR960019223 A KR 960019223A
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KR
South Korea
Prior art keywords
output
pulse width
data
pulse
data extraction
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KR1019940028730A
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Korean (ko)
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KR0132483B1 (en
Inventor
이주석
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이헌조
엘지전자 주식회사
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Priority to KR1019940028730A priority Critical patent/KR0132483B1/en
Publication of KR960019223A publication Critical patent/KR960019223A/en
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Publication of KR0132483B1 publication Critical patent/KR0132483B1/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/10009—Improvement or modification of read or write signals
    • G11B20/10018—Improvement or modification of read or write signals analog processing for digital recording or reproduction
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/10009—Improvement or modification of read or write signals
    • G11B20/10037—A/D conversion, D/A conversion, sampling, slicing and digital quantisation or adjusting parameters thereof
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/10009—Improvement or modification of read or write signals
    • G11B20/10268—Improvement or modification of read or write signals bit detection or demodulation methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/22—Signal processing not specific to the method of recording or reproducing; Circuits therefor for reducing distortions

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  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Signal Processing For Digital Recording And Reproducing (AREA)

Abstract

본 발명은 디지탈 자기기록재생시스템의 데이타 추출회로에 관한 것으로, 종래 데이타 추출부가 고정 비교레벨에 의한 비교기를 사용함으로써 입력의 왜란발생시 정확한 데이타 추출이 곤란하던 점을 감안하여 본 발명은 입력신호를 3치판정하는 3치판정부, 상기 3치판정부의 출력을 전압으로 변환하는 펄스폭 전압변환부, 상기 펄스폭 전압변환부의 출력을 설정되어 있는 비교레벨과 비교하여 특정폭의 펄스임을 나타내는 신호를 출력하는 펄스폭 판단부, 상기 3치판정부의 데이타 출력을 상기 펄스폭 전압변환부와 펄스폭 판단부의 처리기간동안 딜레이시키는 딜레이부, 상기 딜레이부로부터의 데이타를 상기 펄스폭 판단부의 출력으로 클럭에 동기시켜 출력하는 데이타 출력부로 데이타 추출부를 구성하는 데이타 추출부의 비교기의 출력이 T폭펄스나 2T폭펄스인가를 정확히 판단하여 데이타 추출부의 출력으로 정확히 T폭펄스나 2T폭펄스를 내보냄으로써 정확한 데이타 추출이 이루어질 수 있도록 한 것이다.The present invention relates to a data extraction circuit of a digital magnetic recording and reproducing system, and in view of the fact that it is difficult to accurately extract data when a disturbance occurs in the input by using a comparator with a fixed comparison level, the present invention provides an input signal based on 3 data. A value indicating a pulse of a specific width by comparing the output value of the three-valued judgment part, the pulse width voltage conversion part for converting the output of the three-valued judgment part to a voltage, and the output of the pulse width voltage conversion part with a set comparison level. A pulse width determining unit, a delay unit for delaying the data output of the ternary judgment unit during the processing period of the pulse width voltage converting unit and the pulse width determining unit, and synchronizing data from the delay unit to a clock as an output of the pulse width determining unit. The output of the comparator of the data extraction unit constituting the data extraction unit is a T output pulse. Or to the exact width by 2T pulse it is determined whether to be the exact data extracted by exporting the correct pulse width T or 2T pulse width to the output extracting portions of data.

Description

디지탈 자기기록재생시스템의 데이타 추출회로Data Extraction Circuit of Digital Magnetic Recording & Reproduction System

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제4도는 본 발명에 따른 디지탈 자기기록재생시스템의 데이타 추출회로의 블럭 구성도,4 is a block diagram of a data extraction circuit of the digital magnetic recording and reproducing system according to the present invention;

제5도는 제4도의 펄스폭 전압변환부의 상세 구성도,5 is a detailed configuration diagram of the pulse width voltage converter of FIG. 4;

제6도는 제4도의 펄스폭 판단부의 상세 구성도.6 is a detailed block diagram of the pulse width determining unit of FIG.

Claims (5)

입력신호를 3치판정하는 3치판정수단과, 상기 3치판정수단의 출력을 전압으로 변환하는 펄스폭 전압변환수단과, 상기 펄스폭 전압변화수단의 출력을 설정되어 있는 비교레벨과 비교하여 특정폭의 펄스임을 나타내는 신호를 출력하는 펄스폭 판단수단과, 상기 3치판정수단의 데이타 출력을 상기 펄스폭 전압변환수단과 펄스폭 판단수단의 처리기간동안 딜레이시키는 딜레이수단과, 상기 딜레이수단으로부터의 데이타를 상기 펄스폭 판단 수단의 출력신호로써 클럭에 동기시켜 출력하는 데이타 출력수단으로 구성됨을 특징으로 하는 디지탈 자기기록재생시스템의 데이타 추출회로.A third value determining means for determining an input signal in three values, a pulse width voltage converting means for converting the output of the three value determining means into a voltage, and an output of the pulse width voltage changing means in comparison with a predetermined comparison level. Pulse width judging means for outputting a signal indicating a pulse of width, delay means for delaying the data output of the ternary judging means during the processing period of the pulse width voltage converting means and the pulse width judging means, and from the delay means. And data output means for outputting data in synchronization with a clock as an output signal of the pulse width determining means. 제1항에 있어서, 상기 펄스폭 전압변환수단은 입력신호를 반전하는 인버터와, 상기 인버터의 출력에 따라 스위칭되는 스위칭부와, 상기 스우칭부의 출력에 따라 충방전되는 콘덴서와, 상기 인버터 출력의 플링에지에서 상기 콘덴서의 충전전압을 출력하는 데이타 홀드부로 구성됨을 특징으로 하는 디지탈 자기기록재생시스템의 데이타 추출회로.2. The apparatus of claim 1, wherein the pulse width voltage converting means comprises: an inverter for inverting an input signal, a switching unit switched according to an output of the inverter, a capacitor charged and discharged according to an output of the switching unit, and an output of the inverter output. A data extraction circuit of a digital magnetic recording and reproducing system, characterized in that it comprises a data holding section for outputting a charging voltage of the capacitor at a fling edge. 제2항에 있어서, 상기 스위칭부는 상기 인버터의 출력이 로우일 경우 턴온되는 PMOS와, 상기인버터의 출력이 하이일 경우 턴온되는 NMOS로 구성됨을 특징으로 하는 디지탈 자기기록재생시스템의 데이타 추출회로.3. The data extracting circuit of claim 2, wherein the switching unit comprises a PMOS turned on when the output of the inverter is low and an NMOS turned on when the output of the inverter is high. 제1항에 있어서, 상기 펄스폭 판단부는 제1∼제4가변저항에 의해 정해지는 서로 다른 비교레벨을 갖는 제1∼제4비교기와, 상기 제1, 제2비교기의 출력을 논리곱하는 제1앤드 게이트와, 상기 제3, 제4비교기의 출력을 논리곱하는 제2앤드 게이트로 구성됨을 특징으로 하는 디지탈 자기기록재생시스템의 데이타 추출회로.The first and fourth comparators having different comparison levels determined by the first to fourth variable resistors, and the first to logically multiply the outputs of the first and second comparators. And an AND gate, and a second AND gate for performing an AND operation on the outputs of the third and fourth comparators. 제1항에 있어서, 상기 펄스폭 판단부의 특정폭의 펄스임을 나타내는 신호의 시스템에 따라 정해짐을 특징으로 하는 디지탈 자기기록재생시스템의 데이타 추출회로.The data extraction circuit according to claim 1, wherein the data extraction circuit of the digital magnetic recording and reproducing system is determined according to a signal system indicating that the pulse width determining unit is a pulse having a specific width. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940028730A 1994-11-03 1994-11-03 Data retrieving circuit for digital magnetic recording/reproducing system KR0132483B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019940028730A KR0132483B1 (en) 1994-11-03 1994-11-03 Data retrieving circuit for digital magnetic recording/reproducing system

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Application Number Priority Date Filing Date Title
KR1019940028730A KR0132483B1 (en) 1994-11-03 1994-11-03 Data retrieving circuit for digital magnetic recording/reproducing system

Publications (2)

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KR960019223A true KR960019223A (en) 1996-06-17
KR0132483B1 KR0132483B1 (en) 1998-04-18

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101400931B1 (en) * 2012-12-24 2014-05-29 전자부품연구원 Method and apparatus for processing and restoring wide-range signal using stationary-data-rate algorithm

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100721545B1 (en) * 2001-12-31 2007-05-23 주식회사 하이닉스반도체 Pulse Width mismatch detector

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101400931B1 (en) * 2012-12-24 2014-05-29 전자부품연구원 Method and apparatus for processing and restoring wide-range signal using stationary-data-rate algorithm

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