KR100756807B1 - Method for manufacturing semiconductor device - Google Patents

Abstract

A method for fabricating a semiconductor device is provided to prevent a bridge from being formed between cells by forming a cell isolation layer and then forming a landing plug. A first interlayer oxide layer is formed on a substrate(100) having an isolation film and a gate line(120), and then is etched to form a cell isolation layer forming region perpendicular to the gate line. A nitride layer burying the cell isolation layer forming region, and then is etched to form a cell isolation layer. The exposed first interlayer oxide layer is removed by using the cell isolation layer to form a landing plug contact hole which is buried to form a landing plug(145).

Description

Method for manufacturing a semiconductor device {METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE}

1 is a plan view showing a method of manufacturing a semiconductor device according to the present invention.

2A to 2H are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.

The present invention relates to a method for manufacturing a semiconductor device, and after forming a cell separator in a direction perpendicular to a gate line, performing a landing plug forming process to prevent the occurrence of bridge phenomenon between cells, and using the cell separator as a mask as an interlayer oxide layer. After removal of the present invention, a landing plug may be formed to prevent a reduction in the area of a short axis, thereby securing a process margin.

In the method of manufacturing a semiconductor device according to the related art, a gate line is formed on a semiconductor substrate provided with an active region, and an interlayer oxide film is formed on the entire surface.

Next, after forming the landing plug contact hole pattern, the interlayer oxide layer having the pattern as a mask is etched to form a landing plug contact hole.

Next, after forming a polysilicon layer filling the landing plug contact hole, a CMP process is performed to form a cell transistor.

In the above-described method of manufacturing a semiconductor device according to the related art, the landing plug is formed between the gate lines. The inter-cell bridge is shortened due to the shorter line width of the lower gate line or the short axis length due to the instability of the patterning process of the landing plug contact hole. As a phenomenon occurs and the shortened length is shortened, the exposed area of the cell is reduced, thereby increasing resistance, making it difficult to stabilize the process and secure a process margin.

In order to solve the above problems, after forming the cell separation film in a direction perpendicular to the gate line, a landing plug forming process is performed to prevent the occurrence of bridge phenomenon between cells, and after removing the interlayer oxide film using the cell separation film as a mask, the landing plug. It is an object of the present invention to provide a method for manufacturing a semiconductor device that can form a to prevent the reduction of the area of the short axis to ensure a process margin.

Method for manufacturing a semiconductor device according to the present invention
Forming a planarized first interlayer oxide film on the semiconductor substrate including the device isolation layer and the gate line;
Etching the first interlayer oxide layer to form a cell separation region in a direction perpendicular to the gate line;
Forming a cell separator by forming a nitride film filling the predetermined region of the cell separator and then planarizing etching;
Removing the first interlayer oxide film exposed using the cell separator as a mask to form a landing plug contact hole;
And filling the landing plug contact hole to form a landing plug.
The device isolation layer is formed to a thickness of 500 to 1000P using any one selected from HDP, SOD or a combination thereof,
The first interlayer oxide film is one of BPSG, SOD, or HDP;
The cell separator predetermined region is etched to a depth of more than 0 and 1000 Å based on the semiconductor substrate
The nitride film is formed to a thickness of 100 to 3000Å,
The forming of the landing plug contact hole may be performed to expose a semiconductor substrate.
The exposed semiconductor substrate is etched to a depth of 50 to 1000Å,
The cell separator is formed using a line type or hole type mask,
The landing plug is formed using a polysilicon layer, SPE or SEG film,
The landing plug is formed to a thickness of 500 to 3000Å,
Forming a second interlayer oxide film on the entire surface of the semiconductor substrate including the landing plug after the forming of the landing plug;
The second interlayer oxide film is formed of SOD, HDP, and BPSG film.
In addition, the semiconductor device according to the present invention
A semiconductor substrate having an active region, an isolation layer, and a gate line;
A plurality of cell separators provided on the device isolation layer between the gate lines;
And a landing plug provided on the active region through a first interlayer oxide layer between the gate line and the cell separator.
The cell separator is provided in the line type or hole type,
The line type is provided in a direction perpendicular to the gate line,
The cell separator is formed of a nitride film,

The landing plug is formed using a polysilicon layer, SPE or SEG film.
Hereinafter, with reference to the accompanying drawings an embodiment of the present invention will be described in detail.

delete

delete

delete

delete

delete

delete

delete

delete

delete

delete

delete

delete

delete

delete

delete

delete

delete

delete

delete

delete

delete

delete

delete

delete

delete

delete

1 is a plan view illustrating a method of manufacturing a semiconductor device according to the present invention.

Referring to FIG. 1, a gate line 120 is provided on a semiconductor substrate 100 including an isolation layer and an active region 105, and a cell isolation layer 140 that is a nitride film in a direction perpendicular to the gate line 120. ) Is provided, and a landing plug is provided through an interlayer oxide layer between the active region 105 and the gate line 120.

2A to 2H are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the present invention, and FIG. 2C to FIG. 2H are cross-sectional views illustrating a cut plane taken along the line X-X of FIG. 1. Ii) of FIG. 2C is a cross-sectional view illustrating a cutting plane taken along the line Y-Y of FIG. 1.

Referring to FIG. 2A, an active region 105 and an isolation layer are defined in the semiconductor substrate 100.

Here, the device isolation layer is formed to a thickness of 500 to 10000Å, and formed by using any one selected from a high speed wet spin on dielectric (SOD) oxide, a low wet HDP (High Density Plasma) oxide film, or a combination thereof. do.

Next, after the ion implantation process is performed on the entire surface of the semiconductor substrate 100 to form a well, the recess gate region is formed by etching the semiconductor substrate 100 in the gate line predetermined region to a depth of 300 to 3000 Å.

A gate oxide layer of 30 to 300 kW is formed on the entire surface of the semiconductor substrate including the recess gate region, and the gate line 120 is formed in a stacked structure of a gate polysilicon layer, a tungsten silicide layer, and a hard mask layer.

Next, a spacer is formed on the sidewall of the gate line 120.

Referring to FIG. 2B, the first interlayer oxide film 125 is formed on the entire surface and planarized by performing a CMP process.

Here, the first interlayer oxide film 125 is formed to have a thickness of 300 to 5000 mW using a BPSG, SOD or HDP oxide film, and the CMP process has a thickness of 0 to 2000 mW based on the hard mask layer on the gate line 120. The first interlayer oxide film 125 is left.

Referring to FIG. 2C, the first interlayer oxide layer 125 in the predetermined region of the cell separator is etched in a direction perpendicular to the gate line 120.

In this case, the cell separation layer predetermined region is preferably formed by performing an exposure and development process using a mask of a line type or a hole type, and a depth of more than 0 to 1000 microns is preferably etched based on the semiconductor substrate.

Referring to FIG. 2D, a nitride film filling the cell separator predetermined region is formed.

In this case, the nitride film is preferably formed to have a thickness of 100 to 3000 kPa from above the first interlayer oxide film 125.

Referring to FIG. 2E, the CMP process is performed to planarize until the hard mask layer of the first interlayer oxide film 125 or the gate line 120 is exposed.

Referring to FIG. 2F, the landing plug contact hole 143 is formed by removing all of the first interlayer oxide film 125 exposed by using the cell separator 140 formed of the nitride film as a mask.

At this time, the removal of the first interlayer oxide film 125 allows the semiconductor substrate to be etched 50 to 1000 Å so that the semiconductor substrate is sufficiently exposed.

Referring to FIG. 2G, the landing plug contact hole 143 is embedded to form the landing plug 145.

Here, the landing plug is formed using a polysilicon layer, a solid phase epitaxy (SPE) or a selective epitaxial growth (SEG) film, and has a thickness of 500 to 3000 mW.

Referring to FIG. 2H, the second interlayer oxide film 150 is formed on the entire surface and then planarized.

Here, the second interlayer oxide film 150 is preferably formed of SOD, HDP and BPSG (BoroPhosphorus Silicate Glass) films.

The method of manufacturing a semiconductor device according to the present invention has an effect of preventing a bridge phenomenon by forming a cell isolation layer using a nitride film after forming a gate line, and maximizing an exposed area of a source / drain region to prevent an increase in resistance due to an area decrease.

In addition, a preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as belonging to a range.

Claims (17)

Forming a planarized first interlayer oxide layer on the semiconductor substrate including the device isolation layer and the gate line; Etching the first interlayer oxide layer to form a cell isolation region in a direction perpendicular to the gate line; Forming a cell separator by forming a nitride layer filling the predetermined region of the cell separator; Forming a landing plug contact hole by removing the first interlayer oxide layer exposed using the cell separator as a mask; And Filling the landing plug contact hole to form a landing plug Method of manufacturing a semiconductor device comprising a. The method of claim 1, The device isolation film is a semiconductor device manufacturing method, characterized in that formed using a thickness of 500 ~ 1000Å using any one selected from HDP (High Density Plasma), SOD (Spin on dielectric) or a combination thereof. The method of claim 1, The first interlayer oxide film is a manufacturing method of a semiconductor device, characterized in that the BPSG (BoroPhosphorus Silicate Glass), SOD or HDP. The method of claim 1, The cell separator predetermined region is etched to a depth of more than 0 to 1000 Å relative to the semiconductor substrate. The method of claim 1, The nitride film is a semiconductor device manufacturing method, characterized in that formed in a thickness of 100 to 3000 내지. The method of claim 1, The forming of the landing plug contact hole may be performed so that the semiconductor substrate is exposed. The method of claim 6, And the exposed semiconductor substrate is etched to a depth of 50 to 1000 microns. The method of claim 1, The cell separator is formed using a line type or a hole type mask. The method of claim 1, The landing plug may be formed using a polysilicon layer, a solid phase epitaxy (SPE), or a selective epitaxial growth (SEG) film. The method of claim 1, The landing plug is a semiconductor device manufacturing method, characterized in that formed to a thickness of 500 to 3000 내지. The method of claim 1, And forming a second interlayer oxide film on the entire surface of the semiconductor substrate including the landing plug after the forming of the landing plug. The method of claim 11, And the second interlayer oxide film is formed of SOD, HDP and BPSG films. A semiconductor substrate including an active region, an isolation layer, and a gate line; A plurality of cell separators provided on the device isolation layers between the gate lines; And A landing plug provided on the active region through a first interlayer oxide layer between the gate line and the cell separator; A semiconductor device comprising a. The method of claim 13, The cell separator is a semiconductor device, characterized in that provided in the line type or hole type. The method of claim 14, And the line type is provided in a direction perpendicular to the gate line. The method of claim 13, The cell separator is formed of a nitride film. The method of claim 13, The landing plug is a semiconductor device, characterized in that formed using a polysilicon layer, SPE or SEG film.

Images