KR20130017597A - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device Download PDF

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KR20130017597A
KR20130017597A KR1020110080143A KR20110080143A KR20130017597A KR 20130017597 A KR20130017597 A KR 20130017597A KR 1020110080143 A KR1020110080143 A KR 1020110080143A KR 20110080143 A KR20110080143 A KR 20110080143A KR 20130017597 A KR20130017597 A KR 20130017597A
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South Korea
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layer
mask pattern
forming
capping
etch stop
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KR1020110080143A
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Korean (ko)
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KR101744072B1 (en
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송명환
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에스케이하이닉스 주식회사
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H01L27/108Dynamic random access memory structures
    • H01L27/10844Multistep manufacturing methods
    • H01L27/10847Multistep manufacturing methods for structures comprising one transistor one-capacitor memory cells
    • H01L27/10873Multistep manufacturing methods for structures comprising one transistor one-capacitor memory cells with at least one step of making the transistor
    • H01L27/10876Multistep manufacturing methods for structures comprising one transistor one-capacitor memory cells with at least one step of making the transistor the transistor having a trench structure in the substrate
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105After-treatment
    • H01L21/31051Planarisation of the insulating layers
    • H01L21/31053Planarisation of the insulating layers involving a dielectric removal step
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105After-treatment
    • H01L21/311Etching the insulating layers by chemical or physical means
    • H01L21/31144Etching the insulating layers by chemical or physical means using masks
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232Field-effect technology
    • H01L21/8234MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823475MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H01L27/108Dynamic random access memory structures
    • H01L27/10844Multistep manufacturing methods
    • H01L27/10894Multistep manufacturing methods with simultaneous manufacture of periphery and memory cells

Abstract

PURPOSE: A method for manufacturing a semiconductor device is provided to prevent a step due to slurry by forming an etch stop layer and a capping layer on the upper side of an insulation layer. CONSTITUTION: An insulation layer(18) is formed on the upper side of a substrate(11) including a buried gate(15) and a junction region(17). An etch stop layer(22) and a capping layer(23) are laminated on the insulation layer. The insulation layer is planarized using the etch stop layer as a target. A line type first mask pattern is formed on the capping layer. A hole type second mask pattern(25) is formed on the insulation layer including the capping layer. The linewidth of the second mask pattern is narrower than the linewidth of the first mask pattern. An open part(26) to expose the junction region is formed by etching the insulation layer using the second mask pattern as an etch barrier. [Reference numerals] (AA) Cell area; (BB) Peripheral area

Description

반도체장치 제조 방법{METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE}TECHNICAL FIELD [0001] The present invention relates to a method of manufacturing a semiconductor device,
본 발명은 반도체 제조 기술에 관한 것으로, 특히 매립 게이트를 갖는 반도체 장치의 스토리지 노드 콘택 제조 방법에 대한 것이다.
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor manufacturing techniques, and more particularly to a method for manufacturing storage node contacts in a semiconductor device having a buried gate.
통상의 게이트 구조에서는 기판 상에 게이트가 형성되고, 게이트 사이에 랜딩 플러그 콘택(Landing plug contact)이 형성되어 소스/드레인에 연결되며, 랜딩 플러그 콘택 상에 스토리지 노드 콘택(storage node contact)이 형성되어 캐패시터와 기판을 연결하는 구조를 갖는다. In a conventional gate structure, a gate is formed on a substrate, a landing plug contact is formed between the gates, and is connected to a source / drain, and a storage node contact is formed on the landing plug contact. It has a structure for connecting the capacitor and the substrate.
최근 반도체 장치의 축소화에 따라 기판 상에 게이트를 형성하지 않고, 기판을 식각하여 트렌치를 형성한 후 게이트를 매립하는 매립 게이트(buried gate) 구조가 제안되었다. 그리고, 셀영역의 비트라인 형성시 주변영역의 게이트가 함께 형성된다. Recently, a buried gate structure has been proposed in which a gate is buried after etching a substrate to form a trench without forming a gate on the substrate as a semiconductor device is reduced in size. When the bit line is formed in the cell region, the gates of the peripheral region are formed together.
이후, 스토리지 노드 콘택(Storage Node Contact) 및 비트라인 또는 주변영역의 게이트 간 절연을 위해 층간절연막을 형성하고, 화학적기계적연마(Chemical Mechanical Polishing) 공정을 통한 평탄화를 진행한다. Subsequently, an interlayer insulating film is formed to insulate the storage node contact and the gate between the bit line or the peripheral area, and planarization is performed through a chemical mechanical polishing process.
그러나, 평탄화를 위한 화학적기계적연마공정에서 슬러리(Slurry)에 따른 디싱(Dishing) 및 침식(Erosion)이 발생하여 셀영역과 주변영역 또는 셀영역의 센터(Center)와 에지(Edge) 부분에서 급격한 단차가 발생하고, 이로 인해 레지듀(Residue)성 결함(Defect)을 유발하는 문제점이 있다.However, in the chemical mechanical polishing process for planarization, dishing and erosion occurs due to slurry, and there is a sharp step in the center region and the edge region of the cell region and the surrounding region. Occurs, and this causes a problem that causes residue defects.
도 1은 종래 기술의 문제점을 설명하기 위한 TEM사진이다.1 is a TEM photograph for explaining the problem of the prior art.
도 1을 참조하면, 셀영역의 센터와 엣지 부분 및 셀영역과 주변영역 간에 급격한 단차가 발생한 것을 확인할 수 있다.
Referring to FIG. 1, it can be seen that a sharp step occurs between the center and edge portions of the cell region and the cell region and the peripheral region.
본 발명은 상기한 종래 기술의 문제점을 해결하기 위한 것으로, 층간절연막의 평탄화시 슬러리에 따른 단차를 방지하는 반도체 장치 제조 방법을 제공하는데 그 목적이 있다.
SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems of the prior art, and an object thereof is to provide a method of manufacturing a semiconductor device which prevents a step caused by a slurry during planarization of an interlayer insulating film.
상기 목적을 달성하기 위한 본 발명의 실시예에 따른 반도체 장치 제조 방법은 매립게이트 및 접합영역을 포함하는 기판 상부에 절연막을 형성하는 단계; 상기 절연막 상에 식각정지막 및 캡핑막을 적층하는 단계; 상기 식각정지막을 타겟으로 상기 절연막에 평탄화 공정을 진행하는 단계; 상기 캡핑막 상에 라인타입의 제1마스크패턴을 형성하는 단계; 상기 제1마스크패턴을 식각장벽으로 상기 캡핑막 및 식각정지막을 식각하는 단계; 상기 캡핑막을 포함하는 절연막 상에 제1마스크패턴보다 선폭이 작은 홀타입의 제2마스크패턴을 형성하는 단계; 상기 제2마스크패턴을 식각장벽으로 상기 절연막을 식각하여 상기 접합영역을 노출시키는 오픈부를 형성하는 단계; 및 상기 오픈부에 도전물질을 매립하여 플러그를 형성하는 단계를 포함하는 것을 특징으로 한다.A semiconductor device manufacturing method according to an embodiment of the present invention for achieving the above object comprises the steps of forming an insulating film on the substrate including a buried gate and a junction region; Stacking an etch stop layer and a capping layer on the insulating layer; Performing a planarization process on the insulating layer using the etch stop layer as a target; Forming a line type first mask pattern on the capping film; Etching the capping layer and the etch stop layer using the first mask pattern as an etch barrier; Forming a hole-type second mask pattern having a line width smaller than that of the first mask pattern on the insulating film including the capping film; Forming an open portion exposing the junction region by etching the insulating layer using the second mask pattern as an etch barrier; And embedding a conductive material in the open part to form a plug.
본 발명의 또 다른 실시예에 따른 반도체 장치 제조 방법은 셀영역과 주변영역이 구비된 기판의 셀영역에 매립게이트 및 접합영역을 형성하는 단계; 상기 주변영역의 기판 상에 페리게이트를 형성하는 단계; 상기 셀영역의 기판 상부 및 주변영역의 페리게이트 상부에 절연막을 형성하는 단계; 상기 절연막 상에 식각정지막 및 캡핑막을 적층하는 단계; 상기 식각정지막을 타겟으로 상기 절연막에 평탄화 공정을 진행하는 단계; 상기 캡핑막 상에 라인타입의 제1마스크패턴을 형성하는 단계; 상기 제1마스크패턴을 식각장벽으로 상기 셀영역의 캡핑막 및 식각정지막을 식각하는 단계; 상기 캡핑막을 포함하는 절연막 상에 제1마스크패턴보다 선폭이 작은 홀타입의 제2마스크패턴을 형성하는 단계; 상기 제2마스크패턴을 식각장벽으로 상기 셀영역의 절연막을 식각하여 상기 접합영역을 노출시키는 오픈부를 형성하는 단계; 및 상기 오픈부에 도전물질을 매립하여 플러그를 형성하는 단계를 포함하는 것을 특징으로 한다.In another embodiment, a method of manufacturing a semiconductor device includes: forming a buried gate and a junction region in a cell region of a substrate having a cell region and a peripheral region; Forming a ferrite on the substrate in the peripheral region; Forming an insulating layer on the substrate in the cell region and on the ferrite in the peripheral region; Stacking an etch stop layer and a capping layer on the insulating layer; Performing a planarization process on the insulating layer using the etch stop layer as a target; Forming a line type first mask pattern on the capping film; Etching the capping layer and the etch stop layer of the cell region using the first mask pattern as an etch barrier; Forming a hole-type second mask pattern having a line width smaller than that of the first mask pattern on the insulating film including the capping film; Forming an open portion for exposing the junction region by etching the insulating layer of the cell region using the second mask pattern as an etch barrier; And embedding a conductive material in the open part to form a plug.
특히, 상기 식각정지막은 질화막을 포함하고, 상기 캡핑막은 USG(Undoped Silicate Glass)막을 포함하는 것을 특징으로 한다.In particular, the etch stop layer includes a nitride layer, and the capping layer includes a USG (Undoped Silicate Glass) layer.
또한, 상기 오픈부는 계단형태의 입구를 갖는 것을 특징으로 한다.In addition, the open portion is characterized in that it has a stepped entrance.
또한, 상기 도전물질은 폴리실리콘(Poly Silicon)을 포함하는 것을 특징으로 한다.
In addition, the conductive material is characterized in that it comprises polysilicon (Poly Silicon).
상술한 본 발명의 실시예에 따른 반도체 장치 제조 방법은 절연막 상부에 식각정지막 및 캡핑막을 추가로 형성하여 슬러리에 의한 단차를 방지하는 효과가 있다. The semiconductor device manufacturing method according to the embodiment of the present invention described above has an effect of preventing the step by the slurry by further forming an etch stop film and a capping film on the insulating film.
또한, 선폭이 다른 2개의 마스크패턴을 이용하여 오픈부를 계단형태로 형성함에 따라 갭필마진을 확보하여 심(Seam) 현상을 방지하는 효과가 있다.
In addition, since the open portion is formed in the form of a step using two mask patterns having different line widths, there is an effect of securing a gap fill margin to prevent a seam phenomenon.
도 1은 종래 기술의 문제점을 설명하기 위한 TEM사진,
도 2a 내지 도 2g는 본 발명의 실시예에 따른 반도체 장치 제조 방법을 설명하기 위한 공정 단면도.
1 is a TEM photograph for explaining the problems of the prior art,
2A to 2G are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.
이하, 본 발명이 속하는 기술 분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 실시예를 첨부 도면을 참조하여 설명하기로 한다.Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings, so that those skilled in the art can easily carry out the technical idea of the present invention.
도 2a 내지 도 2g는 본 발명의 실시예에 따른 반도체 장치 제조 방법을 설명하기 위한 공정 단면도이다.2A to 2G are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.
도 2a에 도시된 바와 같이, 셀영역과 주변영역이 구비된 기판(11)에 소자분리막(12)을 형성한다. 소자분리막(12)은 STI(Shallow Trench Isolation) 공정을 통해 형성하고, 소자분리막(12)은 절연막으로 형성한다. 절연막은 산화막을 포함하고, 산화막은 예컨대 HDP(High Density Plasma) 산화막 또는 SOD(Spin On Dielectric) 산화막 등을 포함한다. 소자분리막(12)에 의해 활성영역(13)이 정의된다.As shown in FIG. 2A, the device isolation layer 12 is formed on the substrate 11 having the cell region and the peripheral region. The device isolation film 12 is formed through a shallow trench isolation (STI) process, and the device isolation film 12 is formed of an insulating film. The insulating film includes an oxide film, and the oxide film includes, for example, an HDP (High Density Plasma) oxide film or a SOD (Spin On Dielectric) oxide film. The active region 13 is defined by the device isolation layer 12.
이어서, 셀영역의 기판(11)을 선택적으로 식각하여 매립 게이트용 트렌치(14)를 형성한다. 매립 게이트용 트렌치(14)는 라인타입으로 형성하며, 식각속도의 차이에 의해 소자분리막(12)에 형성된 매립 게이트용 트렌치(14)가 활성영역(13)에 형성된 매립 게이트용 트렌치(14)보다 더 깊게 형성될 수 있다. 주변영역은 매립 게이트가 형성되지 않으므로, 셀영역의 기판(11)에 매립 게이트용 트렌치(14)를 형성하기 위한 마스크패턴은 주변영역의 기판(11)을 모두 덮도록 패터닝된다.Subsequently, the buried gate trench 14 is formed by selectively etching the substrate 11 in the cell region. The buried gate trench 14 is formed in a line type, and the buried gate trench 14 formed in the device isolation layer 12 is formed by the difference in the etching rate than the buried gate trench 14 formed in the active region 13. Can be formed deeper. Since the buried gate is not formed in the peripheral region, the mask pattern for forming the trench 14 for the buried gate in the substrate 11 of the cell region is patterned to cover all of the substrate 11 in the peripheral region.
이어서, 매립 게이트용 트렌치(14)에 도전물질을 매립한 후, 매립 게이트용 트렌치(14)의 일부가 매립되도록 리세스(Recess)시켜 매립 게이트(15)를 형성한다. 도전물질을 형성하기 전에 매립 게이트용 트렌치(14)의 측벽 및 바닥부에 게이트절연막(도시생략)을 형성한다. 매립 게이트(15)를 형성하기 위한 도전물질은 텅스텐을 포함한다.Subsequently, after the conductive material is filled in the buried gate trench 14, the buried gate 15 is formed by recessing a portion of the buried gate trench 14 to be buried. Before forming the conductive material, a gate insulating film (not shown) is formed in the sidewalls and the bottom of the buried gate trench 14. The conductive material for forming the buried gate 15 includes tungsten.
이어서, 매립 게이트(15) 상에 매립 게이트용 트렌치(14)의 나머지 부분을 채우는 실링막(16)을 형성한다. 실링막(16)은 매립 게이트(15)와 상부간의 절연 및 매립 게이트(15)의 산화를 방지하기 위한 것으로, 절연막으로 형성하되, 질화막 또는 산화막으로 형성하는 것이 바람직하다.Subsequently, a sealing film 16 is formed on the buried gate 15 to fill the remaining portion of the buried gate trench 14. The sealing film 16 is to prevent insulation between the buried gate 15 and the upper portion and to prevent oxidation of the buried gate 15. The sealing film 16 is formed of an insulating film, but preferably formed of a nitride film or an oxide film.
이어서, 매립 게이트(15)의 양쪽 기판에 이온주입을 진행하여 접합영역(17)을 형성한다. 매립 게이트(15) 사이에 존재하는 접합영역(15)은 비트라인 노드(Bit Line Node)이며, 매립 게이트와 소자분리막(12) 사이의 접합영역(15)은 스토리지 노드 콘택 노드(Storage Node Contact Node)이다. Subsequently, ion implantation is performed to both substrates of the buried gate 15 to form the junction region 17. The junction region 15 existing between the buried gate 15 is a bit line node, and the junction region 15 between the buried gate and the device isolation layer 12 is a storage node contact node. )to be.
도 2b에 도시된 바와 같이, 매립 게이트(15)를 포함하는 셀영역의 기판(11) 상에 제1절연막(18)을 형성한다. 제1절연막(18)은 매립 게이트(13)와 상부층간의 절연을 위한 것이며, 다층으로 형성할 수 있다. 이때, 제1절연막(18)은 셀영역의 기판(11) 상부에만 형성되며, 주변영역의 기판(11) 상부에는 형성되지 않는다.As shown in FIG. 2B, the first insulating layer 18 is formed on the substrate 11 of the cell region including the buried gate 15. The first insulating layer 18 is for insulating between the buried gate 13 and the upper layer, and may be formed in multiple layers. In this case, the first insulating layer 18 is formed only on the substrate 11 of the cell region, and is not formed on the substrate 11 of the peripheral region.
이어서, 주변영역의 기판(11) 상부에 페리게이트(19)를 형성한다. 페리게이트(19)는 배리어금속(19A), 금속전극(19B) 및 게이트하드마스크(19C)의 적층구조로 형성한다. 배리어금속(19A) 하부에는 페리게이트(19)와 기판(11)의 절연을 위한 게이트절연막(도시생략)을 포함한다. 도시되지 않았으나, 주변영역의 페리게이트(19)는 셀영역의 비트라인과 동시에 형성할 수 있다.Next, the ferrite gate 19 is formed on the substrate 11 in the peripheral region. The ferry gate 19 is formed in a stacked structure of a barrier metal 19A, a metal electrode 19B, and a gate hard mask 19C. A lower portion of the barrier metal 19A includes a gate insulating film (not shown) for insulating the ferrite gate 19 and the substrate 11. Although not shown, the ferrite gate 19 of the peripheral region may be formed at the same time as the bit line of the cell region.
이어서, 페리게이트(19)를 포함하는 주변영역의 기판(11)에 단차를 따라 스페이서(20)를 형성한다. 스페이서(20)는 후속 공정에서 페리게이트(19)를 보호하기 위한 것으로, 절연막으로 형성한다. 절연막은 질화막을 포함하고, 질화막은 실리콘질화막(SiN)을 포함한다.Subsequently, spacers 20 are formed along the steps on the substrate 11 in the peripheral region including the ferrite gate 19. The spacer 20 is to protect the ferrite 19 in a subsequent process and is formed of an insulating film. The insulating film includes a nitride film, and the nitride film includes a silicon nitride film (SiN).
도 2c에 도시된 바와 같이, 셀영역의 제1절연막(18) 및 주변영역의 스페이서(20) 상에 제2절연막(21)을 형성한다. 제2절연막(21)은 산화막으로 형성하는 것이 바람직하며, 갭필(Gap fill) 특성을 위해 BPSG(Boron Phosphorus Silicate Glass)막으로 형성할 수 있다. 제2절연막(21)은 주변영역의 페리게이트(19) 사이를 충분히 매립하는 두께로 형성한다. As shown in FIG. 2C, the second insulating layer 21 is formed on the first insulating layer 18 of the cell region and the spacer 20 of the peripheral region. The second insulating layer 21 may be formed of an oxide layer, and may be formed of a boron phosphorus silicate glass (BPSG) layer for a gap fill property. The second insulating film 21 is formed to have a sufficient thickness between the ferrite gates 19 in the peripheral region.
이어서, 제2절연막(21) 상에 식각정지막(22) 및 캡핑막(23)을 적층한다. 식각정지막(22) 및 캡핑막(23)은 제2절연막(21)의 평탄화 공정시 셀영역과 주변영역간의 단차 및 셀영역의 센터(Center)와 엣지(Edge)영역에서의 단차를 방지하는 역할을 하며, 또한 식각정지막(22)은 후속 플러그 물질 형성시 갭필마진을 확보하는 역할을 한다. Subsequently, an etch stop layer 22 and a capping layer 23 are stacked on the second insulating layer 21. The etch stop layer 22 and the capping layer 23 may prevent the step between the cell region and the peripheral region and the step between the center and edge regions of the cell region during the planarization of the second insulating layer 21. In addition, the etch stop layer 22 serves to secure a gap fill margin in subsequent plug material formation.
식각정지막(22)은 절연막으로 형성하고, 절연막은 질화막을 포함하며, 질화막은 실리콘질화막(SiN)을 포함한다. 식각정지막(22)은 예컨대 300Å~500Å의 두께로 형성할 수 있다. 캡핑막(23)은 절연막으로 형성하고, 절연막은 산화막을 포함하며, 산화막은 예컨대 USG(Undoped Silicate Glass)막을 포함한다. 캡핑막(23)은 예컨대 150Å~250Å의 두께로 형성할 수 있다.The etch stop film 22 is formed of an insulating film, the insulating film includes a nitride film, and the nitride film includes a silicon nitride film (SiN). The etch stop film 22 may be formed to a thickness of, for example, 300 kPa to 500 kPa. The capping film 23 is formed of an insulating film, the insulating film includes an oxide film, and the oxide film includes, for example, an USG (Undoped Silicate Glass) film. The capping film 23 can be formed to a thickness of, for example, 150 kPa to 250 kPa.
이어서, 평탄화공정을 진행한다. 평탄화공정은 화학적기계적연마(Chemical Mechanical Polishing) 공정으로 진행할 수 있다. 이때, 평탄화 공정은 식각정지막(22)을 타겟으로 진행하여 슬러리(Slurry)에 따른 디싱(Dishing) 및 침식(Erosion)을 방지한다. 따라서, 셀영역과 주변영역 또는 셀영역의 센터(Center)와 에지(Edge) 부분에서 급격한 단차를 방지하고, 단차로 인한 레지듀(Residue)성 결함(Defect) 역시 방지하는 장점이 있다.Next, the planarization process is performed. The planarization process may be performed by a chemical mechanical polishing process. In this case, the planarization process prevents dishing and erosion due to the slurry by advancing the etch stop layer 22 as a target. Accordingly, there is an advantage in that abrupt steps are prevented in the cell area and the peripheral area or in the center and edge portions of the cell area, and also residual defects due to the steps are prevented.
평탄화 공정시 단차에 따라 식각정지막(22) 상부의 캡핑막(23)은 일부 제거되거나, 그대로 잔류할 수 있다.During the planarization process, the capping layer 23 on the etch stop layer 22 may be partially removed or remain as it is.
도 2d에 도시된 바와 같이, 캡핑막(23) 상에 제1마스크패턴(24)을 형성한다. 제1마스크패턴(24)은 캡핑막(23) 상에 감광막을 코팅(Coating)하고, 노광(Exposure) 및 현상(Develop)으로 셀영역의 스토리지 노드 콘택 영역이 오픈되도록 패터닝하며, 주변영역은 모두 덮는 형태로 패터닝된다. 제1마스크패턴(24)은 라인타입(Line Type)으로 형성하며, 예정된 스토리지 노드 콘택 영역의 선폭보다 큰 선폭으로 패터닝한다. 제1마스크패턴(24)에 의해 오픈된 스토리지 노드 콘택 영역의 선폭은 W1이라고 한다.As shown in FIG. 2D, the first mask pattern 24 is formed on the capping layer 23. The first mask pattern 24 coats the photoresist on the capping layer 23, and is patterned to expose the storage node contact region of the cell region by exposure and development, and the peripheral regions are all Patterned in covering form. The first mask pattern 24 is formed in a line type and is patterned to a line width larger than the line width of the predetermined storage node contact area. The line width of the storage node contact region opened by the first mask pattern 24 is referred to as W1.
이어서, 제1마스크패턴(24)을 식각장벽으로 캡핑막(23) 및 식각정지막(22)을 식각한다.Subsequently, the capping layer 23 and the etch stop layer 22 are etched using the first mask pattern 24 as an etch barrier.
도 2e에 도시된 바와 같이, 제1마스크패턴(24, 도 2d 참조)을 제거한다. 제1마스크패턴(24, 도 2d 참조)이 감광막인 경우, 건식식각으로 제거하며, 건식식각은 산소스트립 공정을 포함한다.As shown in FIG. 2E, the first mask pattern 24 (see FIG. 2D) is removed. When the first mask pattern 24 (refer to FIG. 2D) is a photosensitive film, the first mask pattern 24 is removed by dry etching, and the dry etching includes an oxygen strip process.
이어서, 캡핑막(23)을 포함하는 전체구조 상에 제2마스크패턴(25)을 형성한다. 제2마스크패턴(25)은 캡핑막(23)을 포함하는 전체구조 상에 감광막을 코팅(Coating)하고, 노광(Exposure) 및 현상(Develop)으로 셀영역의 스토리지 노드 콘택 영역이 오픈되도록 패터닝하며, 주변영역은 모두 덮는 형태로 패터닝된다. Next, the second mask pattern 25 is formed on the entire structure including the capping film 23. The second mask pattern 25 coats the photoresist on the entire structure including the capping layer 23, and patterns the storage node contact region of the cell region to be opened by exposure and development. The surrounding area is patterned to cover all of them.
특히, 제2마스크패턴(25)은 홀타입(Hole Type)으로 형성하며, 제1마스크패턴(24, 도 2d 참조)에 의해 오픈된 선폭(W1)보다 작은 선폭(W2)으로 패터닝한다. In particular, the second mask pattern 25 is formed in a hole type and is patterned to a line width W2 smaller than the line width W1 opened by the first mask pattern 24 (see FIG. 2D).
이어서, 제2마스크패턴(25)을 식각장벽으로 제2절연막(21) 및 제1절연막(18)을 식각하여 접합영역(17) 중 스토리지 노드 콘택 노드부(Storage Node Contact Node)를 노출시키는 오픈부(26)를 형성한다. Subsequently, the second insulating layer 21 and the first insulating layer 18 are etched using the second mask pattern 25 as an etch barrier to expose the storage node contact node in the junction region 17. The part 26 is formed.
위와 같이, 라인타입의 제1마스크패턴을 이용하여 W1의 선폭을 갖도록 캡핑막(23) 및 식각정지막(22)을 패터닝하고, 홀타입의 제2마스크패턴을 이용하여 W1보다 작은 W2의 선폭을 갖도록 제2절연막(21) 및 제1절연막(18)을 식각함에 따라 오픈부(26)의 상부가 계단형태를 갖는다. As above, the capping layer 23 and the etch stop layer 22 are patterned to have a line width of W1 using the first mask pattern of the line type, and the line width of W2 smaller than W1 using the hole type second mask pattern. As the second insulating layer 21 and the first insulating layer 18 are etched to have the upper portion, the upper portion of the open portion 26 has a step shape.
도 2f에 도시된 바와 같이, 제2마스크패턴(25, 도 2e 참조)을 제거한다. 제2마스크패턴(25, 도 2e 참조)이 감광막인 경우, 건식식각으로 제거하며, 건식식각은 산소스트립 공정을 포함한다.As shown in FIG. 2F, the second mask pattern 25 (see FIG. 2E) is removed. When the second mask pattern 25 (see FIG. 2E) is a photosensitive film, the second mask pattern 25 is removed by dry etching, and the dry etching includes an oxygen strip process.
이어서, 오픈부(26)에 도전물질(27)을 매립한다. 도전물질(27)은 스토리지 노드 콘택을 형성하기 위한 것으로, 폴리실리콘(Poly Silicon)을 포함한다. 이때, 오픈부(26)의 입구가 계단형태를 갖고 있어 도전물질(27) 매립시 갭필마진(Gap fill Margin)을 확보할 수 있다. 따라서, 갭필부족에 의한 심(Seam) 현상을 방지할 수 있다. Subsequently, the conductive material 27 is embedded in the open portion 26. The conductive material 27 is for forming a storage node contact, and includes polysilicon. In this case, the opening of the opening 26 has a step shape, so that a gap fill margin may be secured when the conductive material 27 is embedded. Therefore, the seam phenomenon by the gap fill lack can be prevented.
도 2g에 도시된 바와 같이, 도전물질(27, 도 2f 참조)을 평탄화하여 오픈부(26) 내에 잔류하는 스토리지 노드 콘택 플러그(27A, Storage Node Contact Plug)를 형성한다. 이때, 평탄화는 화학적기계적연마공정을 포함하며, 식각정지막(22)이 노출되는 타겟으로 진행한다. 따라서, 식각정지막(22) 상부의 캡핑막(23, 도 2f 참조)은 모두 제거되며, 스토리지 노드 콘택 플러그(27A)는 각각의 오픈부(26) 내에 잔류하는 형태로 분류(Isolation)된다. As shown in FIG. 2G, the conductive material 27 (see FIG. 2F) is planarized to form a storage node contact plug 27A remaining in the open part 26. In this case, the planarization includes a chemical mechanical polishing process and proceeds to the target to which the etch stop layer 22 is exposed. Accordingly, all of the capping layer 23 (see FIG. 2F) on the etch stop layer 22 is removed, and the storage node contact plug 27A is isolated in the form of remaining in each open part 26.
위와 같이, 식각정지막(22)을 타겟으로 도전물질(27, 도 2f 참조)을 평탄화함에 따라 갭필 특성상 표면 쪽에 심(Seam)이 발생했다고 할지라도 평탄화 공정에서 충분히 제거가 가능한 장점이 있다.As described above, even when the conductive material 27 (see FIG. 2F) is planarized by using the etch stop layer 22 as a target, even if seam is generated on the surface side of the gap fill characteristic, it may be sufficiently removed in the planarization process.
본 발명의 기술 사상은 상기 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위 내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.
Although the technical spirit of the present invention has been described in detail according to the above embodiments, it should be noted that the above embodiments are for the purpose of description and not of limitation. In addition, it will be understood by those of ordinary skill in the art that various embodiments are possible within the scope of the technical idea of the present invention.
11 : 기판 12 : 소자분리막
13 : 활성영역 14 : 트렌치
15 : 매립 게이트 16 : 실링막
17 : 접합영역 18 : 제1절연막
19 : 페리게이트 20 : 스페이서
21 : 제2절연막 22 : 식각정지막
23 : 캡핑막 24 : 제1마스크패턴
25 : 제2마스크패턴 26 : 오픈부
27 : 도전물질 27A : 스토리지 노드 콘택 플러그
11 substrate 12 device isolation film
13 active region 14 trench
15: buried gate 16: sealing film
17 junction region 18 first insulating film
19: Ferrigate 20: spacer
21: second insulating film 22: etch stop film
23: capping film 24: the first mask pattern
25: second mask pattern 26: open portion
27: conductive material 27A: storage node contact plug

Claims (5)

  1. 매립게이트 및 접합영역을 포함하는 기판 상부에 절연막을 형성하는 단계;
    상기 절연막 상에 식각정지막 및 캡핑막을 적층하는 단계;
    상기 식각정지막을 타겟으로 상기 절연막에 평탄화 공정을 진행하는 단계;
    상기 캡핑막 상에 라인타입의 제1마스크패턴을 형성하는 단계;
    상기 제1마스크패턴을 식각장벽으로 상기 캡핑막 및 식각정지막을 식각하는 단계;
    상기 캡핑막을 포함하는 절연막 상에 제1마스크패턴보다 선폭이 작은 홀타입의 제2마스크패턴을 형성하는 단계;
    상기 제2마스크패턴을 식각장벽으로 상기 절연막을 식각하여 상기 접합영역을 노출시키는 오픈부를 형성하는 단계; 및
    상기 오픈부에 도전물질을 매립하여 플러그를 형성하는 단계
    를 포함하는 반도체 장치 제조 방법.
    Forming an insulating film on the substrate including the buried gate and the junction region;
    Stacking an etch stop layer and a capping layer on the insulating layer;
    Performing a planarization process on the insulating layer using the etch stop layer as a target;
    Forming a line type first mask pattern on the capping film;
    Etching the capping layer and the etch stop layer using the first mask pattern as an etch barrier;
    Forming a hole-type second mask pattern having a line width smaller than that of the first mask pattern on the insulating film including the capping film;
    Forming an open portion exposing the junction region by etching the insulating layer using the second mask pattern as an etch barrier; And
    Embedding a conductive material in the open part to form a plug
    ≪ / RTI >
  2. 셀영역과 주변영역이 구비된 기판의 셀영역에 매립게이트 및 접합영역을 형성하는 단계;
    상기 주변영역의 기판 상에 페리게이트를 형성하는 단계;
    상기 셀영역의 기판 상부 및 주변영역의 페리게이트 상부에 절연막을 형성하는 단계;
    상기 절연막 상에 식각정지막 및 캡핑막을 적층하는 단계;
    상기 식각정지막을 타겟으로 상기 절연막에 평탄화 공정을 진행하는 단계;
    상기 캡핑막 상에 라인타입의 제1마스크패턴을 형성하는 단계;
    상기 제1마스크패턴을 식각장벽으로 상기 셀영역의 캡핑막 및 식각정지막을 식각하는 단계;
    상기 캡핑막을 포함하는 절연막 상에 제1마스크패턴보다 선폭이 작은 홀타입의 제2마스크패턴을 형성하는 단계;
    상기 제2마스크패턴을 식각장벽으로 상기 셀영역의 절연막을 식각하여 상기 접합영역을 노출시키는 오픈부를 형성하는 단계; 및
    상기 오픈부에 도전물질을 매립하여 플러그를 형성하는 단계
    를 포함하는 반도체 장치 제조 방법.
    Forming a buried gate and a junction region in a cell region of a substrate having a cell region and a peripheral region;
    Forming a ferrite on the substrate in the peripheral region;
    Forming an insulating layer on the substrate in the cell region and on the ferrite in the peripheral region;
    Stacking an etch stop layer and a capping layer on the insulating layer;
    Performing a planarization process on the insulating layer using the etch stop layer as a target;
    Forming a line type first mask pattern on the capping film;
    Etching the capping layer and the etch stop layer of the cell region using the first mask pattern as an etch barrier;
    Forming a hole-type second mask pattern having a line width smaller than that of the first mask pattern on the insulating film including the capping film;
    Forming an open portion exposing the junction region by etching the insulating layer of the cell region using the second mask pattern as an etch barrier; And
    Embedding a conductive material in the open part to form a plug
    ≪ / RTI >
  3. 제1 및 제2항에 있어서,
    상기 식각정지막은 질화막을 포함하고, 상기 캡핑막은 USG(Undoped Silicate Glass)막을 포함하는 반도체 장치 제조 방법.
    The method according to claim 1 and 2,
    The etch stop layer includes a nitride layer, and the capping layer includes a USG (Undoped Silicate Glass) layer.
  4. 제1 및 제2항에 있어서,
    상기 오픈부는 계단형태의 입구를 갖는 반도체 장치 제조 방법.
    The method according to claim 1 and 2,
    The open portion has a stepped opening of the semiconductor device manufacturing method.
  5. 제1 및 제2항에 있어서,
    상기 도전물질은 폴리실리콘(Poly Silicon)을 포함하는 반도체 장치 제조 방법.
    The method according to claim 1 and 2,
    The conductive material includes polysilicon (Poly Silicon).
KR1020110080143A 2011-08-11 2011-08-11 Method for manufacturing semiconductor device KR101744072B1 (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9490275B2 (en) 2015-01-22 2016-11-08 Samsung Display Co., Ltd. Method for manufacturing thin film transistor array panel

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9490275B2 (en) 2015-01-22 2016-11-08 Samsung Display Co., Ltd. Method for manufacturing thin film transistor array panel

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