KR100753406B1 - semiconductor package - Google Patents

semiconductor package Download PDF

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Publication number
KR100753406B1
KR100753406B1 KR1020040001522A KR20040001522A KR100753406B1 KR 100753406 B1 KR100753406 B1 KR 100753406B1 KR 1020040001522 A KR1020040001522 A KR 1020040001522A KR 20040001522 A KR20040001522 A KR 20040001522A KR 100753406 B1 KR100753406 B1 KR 100753406B1
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South Korea
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semiconductor chip
bonding
substrate
bonding pad
bonding wire
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KR1020040001522A
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Korean (ko)
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KR20050073681A (en
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정관호
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주식회사 하이닉스반도체
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Priority to KR1020040001522A priority Critical patent/KR100753406B1/en
Publication of KR20050073681A publication Critical patent/KR20050073681A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/46—Structure, shape, material or disposition of the wire connectors prior to the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49517—Additional leads
    • H01L23/4952—Additional leads the additional leads being a bump or a wire

Abstract

본 발명은 반도체 칩의 본딩패드 배열에 관계없이 패키지공정을 적용시킬 수 있는 반도체패키지에 관해 개시한다. 개시된 본 발명은 본딩패드가 구비된 반도체 칩과, 반도체 칩이 안착되는 리드프레임과, 반도체 칩과 리드프레임 사이에 개재되는 제 1접착제와, 본딩패드와 리드프레임을 연결시키는 제 1본딩와이어와, 반도체칩 위에 안착되는 기판과, 반도체 칩과 기판 사이에 개재되는 제 2접착제와, 본딩패드와 기판을 연결시키는 제 2본딩와이어를 포함하여 구성된다.The present invention discloses a semiconductor package to which the packaging process can be applied regardless of the bonding pad arrangement of the semiconductor chip. The disclosed invention includes a semiconductor chip having a bonding pad, a lead frame on which the semiconductor chip is seated, a first adhesive interposed between the semiconductor chip and the lead frame, a first bonding wire connecting the bonding pad and the lead frame, And a second bonding agent interposed between the semiconductor chip and the substrate, and a second bonding wire connecting the bonding pad and the substrate.

본 발명에 따르면, 본딩패드가 크로스(cross)되어 본딩와이어 제작이 불가능할 경우, 본딩와이어를 대신할 수 있는 트레이스가 구비된 기판을 제작하여 상기 기판을 반도체 칩 위에 부착시켜 본딩와이어 공정을 실시함으로써, 본딩패드 배열에 관계없이 패키지를 제작할 수 있다.According to the present invention, if the bonding pads are cross and it is impossible to manufacture the bonding wire, a substrate having a trace capable of replacing the bonding wire is manufactured and the substrate is attached to the semiconductor chip to perform the bonding wire process. Packages can be produced regardless of the bonding pad arrangement.

Description

반도체패키지{semiconductor package}Semiconductor Package {semiconductor package}

도 1은 종래기술에 따른 반도체패키지의 단면도.1 is a cross-sectional view of a semiconductor package according to the prior art.

도 2는 본 발명에 따른 반도체패키지의 단면도.2 is a cross-sectional view of a semiconductor package according to the present invention.

본 발명은 반도체 패키지에 관한 것으로, 더욱 상세하게는 반도체 칩의 본딩패드 배열에 관계없이 패키지공정을 적용시킬 수 있는 반도체패키지에 관한 것이다.The present invention relates to a semiconductor package, and more particularly, to a semiconductor package to which a packaging process can be applied regardless of a bonding pad arrangement of a semiconductor chip.

도 1은 종래기술에 따른 반도체패키지의 단면도이다.1 is a cross-sectional view of a semiconductor package according to the prior art.

종래기술에 따른 반도체패키지는, 도 1에 도시된 바와같이, 본딩패드(2)가 구비된 반도체 칩(3)과, 반도체 칩(3)이 안착되는 리드프레임(1)과, 반도체 칩(3)과 리드프레임(1) 사이에 개재되는 접착제(4)와, 본딩패드(2)와 리드프레임(1)을 연결시키는 본딩와이어(5)를 포함하여 구성된다. 이때, 리드프레임(1)에는 반도체칩(3)이 안착되는 안착부(1a)가 홈형상으로 형성된다.As shown in FIG. 1, the semiconductor package according to the related art includes a semiconductor chip 3 having a bonding pad 2, a lead frame 1 on which the semiconductor chip 3 is seated, and a semiconductor chip 3. ) And a bonding wire 5 interposed between the lead frame 1 and the bonding pad 2 and the lead frame 1. At this time, the lead frame 1 is formed with a recess 1a in which the semiconductor chip 3 is seated in a groove shape.

그러나, 종래의 기술에서는 FBGA용으로 개발된 웨이퍼의 경우, 본딩패드의 구조적 차이로 인해 TSOP(Thin Small Out Package)로 제작이 불가능하다.However, in the related art, in the case of a wafer developed for an FBGA, it is impossible to manufacture a thin small out package (TSOP) due to structural differences in bonding pads.

따라서, 반도체 칩 개발 시 본딩패드를 옵션(option)으로 추가 제작하여 반도체 칩 면적이 증가하고 개발기간이 늘어나며, 웨이퍼 개발 후 본딩패드를 재배열할 경우 가격이 상승하고 신뢰성이 저하되는 문제가 있다.Therefore, when the semiconductor chip is developed, the bonding pad is additionally manufactured as an option to increase the semiconductor chip area and the development period, and when the rearrangement of the bonding pad after the wafer is developed, the price increases and the reliability decreases.

따라서, 상기 문제점을 해결하고자, 본 발명의 목적은 본딩패드가 크로스(cross)되어 본딩와이어 제작이 불가능할 경우, 본딩와이어를 대신할 수 있는 트레이스가 구비된 기판을 제작하여 상기 기판을 반도체 칩 위에 부착시켜 본딩와이어 공정을 실시함으로써, 반도체 칩의 본딩패드 배열에 관계없이 패키지공정을 적용시킬 수 있는 반도체패키지를 제공하려는 것이다.Accordingly, in order to solve the above problem, an object of the present invention is to manufacture a substrate having a trace to replace the bonding wire and attach the substrate to the semiconductor chip when the bonding pad is cross and thus it is impossible to manufacture the bonding wire. The present invention provides a semiconductor package to which a packaging process can be applied regardless of the bonding pad arrangement of a semiconductor chip.

상기 목적을 달성하기 위한 본 발명에 따른 반도체패키지는 본딩패드가 크로스(cross)되게 배치된 반도체 칩과, 상기 반도체 칩의 상기 본딩패드가 형성된 면의 상부에 접착제의 의해 접착되며 상기 본딩패드와 일측이 연결되는 트레이스가 형성된 기판과, 상기 반도체 칩이 안착되는 리드프레임과, 상기 반도체 칩에 형성된 상기 본딩패드와 리드프레임을 전기적으로 연결하는 제 1 본딩와이어와, 상기 반도체 칩에 형성된 상기 본딩패드와 상기 기판에 형성된 상기 트레이스의 타측을 전기적으로 연결하는 제 2 본딩와이어를 포함한다.The semiconductor package according to the present invention for achieving the above object is bonded to the upper surface of the semiconductor chip and the bonding pad formed with a bonding pad, the bonding pad of the semiconductor chip is bonded by an adhesive and one side with the bonding pad A substrate on which the trace is connected, a lead frame on which the semiconductor chip is seated, a first bonding wire electrically connecting the bonding pad and the lead frame formed on the semiconductor chip, and the bonding pad formed on the semiconductor chip; And a second bonding wire electrically connecting the other side of the trace formed on the substrate.

상기 접착제는 액상타입인 것을 사용한다.The adhesive uses a liquid type.

상기 기판은 상기 반도체 칩의 크기보다 작게 제작되며, 폴리이미드 테이프 재질을 포함한다.The substrate is made smaller than the size of the semiconductor chip, and includes a polyimide tape material.

본 발명에 따르면, 본딩패드가 크로스(cross)되어 본딩와이어 제작이 불가능 할 경우, 본딩와이어를 대신할 수 있는 트레이스가 구비된 기판을 제작하여 상기 기판을 반도체 칩 위에 부착시켜 본딩와이어 공정을 실시함으로써, 본딩패드 배열에 관계없이 패키지를 제작할 수 있다.According to the present invention, when the bonding pads are cross and it is impossible to manufacture the bonding wire, a substrate having a trace capable of replacing the bonding wire is manufactured and the substrate is attached to the semiconductor chip to perform the bonding wire process. The package can be produced regardless of the bonding pad arrangement.

(실시예)(Example)

이하, 첨부된 도면을 참고로하여 본 발명에 따른 반도체패키지를 설명하기로 한다.Hereinafter, a semiconductor package according to the present invention will be described with reference to the accompanying drawings.

본 발명은 본딩패드가 크로스(cross)되어 본딩와이어 제작이 불가능할 경우, 본딩와이어를 대신할 수 있는 트레이스가 구비된 기판을 제작하여 상기 기판을 반도체 칩 위에 부착시켜 본딩와이어 공정을 실시하려는 것이다.According to the present invention, when the bonding pads are cross and it is impossible to manufacture the bonding wire, a substrate having a trace capable of replacing the bonding wire is manufactured, and the substrate is attached to the semiconductor chip to perform the bonding wire process.

도 2는 본 발명에 따른 반도체패키지의 단면도이다.2 is a cross-sectional view of a semiconductor package according to the present invention.

본 발명에 따른 반도체패키지는, 도 2에 도시된 바와같이, 본딩패드(12)가 구비된 반도체 칩(13)과, 반도체 칩(13)이 안착되는 리드프레임(11)과, 반도체 칩(13)과 리드프레임(11) 사이에 개재되는 제 1접착제(14)와, 본딩패드(12)와 리드프레임(11)을 연결시키는 제 1본딩와이어(15)와, 반도체칩(13) 위에 안착되는 기판(18)과, 반도체 칩(13)과 기판(18) 사이에 개재되는 제 2접착제(17)와, 본딩패드(12)와 기판(18)을 연결시키는 제 2본딩와이어(16)를 포함하여 구성된다.As shown in FIG. 2, the semiconductor package according to the present invention includes a semiconductor chip 13 having a bonding pad 12, a lead frame 11 on which the semiconductor chip 13 is seated, and a semiconductor chip 13. ) And the first adhesive 14 interposed between the lead frame 11, the first bonding wire 15 connecting the bonding pad 12 and the lead frame 11, and the semiconductor chip 13. A substrate 18, a second adhesive 17 interposed between the semiconductor chip 13 and the substrate 18, and a second bonding wire 16 connecting the bonding pad 12 and the substrate 18 to each other. It is configured by.

상기 구성을 가진 본 발명에 따른 반도체패키지는, 반도체 칩(13)에서 와이어본딩이 불가능한 본딩패드(12)를 고려하여 트레이스(trace)를 디자인하고, 와이어본딩이 가능하도록 제작된 기판(18)을 제작한다. The semiconductor package according to the present invention having the above-described structure is designed in consideration of the bonding pads 12, which are not wire-bonded in the semiconductor chip 13, to design a trace, and to manufacture the substrate 18 to be wire-bonded. To make.

이때, 상기 기판(18)은 여러개의 반도체 칩(13)이 매트릭스(matrix)형태로 제작된 후, 싱귤레이션(singulation)을 통해 개별적으로 분리된다. 또한, 상기 기판(18)은 반도체 칩(13)의 크기보다 작게 제작되며, 폴리이미드 테이프 재질을 이용할 수도 있다.At this time, the substrate 18 is made of a plurality of semiconductor chips 13 in the form of a matrix (matrix), and then separately separated through a singulation (singulation). In addition, the substrate 18 may be made smaller than the size of the semiconductor chip 13, and a polyimide tape material may be used.

이어, 웨이퍼를 싱귤레이션 실시하여 반도체 칩(13) 단위로 분리시킨다. 그런다음, 리드프레임(11)에 반도체 칩(13)을 부착시키고 경화한다. Subsequently, the wafer is singulated and separated into semiconductor chip units 13. Then, the semiconductor chip 13 is attached to the lead frame 11 and cured.

이후, 상기 기판(18)을 반도체 칩(13) 위에 부착하고 경화한다. 이때, 상기 리드프레임(11)과 반도체 칩(13) 사이 및 반도체칩(13)과 기판(18) 사이에는 각각 제 1 및 제 2접착제(14)(17)를 개재시켜 이들 간의 접착력을 향상시킨다. 또한, 상기 제 1 및 제 2접착제(14)(17)은 액상타입을 이용한다.Thereafter, the substrate 18 is attached onto the semiconductor chip 13 and cured. At this time, the adhesive force between the lead frame 11 and the semiconductor chip 13 and between the semiconductor chip 13 and the substrate 18 is interposed between the first and second adhesives 14 and 17, respectively. . In addition, the first and second adhesives 14 and 17 use a liquid type.

이어, 리드프레임(11)과 반도체 칩(13) 사이를 연결시키는 제 1본딩와이어(15)를 제작하고, 이와 동시에 반도체칩(13)과 기판(18)을 연결시키는 제 2본딩와이어(16)를 제작한다.Subsequently, a first bonding wire 15 is formed to connect the lead frame 11 and the semiconductor chip 13, and at the same time, the second bonding wire 16 is connected to the semiconductor chip 13 and the substrate 18. To produce.

그런다음, 상기 결과물에 몰딩 및 트림(trim), 플레이팅(plating) 및 포밍(forming) 등의 공정을 순서대로 실시하여 패키지 제작을 완료한다.Then, molding and trimming, plating, and forming are performed on the resultant product in order to complete the package fabrication.

본 발명에 따르면, 본딩패드가 크로스(cross)되어 본딩와이어 제작이 불가능할 경우, 본딩와이어를 대신할 수 있는 트레이스가 구비된 기판을 제작하여 상기 기판을 반도체 칩 위에 부착시켜 본딩와이어 공정을 실시함으로써, 본딩패드 배열에 관계없이 패키지를 제작할 수 있다.According to the present invention, if the bonding pads are cross and it is impossible to manufacture the bonding wire, a substrate having a trace capable of replacing the bonding wire is manufactured and the substrate is attached to the semiconductor chip to perform the bonding wire process. Packages can be produced regardless of the bonding pad arrangement.

이상에서와 같이, 본 발명은 본딩패드가 크로스(cross)되어 본딩와이어 제작 이 불가능할 경우, 본딩와이어를 대신할 수 있는 트레이스가 구비된 기판을 제작하여 상기 기판을 반도체 칩 위에 부착시켜 본딩와이어 공정을 실시함으로써, 본딩패드 배열에 관계없이 패키지를 제작할 수 있다.As described above, in the present invention, when the bonding pads are cross-crossed, it is impossible to manufacture the bonding wires, the substrate is provided with a trace to replace the bonding wires, and the substrate is attached to the semiconductor chip to perform the bonding wire process. By carrying out, a package can be produced regardless of the bonding pad arrangement.

따라서, 본 발명은 소량생산 또는 긴급생산 대응이 가능하며, 반도체 칩의 본딩패드를 재배열하는 공정 대비하여 원가 경쟁력이 있는 이점이 있다.Therefore, the present invention is capable of small-scale production or emergency production, and has an advantage of being cost-competitive compared to the process of rearranging the bonding pads of the semiconductor chip.

기타, 본 발명은 그 요지를 일탈하지 않는 범위에서 다양하게 변경하여 실시할 수 있다. In addition, this invention can be implemented in various changes within the range which does not deviate from the summary.

Claims (4)

본딩패드가 크로스(cross)되게 배치된 반도체 칩과,A semiconductor chip in which bonding pads are disposed to cross, 상기 반도체 칩의 상기 본딩패드가 형성된 면의 상부에 접착제의 의해 접착되며 상기 본딩패드와 일측이 연결되는 트레이스가 형성된 기판과,A substrate having a trace bonded to an upper portion of the surface of the semiconductor chip on which the bonding pad is formed by an adhesive and connected to one side of the bonding pad; 상기 반도체 칩이 안착되는 리드프레임과,A lead frame on which the semiconductor chip is seated; 상기 반도체 칩에 형성된 상기 본딩패드와 리드프레임을 전기적으로 연결하는 제 1 본딩와이어와,A first bonding wire electrically connecting the bonding pad and the lead frame formed on the semiconductor chip; 상기 반도체 칩에 형성된 상기 본딩패드와 상기 기판에 형성된 상기 트레이스의 타측을 전기적으로 연결하는 제 2 본딩와이어를 포함하는 반도체패키지.And a second bonding wire electrically connecting the bonding pad formed on the semiconductor chip and the other side of the trace formed on the substrate. 삭제delete 제 1항에 있어서, 상기 기판은 상기 반도체 칩의 크기보다 작게 제작된 것을 특징으로 하는 반도체패키지.The semiconductor package of claim 1, wherein the substrate is made smaller than the size of the semiconductor chip. 제 1항에 있어서, 상기 기판은 폴리이미드 테이프 재질을 포함하는 것을 특징으로 하는 반도체패키지.The semiconductor package of claim 1, wherein the substrate comprises a polyimide tape material.
KR1020040001522A 2004-01-09 2004-01-09 semiconductor package KR100753406B1 (en)

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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR0119421Y1 (en) * 1993-08-17 1998-08-01 김광호 Control key protection apparatus of mini cassette
KR20020047745A (en) * 2000-12-14 2002-06-22 마이클 디. 오브라이언 Semiconductor package

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR0119421Y1 (en) * 1993-08-17 1998-08-01 김광호 Control key protection apparatus of mini cassette
KR20020047745A (en) * 2000-12-14 2002-06-22 마이클 디. 오브라이언 Semiconductor package

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