TW201332031A - Method for manufacturing a substrate, package method, package structure and system-in-package structure for a semiconductor package - Google Patents

Abstract

A method for manufacturing a substrate, a package method, a package structure and a system-in-package structure for a semiconductor package are provided. The package method comprises the following steps: providing a metal foil which comprises a first surface and a second surface; respectively forming a patterned resistant layer on the first surface and the second surface of the metal foil; forming at least one connection pad to each of the patterned resistant layer; pressing the second surface of the metal foil into a release layer of a carrier; etching the metal foil to form a patterned metal foil; disposing at least one semiconductor element on the patterned resistant layer of the first surface of the patterned metal foil; electrically connecting the at least one semiconductor element with the at least one connection pad of the first surface; packaging a space over the carrier; and removing the carrier.

Description

Substrate process, package method, package structure and system level package structure for a semiconductor package

The present invention relates to a substrate process, a package method, a package structure, and a system level package structure for a semiconductor package. More specifically, the present invention relates to a substrate process and a package method for packaging a patterned metal foil as a substrate. Package structure and system level package structure.

In general, the semiconductor process can be divided into two phases, the first phase is the wafer (Wafer) process, and the second phase is the package test. With the rapid development of semiconductor technology, wafer process technology has been continuously improved to meet the needs of the semiconductor industry. On the other hand, due to the continuous improvement of wafer processing technology, the traditional packaging and testing technology has gradually been eliminated by the market, making package testing technology new and innovative to cope with changes in the semiconductor industry.

Furthermore, the package test technology can be classified into a package phase and a test phase, in which the package phase mainly provides functions such as product protection, heat dissipation, and circuit conduction, and the test phase detects whether the function of the product is normal. Since the advantages and disadvantages of the packaging stage have a great influence on the quality of the semiconductor process and the subsequent application level, the packaging technology applied in the packaging stage often changes with the trend of the semiconductor market, resulting in many different packaging technologies developed in the market. For example, Flip Chip Package, Stacked Die Package, Chip Scale Package, and the like.

Although the market is full of packaging technology, in order to meet the trend of electronic products towards light and thin, all packaging technology can not escape a principle, that is, how to make the volume after packaging more light and thin. Furthermore, because the thin and light package volume has the advantages of cost reduction and space saving, the ideal packaging technology not only provides product protection, heat dissipation and circuit conduction, but also must move toward a thin and light package size, which can be favored by the market. .

Furthermore, conventional packaging techniques must be packaged using a substrate having a thickness (approximately 200 microns), such as a common leadframe or copper substrate. Since the conventional packaging technology is still unable to complete the package and have the same package quality with a large reduction in the thickness of the substrate, the packaged product cannot be significantly thinned.

In view of this, how to provide a semiconductor packaging technology to ensure that the volume after packaging is thinner and thinner is an urgent need of the industry.

It is an object of the present invention to provide a substrate process, a package method, a package structure, and a system level package structure for a semiconductor package. The substrate process, the packaging method, the package structure and the system-in-package structure of the present invention are packaged by using a patterned metal foil as a substrate of a package, which effectively improves the lack of packaging of a substrate having a certain thickness by conventional packaging technology.

In particular, since the thickness of the patterned metal foil is much smaller than the thickness of the substrate used in the conventional packaging technology, the volume after packaging is effectively thinned compared to the conventional packaging technology. On the other hand, when applied to the system-in-package type, the system-level package structure of the present invention not only reduces the space of one substrate compared with the conventional packaging technology, but also increases the flexibility of the circuit connection between the packages.

To achieve the above object, the present invention provides a substrate process for a semiconductor package, the substrate process comprising the following steps:

1. Providing a metal foil (Metal Foil), the metal foil comprising a first surface and a second surface;
2. Forming a patterned resist layer on the first surface and the second surface, respectively;
3. Forming at least one connection pad on each of the patterned resist layers;
4. The metal foil is etched.

To achieve the above object, the present invention further provides a packaging method for a semiconductor package, the packaging method comprising the following steps:

1. Providing a metal foil, the metal foil comprising a first surface and a second surface;
2. Forming a patterned resist layer on the first surface and the second surface of the metal foil;
3. Forming at least one connection pad on each of the patterned resist layers;
4. Pressing the second surface of the metal foil onto a release layer of a carrier;
5. Etching the metal foil to form a patterned metal foil;
6. Forming at least one semiconductor component on the patterned resist layer of the first surface of the patterned metal foil;
7. Electrically connecting the at least one semiconductor component to the at least one connection pad of the first surface;
8. Encapsulating a space on the carrier; and
9. Remove the carrier.

To achieve the above object, the present invention further provides a package structure for a semiconductor package, wherein the package structure comprises a package and a patterned metal foil. The patterned metal foil is disposed in the package and includes a first surface, a second surface, and at least one semiconductor component. The first surface has a first patterned resist layer thereon, wherein the first patterned resist layer has at least one first connection pad thereon. The second surface has a second patterned resist layer thereon, wherein the second patterned resist layer has at least one second connection pad exposed to the outside of the package. The at least one semiconductor component is disposed on the first patterned resist layer of the first surface of the patterned metal foil and electrically connected to the at least one first connection pad.

To achieve the above object, the present invention further provides a system-in-package structure for a semiconductor package, wherein the system-in-package structure comprises a package structure, a substrate, and a wafer device.

The package structure includes a package and a patterned metal foil. The patterned metal foil is disposed in the package and includes a first surface, a second surface, and at least one semiconductor component. The first surface has a first patterned resist layer thereon, wherein the first patterned resist layer has at least one first connection pad thereon. The second surface has a second patterned resist layer thereon, wherein the second patterned resist layer has at least one second connection pad exposed to the outside of the package. The at least one semiconductor component is disposed on the first patterned resist layer of the first surface of the patterned metal foil and electrically connected to the at least one first connection pad.

The substrate has at least one substrate connection pad, wherein the substrate connection pad is electrically connected to the at least one second connection pad on the second surface of the patterned metal foil. The wafer device is disposed to be bonded between the package structure and the substrate. The wafer device has at least one wafer connection pad, wherein the wafer connection pad is electrically connected to the at least one second connection pad on the second surface of the patterned metal foil.

Other objects of the present invention, as well as the technical means and embodiments of the present invention, will be apparent to those of ordinary skill in the art.

The present invention is not limited by the embodiments, and the embodiments of the present invention are not intended to limit the invention to any specific environment, application or special mode as described in the embodiments. Therefore, the description of the embodiments is merely illustrative of the invention and is not intended to limit the invention. It should be noted that in the following embodiments and drawings, components that are not directly related to the present invention have been omitted and are not shown, and the dimensional relationships between the components in the drawings are merely for easy understanding and are not intended to limit the actual implementation. proportion. Further, in the following embodiments, elements having the same reference numerals may be regarded as the same unless otherwise specified.

A first embodiment of the present invention is a packaging method for a semiconductor package. Figure 1 is a flow chart of a first embodiment. As shown in FIG. 1, in step S101, a metal foil is provided, the metal foil comprising a first surface and a second surface. In step S103, a patterned resist layer is formed on the first surface and the second surface of the metal foil. In step S105, at least one connection pad is formed on each of the patterned resist layers. In step S107, the second surface of the metal foil is pressed onto a release layer of a carrier, and in step S109, the metal foil is etched to form a patterned metal foil. In step S111, at least one semiconductor component is disposed on the patterned resist layer on the first surface of the metal foil. In step S113, the at least one semiconductor component is electrically connected to the at least one connection pad of the first surface. In step S115, a space on the carrier board is packaged. In step S117, the carrier is removed.

Figure 2A is a schematic cross-sectional view of one of the metal foils. As shown in FIG. 2A, a metal foil 21 is used as a substrate, and the metal foil 21 includes a first surface 21 and a second surface 23. The material of the metal foil 21 is copper (Cu), and its thickness H1 is substantially 35 micrometers (μm). It should be noted that the material of the metal foil 21 is not limited to copper, and the materials which can be easily replaced by those skilled in the art are within the scope of protection claimed in the present application. Further, the thickness H1 of the metal foil 21 is substantially 35 μm, which is a preferred embodiment of the present embodiment, and the thickness H1 of the metal foil 21 can be made lighter and thinner according to the related art.

As shown in FIG. 2B, a patterned resist layer 231 is formed on one of the first surfaces 23 of the metal foil 21, and a patterned resist layer 251 is formed on the second surface 25 of the metal foil 21. The first surface 23 covered by the patterned resist layer 231 and the second surface 25 covered by the patterned resist layer 251 are protected from being etched. In addition, the patterned resist layer 231 and the patterned resist layer 251 can increase the tensile strength and the hardness of the metal foil 21, and the base metal foil 21 is relatively strong and is not easily damaged. It should be noted that the range of the patterned resist layer 231 and the range of the patterned resist layer 251 may be the same or different.

Further, the material of the patterned resist layer 231 and the patterned resist layer 251 is nickel (Ni), and the thickness thereof is substantially in the range of 2 to 5 μm. However, the material of the patterned resist layer 231 and the patterned resist layer 251 is not limited to nickel, and materials which can be easily replaced by those skilled in the art are within the scope of the claimed invention. In addition, the thickness of the patterned resist layer 231 and the patterned resist layer 251 is substantially between 2 and 5 micrometers, which is a preferred embodiment of the present embodiment, and is not intended to limit the present invention.

As shown in FIG. 2C, at least one first connection pad 2311 is formed on the patterned resist layer 231, and the patterned resist layer 251 is formed with at least one second connection pad 2511.

Further, the material of the first connection pad 2311 and the second connection pad 2511 is gold (Au), and the thickness thereof is substantially less than 0.2 μm. However, the materials of the first connection pads 2311 and the second connection pads 2511 are not limited to gold, and materials that can be easily replaced by those skilled in the art are within the scope of the claimed invention. In addition, the thickness of the first connection pad 2311 and the second connection pad 2511 is substantially less than 0.2 micrometers, which is a preferred embodiment of the embodiment, and is not intended to limit the invention.

As shown in FIG. 2D, the second surface 25 of the metal foil 21 is pressed onto one of the release layers 203 of a carrier 201. The release layer 203 can be a gel material for accepting the second surface 25 of the metal foil 21, and the carrier 201 can be a rigid material for supporting the substrate.

As shown in FIG. 2E, the metal foil 21 is etched by an etching technique to etch the surface of the metal foil 21 not covered by the patterned resist layer 231 and the patterned resist layer 251, and a patterned metal foil 21a is formed. Only the patterned resist layer 231 is present on the first surface 23 of the patterned metal foil 21a, and only the patterned resist layer 251 is present on the second surface 25 of the patterned metal foil 21a. It is easily understood by those skilled in the art how to etch the metal foil 21 to form the patterned metal foil 21a, which will not be described herein.

It should be noted that in other embodiments, the steps described in FIG. 2D and FIG. 2E may be mutually adjusted. Specifically, the step of etching the metal foil 21 can be performed before the second surface 25 of the metal foil 21 is pressed onto one of the release layers 203 of the carrier 201, and can be easily understood by those skilled in the art. After the steps described in the 2D diagram and the 2E diagram are mutually reversed, they are still within the scope of the claimed protection.

As shown in FIG. 2F, a patterned semiconductor layer 233 is disposed on the patterned resist layer 231 of the first surface 23 of the patterned metal foil 21a. Further, the semiconductor element 233 is bonded to the patterned resist layer 231 of the first surface 23 of the patterned metal foil 21a through a die attach film (DAF) technique. In other words, the semiconductor element 233 and the patterned resist layer 231 of the first surface 23 of the patterned metal foil 21a have a die-bonding film (not shown).

The number of semiconductor elements 233 disposed on the patterned resist layer 231 of the first surface 23 of the patterned metal foil 21a is for illustrative purposes only and is not intended to limit the invention, so that the number of semiconductor elements 233 disposed may be increased. Bonding the semiconductor device 233 to the patterned resist layer 231 of the first surface 23 of the patterned metal foil 21a by a die bonding film technique is a preferred embodiment of the present embodiment, and can be easily replaced by those skilled in the art. The bonding technology is within the scope of the protection claimed in this case. Further, other passive components (not shown) may be disposed on the patterned resist layer 231 of the first surface 23 of the patterned metal foil 21a to form a circuit having a different function from the semiconductor component 233.

As shown in FIG. 2G, the semiconductor element 233 is electrically connected to the first connection pad 2311 of the first surface 23 of the patterned metal foil 21a through a wire-bonding or electrical connection technique. The electrical connection through the wire bonding technology is a preferred embodiment of the embodiment, and the connection technology that can be easily replaced by those skilled in the art is within the scope of the claimed invention.

As shown in FIG. 2H, a space 200 on the carrier 201 is packaged by a molding process to protect all components on the carrier 201. The encapsulation through the injection molding process is a preferred embodiment of the embodiment, and the connection technology that can be easily replaced by those skilled in the art is within the scope of the claimed invention.

As shown in FIG. 2I, after the space 200 on the carrier 201 is packaged, the carrier 201 will be removed to form a package structure 2 for a semiconductor package. Further, the package structure 2 produced by the steps described in FIG. 2A-2I has a thickness H1 of the patterned metal foil 21a which is much smaller than the thickness of the substrate (about 200 micrometers) used in the conventional packaging technology, so the packaged volume Compared with the traditional packaging technology, it has been effectively thinned and can still maintain the original strength.

A second embodiment of the present invention is a substrate process for a semiconductor package. For the substrate process of the present embodiment, please refer to FIG. 2A, FIG. 2B, FIG. 2C and FIG. 2E and the related description of the first embodiment. In the present embodiment, the order of execution of the steps in accordance with FIGS. 2A, 2B, 2C, and 2E is a preferred embodiment, but is not intended to limit the present invention. In addition, those skilled in the art can easily understand that the order of execution of the steps described in FIG. 2A, FIG. 2B, FIG. 2C, and FIG. 2E is still claimed in the present invention based on the inventive spirit of the present invention. range.

A third embodiment of the present invention is a package structure for a semiconductor package. For the package structure of this embodiment, please refer to FIG. 2I and the related description of the first embodiment. Specifically, the package structure of the embodiment can be identical to the package structure 2 of the first embodiment. In other words, the package structure 2 completed by the packaging method of FIG. 2A-2I is the package structure of the embodiment.

It should be noted that the execution sequence of each step described in FIG. 2A-2I is a preferred embodiment of the embodiment, and is not intended to limit the present invention. In addition, those skilled in the art can easily understand that the order of execution of the steps described in FIG. 2A-2I is still within the scope of the claimed invention based on the spirit of the invention.

A fourth embodiment of the present invention is a system in package structure 3 for a semiconductor package. FIG. 3 is a schematic cross-sectional view showing a system-level package structure 3 of the present embodiment. Specifically, based on the same inventive concept, the system-in-package structure 3 of the present embodiment includes all the features of the package structure 2 described in the third embodiment.

As shown in FIG. 3, the system-in-package structure 3 includes a package structure 2, a substrate 377, and a wafer device 355. The package structure 2 of the present embodiment can be identical to the package structure 2 described in the first embodiment and the third embodiment, and has the same technical features; and the wafer device 355 can be regarded as a semiconductor device having a conventional package structure, and can also be regarded as A semiconductor device having a package structure 2.

Further, this embodiment bonds the wafer device 355 and the package structure 2, and the bonding wafer device 355 and the substrate 377 through a die bonding film technology, so that between the wafer device 355 and the package structure 2, and between the wafer device 355 and the substrate 377 Having a die-bonding film (not shown in the drawings) is a preferred embodiment of the present embodiment, and the bonding technology which can be easily replaced by those skilled in the art is within the scope of the claimed invention. It should be noted that the wafer device 355 and the package structure 2 of the present embodiment bond the first surface 23 of the package structure 2 toward the wafer device 355, that is, the package structure 2 is inverted upside down and bonded.

As shown in FIG. 3, the substrate 355 has at least one substrate connection pad 3551, and the wafer device 377 also has at least one wafer connection pad 3771; and the number of substrate connection pads 3551 of the substrate 355 and the wafer connection pad 3771 of the wafer device 377 The quantity can also be different.

Further, the second connection pad 2511 on the second surface 25 of the patterned metal foil 21a of the package structure 2 is electrically connected to the second connection pad 2511 of the patterned metal foil 21a of the package structure 2 through a wire bonding or electrical connection technology, and electrically connected to the wafer connection pad 3771 The second connection pad 2551 on the second surface 25 of the patterned metal foil 21a of the package structure 2, the package structure 2 of the system package structure 3, the wafer device 377 and the substrate 355 are electrically connected to each other.

On the other hand, a space 300 on the substrate 355 is packaged by an injection molding process to protect all of the components on the substrate 355. The encapsulation through the injection molding process is a preferred embodiment of the embodiment, and the connection technology that can be easily replaced by those skilled in the art is within the scope of the claimed invention.

Since the system-in-package structure 3 includes the package structure 2 described in the first embodiment and the third embodiment, it also has the advantage of making the packaged volume lighter and thinner. In addition, compared with the conventional system-level packaging technology, the structure of the system-level package structure 3 can reduce the flexibility of the circuit connection between the packages by reducing the repetitive connection between the packages, that is, the system-level package structure 3 The circuit connection configuration between the package structure 2, the wafer device 377 and the substrate 355 can increase the elastic variation of the possible application of the patterned metal foil 21a of the package structure 2, for example, the wiring connection design may include The jumper design is designed to simplify the complexity of subsequent electrical connections, making it more flexible in operation.

A fifth embodiment of the present invention is another system in package structure 4 for a semiconductor package. FIG. 4 is a schematic cross-sectional view showing a system-level package structure 4 of the present embodiment. This embodiment is essentially the same as the fourth embodiment, with the main difference being the second connection on the second surface 25 of the patterned metal foil 21a of the package structure 2 of the wafer connection pad 3771 of the wafer device 377 of the system-in-package structure 4. The pads 2551 are not electrically connected using wire bonding techniques. Specifically, the wafer connection pad 3771 of the wafer device 377 of the system-in-package structure 4 is electrically connected to the second surface 25 of the patterned metal foil 21a of the package structure 2 through a conductor post 3773 (Conductive Pillar). Connect the pad 2551.

Further, between the wafer connection pad 3771 of the wafer device 377 of the system-in-package structure 4 and the second connection pad 2551 on the second surface 25 of the patterned metal foil 21a of the package structure 2 through a through via technique A connecting channel can be formed, and the conductor post 3773 is formed by filling the connecting channel with an electrically conductive material. Through the electrical conduction characteristics of the conductor post 3773, the wafer connection pad 3771 of the wafer device 377 and the second connection pad 2551 on the second surface 25 of the patterned metal foil 21a of the package structure 2 will be electrically connected.

Since the system-in-package structure 4 includes the package structure 2 described in the first embodiment and the third embodiment, it also has the advantage of making the packaged volume lighter and thinner. In addition, compared with the conventional system-level packaging technology, the structure of the system-level package structure 4 can reduce the flexibility of the circuit connection between the packages by reducing the repetitive connection between the packages, that is, the system-level package structure 4 The wiring structure configuration of the package structure 2, the wafer device 377, and the substrate 355 can be more flexible.

In summary, the substrate manufacturing process, the packaging method, the package structure, and the system-in-package structure for a semiconductor package of the present invention are packaged by using a metal foil as a substrate of a package, which has effectively improved the conventional packaging technology. The substrate of a certain thickness is missing from the package. In particular, since the thickness of the metal foil is much smaller than the thickness of the substrate used in the conventional packaging technology, the volume after packaging has been effectively thinned compared to the conventional packaging technology. On the other hand, when applied to the system-in-package type, the system-level package structure of the present invention not only reduces the space of one substrate compared with the conventional packaging technology, but also increases the flexibility of the circuit connection between the packages.

The embodiments described above are only intended to illustrate the embodiments of the present invention, and to explain the technical features of the present invention, and are not intended to limit the scope of protection of the present invention. Any changes or equivalents that can be easily made by those skilled in the art are within the scope of the invention. The scope of the invention should be determined by the scope of the claims.

2. . . Package structure

200. . . space

201. . . Carrier board

203. . . Release layer

twenty one. . . Metal foil

21a. . . Patterned metal foil

twenty three. . . First surface

231. . . First patterned resist

233. . . Semiconductor component

2311. . . First first connection pad

25. . . Second surface

251. . . Second patterned resist

2511. . . Second first connection pad

3. . . System level package structure

300. . . space

355. . . Substrate

3551. . . Substrate connection pad

377. . . Wafer device

3771. . . Wafer connection pad

3773. . . Conductor column

4. . . System level package structure

H1. . . Thickness of metal foil

Figure 1 is a flow chart of a first embodiment of the present invention;

2A-2I is a schematic diagram of a packaging process according to a first embodiment of the present invention;

3 is a schematic cross-sectional view showing a system-level package structure 3 of a fourth embodiment of the present invention;

Figure 4 is a cross-sectional view showing a system-level package structure 4 of a fifth embodiment of the present invention.

no

Claims (16)

A substrate process for a semiconductor package, the substrate process comprising the following steps:
(a) providing a metal foil (Metal Foil), the metal foil comprising a first surface and a second surface;
(b) forming a patterned resist layer on the first surface and the second surface, respectively;
(c) forming at least one connection pad on each of the patterned resist layers; and (d) etching the metal foil to form a patterned metal foil. The substrate process of claim 1, wherein the patterned resist layer is used to increase tensile strength and hardness of the metal foil. A packaging method for a semiconductor package, the packaging method comprising the following steps:
(a) providing a metal foil, the metal foil comprising a first surface and a second surface;
(b) forming a patterned resist layer on the first surface and the second surface of the metal foil, respectively;
(c) forming at least one connection pad on each of the patterned resist layers;
(d) pressing the second surface of the metal foil onto a release layer of a carrier;
(e) etching the metal foil to form a patterned metal foil;
(f) providing at least one semiconductor component on the patterned resist layer of the first surface of the patterned metal foil;
(g) electrically connecting the at least one semiconductor component to the at least one connection pad of the first surface;
(h) encapsulating a space on the carrier; and (i) removing the carrier. The encapsulation method of claim 3, wherein the patterned resist layer is used to increase tensile strength and hardness of the metal foil. The encapsulation method of claim 3, wherein the step (f) is to pattern the at least one semiconductor component on the first surface of the patterned metal foil through a die attach film (DAF) On the resist layer. The encapsulation method of claim 3, wherein the step (f) further comprises the following steps:
(f1) providing at least one passive component on the patterned resist layer of the first surface of the patterned metal foil. The encapsulation method of claim 3, wherein the step (h) encapsulates the space on the carrier through a molding process. A package structure for a semiconductor package, comprising:
a package
A patterned metal foil, disposed in the package, comprising:
a first surface having a first patterned resist layer on the first surface, the first patterned resist layer having at least one first connection pad, and a second surface having a second surface a second patterned resist layer having at least one second connection pad exposed to the outside of the package; and at least one semiconductor component disposed on the first surface of the patterned metal foil The first patterned resist layer is electrically connected to the at least one first connection pad. The package structure of claim 8, wherein the first patterned resist layer and the second patterned resist layer are used to increase a tensile strength and a hardness of the metal foil. The package structure of claim 8, wherein the at least one semiconductor component and the first patterned resist layer of the first surface of the patterned metal foil have a die-bonding film. The package structure of claim 8, wherein the package structure further comprises at least one passive component disposed on the first patterned resist layer of the first surface of the patterned metal foil. A System-in-Package (SIP) structure for a semiconductor package, comprising:
A package structure comprising:
a package
A patterned metal foil, disposed in the package, comprising:
a first surface having a first patterned resist layer on the first surface, the first patterned resist layer having at least one first connection pad, and a second surface having a second surface a second patterned resist layer having at least one second connection pad exposed to the outside of the package; and at least one semiconductor component disposed on the first surface of the patterned metal foil The first patterned resist layer is electrically connected to the at least one first connection pad;
a substrate having at least one substrate connection pad electrically connected to the at least one second connection pad on the second surface of the patterned metal foil; and a wafer device bonded to the package structure and the Between the substrates, and having at least one wafer connection pad electrically connected to the at least one second connection pad on the second surface of the patterned metal foil. The system-in-package structure of claim 12, wherein the wafer connection pad of the wafer device is electrically connected to the at least one second surface on the second surface of the patterned metal foil through a conductive pillar (Conductive Pillar) A connection pad is formed in the package of the package structure. The system-in-package structure of claim 12, wherein the first patterned resist layer and the second patterned resist layer are used to increase a tensile strength and a hardness of the metal foil. The system-in-package structure of claim 12, wherein between the at least one semiconductor component and the first patterned resist layer of the first surface of the patterned metal foil, between the wafer device and the package structure And a die-bonding film between the wafer device and the substrate. The system-in-package structure of claim 12, wherein the package structure further comprises at least one passive component disposed on the first patterned resist layer of the first surface of the patterned metal foil .