KR100745863B1 - Crc operation unit and crc operation method - Google Patents

Abstract

The present invention relates to a CRC arithmetic unit and a CRC arithmetic method for flexibly applying various generator polynomials by performing high-speed CRC arithmetic without significantly increasing the circuit scale. In general, a CRC calculation device is constructed by adding a circuit to a circuit in which a DSP is provided. The CRC calculation device includes a first general register 12 storing an arbitrary generator polynomial, The memory 22, the shift register 23, the second general purpose register 24, and the barrel shifter 25, which have a selector 13 for selecting and outputting data having a value of 0 A calculation data supply unit 21 for outputting calculation data for CRC calculation based on the transmission / reception data, a generation polynomial supply unit 11, and a generation polynomial and calculation data output from the calculation data supply unit 21, And an arithmetic instruction execution control unit 41 for controlling the operations of the respective units.

Generator polynomial, barrel shifter, operation data

Description

{CRC OPERATION UNIT AND CRC OPERATION METHOD}

1 is a block diagram showing a configuration of a CRC calculation apparatus according to the first embodiment

2 is a flow chart showing the operation of the CRC calculation apparatus of the first embodiment.

3 is an explanatory diagram showing an example of a data section of the CRC arithmetic unit of the first embodiment

4 is an explanatory diagram showing a specific example of the encoding operation of the CRC arithmetic unit of the first embodiment

5 is an explanatory diagram showing a specific example of the decoding operation of the CRC arithmetic unit of the first embodiment

6 is a block diagram showing a configuration of a CRC calculation apparatus according to the second embodiment

The present invention relates to a CRC (Cyclic Redundancy Check), which is an error detection code for detecting whether or not an error occurs in the transmission / reception data, such as when transmission / reception data is transmitted through a communication path or when data is processed for transmission, And a CRC calculation device and a CRC calculation method for detecting a code error of transmission / reception data added with an error detection code.

CRC is a frequently used error detection method in digital communication. This error detection method detects an error as follows. In other words, the transmission side regards the transmission data as a higher-order polynomial and adds the remainder obtained by dividing the transmission data by a predetermined generating polynomial to a CRC code next to the transmission data (coding). On the receiving side, the same generation polynomial is used to perform division (decode). If the remainder is 0, it is determined that there is no error in the transmitted data. If the remainder is not 0, it is determined that there is an error (error detection). As the generation polynomial, for example, the following is used in the actual CRC.

(1) CRC-12

(2) CRC-16

(3) CRC-CCITT

An apparatus for performing the above-described encoding and error detection, that is, a CRC calculation, includes a CRC calculation apparatus that performs CRC calculation in hardware. This uses a divider configured by combining a shift register and an exclusive OR gate. In this kind of apparatus, the generation polynomial is determined according to how the shift register and the exclusive-OR gate are connected. This makes it impossible to change the generator polynomial in this kind of device. Therefore, it is necessary to use a different device for each generation polynomial to be applied. In addition, a device to which the same generating polynomial is applied on the transmitting side and the receiving side should be used.

Meanwhile, as a CRC calculation device capable of flexibly applying various generation polynomials, there is a CRC calculation device using software. In such an apparatus, various generating polynomials can be easily applied simply by replacing a program or data. Conventionally, the CRC calculation is executed by the processor of the communication terminal, and the processing load of the communication terminal is deteriorated because a large load is imposed on the processor. In addition, CRC calculation by software is not suitable for high-speed communication because of low computation speed.

Therefore, for example, as disclosed in Japanese Unexamined Patent Application Publication No. 5-151007, a combination of a generator polynomial setting register, a shift register, and an exclusive OR gate may be used as a device capable of making both the flexibility of the generating polynomial and the high- A device is known. This device can apply various generation polynomials by changing the generator polynomial set in the generator polynomial setting register while enabling high-speed processing because the CRC operation is performed by hardware.

However, the above-mentioned CRC calculation device has a problem of increasing the circuit scale of the communication device and the like because it uses a specialized dedicated circuit for CRC calculation. The generator polynomial of the same bit length as the generator polynomial setting register can be applied to various kinds of polynomials, but the application of the generator polynomial of different bit length is not considered.

SUMMARY OF THE INVENTION In view of the above problems, it is an object of the present invention to provide a CRC calculation device and a CRC calculation method capable of performing a high-speed CRC calculation without causing a significant increase in circuit scale and flexibly applying various generation polynomials do.

In order to achieve the above object, according to the present invention, there is provided a CRC arithmetic unit comprising: generating polynomial supplying means for holding data representing a generating polynomial and selectively outputting data representing the generating polynomial and zero data of all bits of O; And an arithmetic logic operation means for performing an exclusive OR operation on the data or zero data indicating the generated polynomial and the operation data, wherein the generating polynomial supplying means comprises: Wherein the arithmetic logic unit is configured to select data and zero data representing the generator polynomial according to a value of a most significant bit of an arithmetic logic operation result by the arithmetic logic unit, The value of the lower bit is set to the value of the upper bit, and the value of the unprocessed CRC year And outputs the data having the value of the most significant bit of the data to be subjected to the multiplication as the value of the least significant bit as the calculation data.

Specifically, the generating polynomial supplying means includes, for example, a first register for holding data representing the generating polynomial, and a selector for selectively outputting data representing the generating polynomial or the zero data, More specifically, for example, the means may include: a second register for holding the operation result by the arithmetic logic operation means; a shifter for shifting the operation result held in the second register by one bit to the left and outputting the shifted result; A memory for holding data to be subjected to the CRC operation and a memory for storing a part of the data to be subjected to the unprocessed CRC calculation sent from the memory and outputting a value of a most significant bit of the held data, And a shift register that shifts left by one bit.

This makes it easy to flexibly apply various generation polynomials by changing the data indicating the generation polynomial held in the generation polynomial supplying means. In addition, selection of data or zero data indicating the generator polynomial and input of the arithmetic logic operation means and generation of operation data for performing CRC operation are automatically performed irrespective of the execution of the program command, so that high-speed CRC operation can be performed. In addition, since the generator polynomial supply means, the supply means, and the arithmetic logic operation means can mainly use components provided with a normal processor, the increase in the circuit scale of the entire apparatus including the CRC calculation apparatus can be suppressed to a small extent.

Wherein said calculation instruction execution control means includes means for outputting data or zero data indicating said generation polynomial by said generation polynomial supply means in accordance with a predetermined calculation instruction, And to control the output of the calculation data and the execution of the exclusive-OR calculation by the arithmetic logic calculation means.

Wherein said calculation instruction execution control means comprises: a generation polynomial supply means for performing the exclusive-OR computation by said arithmetic logic operation means one time in accordance with a predetermined operation instruction; an operation by said operation data supply means and said arithmetic logic operation means; .

Wherein said generation polynomial supply means, said calculation data supply means, and said arithmetic logic means for performing the exclusive-OR calculation by said arithmetic logic calculation means on all of the data to be subjected to said unprocessed CRC calculation in accordance with a predetermined calculation instruction, And to control the operation by the calculation means.

And the arithmetic logic operation means performs the exclusive-OR operation on the values of all the bits held in the shift register in accordance with a predetermined arithmetic operation instruction, the arithmetic data supply means and the arithmetic logic operation And to control operation by means.

As a result, it is possible to improve the flexibility of the CRC calculation processing by increasing the degree of freedom of the combination of the calculation instructions, or to improve the CRC calculation processing with the fewer calculation instructions.

And to store, in the memory, a value held in the second register after the exclusive OR operation by the arithmetic logic unit is performed on all of the data to be subjected to the unprocessed CRC operation.

Wherein the CRC operation is performed on the basis of whether or not the value held in the second register is 0 after the exclusive OR operation by the arithmetic logic operation means is performed on all of the data to be subjected to the unprocessed CRC operation, And to determine whether or not there is an error in the data.

This makes it easy to perform CRC encoding and error detection of data.

The generator polynomial supply means holds the data representing the generator polynomial in the upper padding when the number of bits of the data representing the generator polynomial is smaller than the number of bits that the generator polynomial supply means can hold, Value.

This makes it possible to improve the flexibility of the generator polynomials applied to the number of bits as well as to the types of generator polynomials.

In addition, the present invention provides a CRC arithmetic apparatus comprising generator polynomial holding means for holding data representing a generator polynomial, CRC arithmetic means for performing CRC arithmetic based on data representing a generator polynomial and data subjected to a CRC arithmetic operation, When the number of bits of data representing the generator polynomial is smaller than the number of bits that the generator polynomial holding means can hold, data indicating the generator polynomial is held in the generator polynomial holding means as upper padding, Is held.

This makes it possible to increase the flexibility of the generator polynomial to be applied to the number of bits of the generated polynomial as well as the type of the generated polynomial even when a dedicated circuit specialized for CRC calculation is constructed.

(Embodiment 1)

An example of a CRC calculation apparatus installed in a processor such as a DSP (digital signal processor) as an embodiment of the present invention will be described with reference to Fig. This device is generally constructed by adding a little circuit to a circuit equipped with a DSP.

As shown in Fig. 1, the CRC arithmetic unit is provided with a generator polynomial supply unit 11 (generator polynomial supply unit) for holding and outputting an arbitrary generator polynomial, and a CRC generator 11 for generating CRC An arithmetic data supplying unit 21 for supplying arithmetic data and arithmetic operation unit for performing a CRC operation using the generated polynomial and arithmetic data output from the generating polynomial supplying unit 11 and the arithmetic data supplying unit 21 31 (arithmetic logic operation means), and an operation instruction execution control section 41 (operation instruction execution control means) for controlling the operation of each section.                     

The generator polynomial supply unit 11 includes a first general register 12 in which a generator polynomial is stored and a second polynomial in which the value stored in the first general register 12 (generator polynomial) And a selector 13 for selecting and outputting the data. More specifically, the selector 13 selects "0" when the value of the most significant bit (MSB) of the second general-purpose register 24 is 0, and when the value of the most significant bit (MSB) of the second general- As shown in FIG. The selector 13 may actually be constituted by an AND circuit column or the like which performs an AND operation between the value of each bit of the first general purpose register 12 and the value of the MSB of the second general purpose register 24. [

The operation data supply unit 21 includes a memory 22, a shift register 23, a second general purpose register 24, and a barrel shifter 25.

The memory 22 stores transmission / reception data.

The shift register 23 outputs the value of the MSB of the data held for each cycle of the CRC operation to the arithmetic unit 31 as the LSB value of the arithmetic data, and then shifts the data leftward by one bit. When the value of all the bits of the held data is outputted, the next data is transferred from the memory 22.

The second general purpose register 24 holds the data transferred from the memory 22 as an initial value when the CRC operation is started and at the same time stores the data of the operation result outputted from the operation unit 31 for each one cycle of CRC operation Respectively.

The barrel shifter 25 left-shifts the data held in the second general-purpose register 24 by one bit, and outputs a value of an upper bit higher than the LSB to the arithmetic unit 31 as a value of a higher-order bit than the LSB of the operation data . The value of the MSB of the shift register 23 may be input to the barrel shifter 25 instead of directly inputting the value of the MSB of the shift register 23 to the value of the LSB of the operation data at the time of the left shift.

The operation unit 31 includes an arithmetic logic operator 32 and performs an exclusive OR operation on the generated polynomial or "0" output from the generator polynomial supply unit 11 and the operation data output from the operation data supply unit 21 . The data of the operation result is stored in the second general-purpose register 24 as described above.

Each of the parts has a bit width of, for example, M bits.

The calculation instruction execution control section 41 mainly controls the operations of the respective sections constituting the DSP on the basis of the operation instructions given as the programs, and controls the operations of the respective sections mainly based on the operation instructions related to the CRC operation.

The first general purpose register 12, the memory 22, the second general purpose register 24, the barrel shifter 25, and the arithmetic logic unit 32 may be those provided by a processor. That is, in particular, it is a part having a control function for the CRC operation in the operation instruction execution control unit 41 and the signal path between the selector 13, the shift register 23, Therefore, it is possible to construct a CRC arithmetic unit only by adding these components to a general processor, and since the entire CRC arithmetic unit is not specialized in CRC arithmetic, the increase in the overall circuit scale of the DSP and the like can be suppressed to a small extent.

In the CRC calculation apparatus configured as described above, the CRC calculation is performed in accordance with the calculation instruction given to the calculation instruction execution control unit 41. [ Hereinafter, the operation will be described on the basis of the flowchart of Fig. 2 (and each of the following steps is for convenience of explanation, and does not necessarily correspond to a command cycle or a machine cycle on a one-to-one basis).

(Step S1) The generator polynomial is set in the first general register 12 by the first transfer instruction. If the bit length of the generator polynomial set here is N, then N < M (M is the bit width of the first general purpose register 12). In this case, a value padded by high-order by a left shift instruction or the like and 0 is embedded in the lower bit is set in the first general purpose register 12.

(Step S2) Similarly, the first M-bit data (initial data) in the transmission / reception data stored in the memory 22 is set in the second general-purpose register 24 by the transmission instruction.

(Step S3) The next M bits of data (input data 1 to X) are set in the shift register 23 by the transfer instruction.

(Step S4) Next, the CRC operation of the M cycle, that is, the CRC operation corresponding to the M-bit transmission / reception data held in the shift register 23, is executed. More specifically, the following operations are performed.

That is, the arithmetic logic operator 32 determines whether the value held in the second general-purpose register 24 is the value of the upper M-1 bit among the values shifted out from the barrel shifter 25 as described above, (Including N bits and 0s) of the M bits output from the selector 13 and the data of which the value of the entire bit is 0 And the data of the operation result is stored in the second general-purpose register 24. The second general- That is, one cycle of CRC calculation corresponding to one-bit transmission / reception data. The value held in the shift register 23 is shifted left by 1 bit, and 0 is embedded in the LSB. These operations are repeated M times, for example, by a repetition instruction (instruction indicating repetition of a subsequent instruction a predetermined number of times) and a CRC operation instruction. This makes it possible, for example, to perform the CRC operation of one cycle (and the shift operation of the shift register 23 in one machine cycle), and the same operation as the operation by the combination of the repetitive instruction and the CRC operation instruction can be performed by a single instruction The CRC operation may be repeated until the value becomes 0 after the value M is set in the general register and decreased for each CRC operation of one cycle.

(Step S5) When the CRC calculation of the M cycle is completed, it is determined whether or not the remaining transmission / reception data held in the memory 22 is the final data (whether or not the remaining transmission / reception data is M bits or less). Specifically, for example, it may be determined whether or not the value of a pointer (not shown) indicating the address of the transmission / reception data transmitted from the memory 22 to the shift register 23 is the address of the final data. Counts (counts down) the number of CRC calculations in the cycle, subtracts M from the total number of bits K of the transmission / reception data, divides the integer X by M,

X = int ((K-M) / M)

It may be determined whether or not the number of times of repetition is equal to the number of repetition times. Further, the count or the determination of the number of times of the CRC operation may be performed by a program instruction or may be automatically performed by hardware (and in the case where M is subtracted from K, the first M bits are used as initial data, (24). If it is not the last data remaining in the memory 22, the above steps S3 to S5 are repeated.

(Step S6) If the transmission / reception data remaining in the memory 22 in the step S6 is determined as the final data, the final data is transferred to the shift register 23. [ Here, as shown in FIG. 3, the number of bits of the final data is the sum of the total number of bits K of the transmission / reception data,

L = (K-M) mod M

to be. Since the remaining L is smaller than M, the final data is set to the upper padding in the shift register 23 and O is embedded in the lower bits.

(Step S7) Finally, the CRC calculation of the M + L cycle is performed as in the step S4. (And the bit length M of the arithmetic logic operator 32 is added to the remaining L in the number of stages of the final CRC operation) is the end of the transmission / reception data This is because it repeats the operation until the bit is shifted to one higher bit than the MSB of the arithmetic logic operator 32. This corresponds to performing the CRC operation up to the LSB by multiplying the transmit / receive data by 2). Therefore, the value held in the second general-purpose register 24 when the CRC operation of the M + L cycles (all of the K cycles as described above) is completed in step S7 results in the CRC operation on the whole transmission / reception data. Therefore, in the case of transmission, the value held in the second general-purpose register 24 is stored in the memory 22 and added to the transmission data, for example, to become CRC-coded transmission data. In the case of reception, it is judged whether or not the value held in the second general-purpose register 24 is 0. Specifically, for example, if the value held in the second general-purpose register 24 and the value of the whole bit are 0 It is possible to determine whether or not there is an error in the received data by performing an exclusive-OR operation of the in-zero data and determining whether or not a zero flag register (not shown) is set.

Next, the above operation will be described with reference to specific data examples based on Fig. 4 and Fig.

First, an example of encoding will be described. In this example, as shown in Fig. 4, when the transmission data before encoding is "100000110101 (binary representation)" (bit number K = 12) and the generation polynomial is "10101 (binary representation) do. In this case, the repetition number X of the CRC calculation in the 5th cycle is

X = int ((K-M) / M) = int ((12-5) / 5) = 1,

The number of bits L of the final data,

L = (K-M) mod M = (12-5) mod 5 = 2,

In addition, the number of cycles of the final CRC calculation is

M + L = 5 + 2 = 7

to be.

(1) When the CRC operation is started, the generator polynomial "10101" is set in the first general purpose register 12 and the value "10000" of the first 5 bits of the transmission data is set in the second general purpose register 24, The 5-bit value &quot; 01101 &quot; is set in the shift register 23.                     

(2) In the first CRC operation cycle 1, since the value of the MSB of the second general-purpose register 24 is "1", the generator polynomial "10101" is selected by the selector 13 and the generator polynomial and the second general register 0000 &quot; of the MSB of the shift register 23 and the value &quot; 0 &quot; of the MSB of the shift register 23 are mapped to four bits (more precisely, four bits higher than the LSB after being shifted left by the barrel shifter 25) And the exclusive OR operation is performed by the logical operator 32. [ The operation result is &quot; 10101 &quot;, and the operation result is stored in the second general purpose register 24. [

(3) The value held in the shift register 23 is shifted left by one bit. In FIG. 4, the value embedded in the LSB is 0, but it does not have to be 0 (in contrast, in the final CRC calculation, it is necessary to embed 0 in order to correspond to the N-folding of the transmission data by 2).

(4) Hereinafter, the same operation is repeated. When the 5-cycle CRC operation is completed, the 2-bit final data "01" stored in the memory 22 is stored in the shift register 23 as upper padding and 0 And transmitted. The operations of (2) and (3) above are repeated for 7 cycles in the final CRC calculation.

(5) The value &quot; 00010 &quot; held in the second general-purpose register 24 when the last CRC operation is terminated is a CRC operation result. Therefore, as shown in Fig. 5, the result of the CRC calculation is added as the error detection code at the end of the original transmission data, and 17-bit coded data (&quot; 10000011010100010 &quot;) is obtained.

On the other hand, the operation in the case of decoding the coded data as described above is the same as (1) to (4) in the case of the encoding as shown in Fig. When this CRC calculation result is "00000" as shown in FIG. 5, it is determined that there is no error in the data.

Here, in this example, since the error detection code is added as described above and the bit length of the data is 17 bits, the repetition number X of the 5-cycle CRC operation is

X = int ((K-M) / M) = int ((17-5) / 5)

The number of bits L of the final data,

L = (K-M) mod M = (17-5) mod5 = 2.

In addition, the number of cycles of the final CRC calculation is

M + L = 5 + 2 = 7

5, if the remainder is 0 at the time of performing the CRC operation of 2 cycles, which is the same as the number of bits of the final data L, the remainder after the CRC operation is 0, and if the remainder is not 0, The result is the same even if the operation is stopped in two cycles. However, seven cycles may be repeated as described above, that is, the same operation may be performed in encoding and decoding, thereby simplifying the configuration.

In the above example, the bit widths of the respective constituent elements are the same, but the present invention is not limited thereto. For example, in the first general purpose register 12 and the arithmetic logic operator 32 and other constituent elements, Or the bit width may be different between the first general purpose register 12 and the like and the arithmetic logic operator 32. [

For example, in the case where received data is input as serial data, the received data may be stored in a buffer (first in first out (FIFO)) without installing the shift register 23, To the second general-purpose register 24 or to the arithmetic logic unit 32 directly.

Since the barrel shifter 25 only shifts the input data by one bit in the CRC arithmetic unit, a shift register may be used when there is a margin in the cycle time.

When a register dedicated to the CRC operation is provided in place of the second general-purpose register 24, the barrel shifter 25 may not be used by shifting the input / output by one bit.

It is also possible to use a memory instead of the first general purpose register 12 or the second general purpose register 24.

The selection control of the selector 13 is not limited to the execution according to the value of the MSB of the second general-purpose register 24 as described above. When the exclusive-OR operation is performed by the arithmetic logic operator 32, A flag register holding the MSB value may be provided and controlled according to the value held in the flag register. In this case, when the CRC operation of the first one cycle is performed, the value of the first flag register is set to the first value in the arithmetic logic operator 32 without performing a left shift (or by bypassing 25) in the barrel shifter 25 Can be set.

In addition, the above-described series of CRC calculations on all bits of the transmission / reception data may be executed by the microprogram built in the operation instruction execution control unit 41 so that the CRC operation can be instructed by one or a small number of program instructions.

(Second Embodiment)

As an example of the second embodiment, an example of a CRC arithmetic unit configured by hardware including a generator polynomial setting register and capable of applying a generator polynomial of arbitrary bit length will be described.

This CRC calculation apparatus has a CRC calculation unit 51 and a generator polynomial supply unit 61 as shown in FIG.

The CRC arithmetic unit 51 (CRC arithmetic means) is constituted by connecting predetermined D-type flip-flops 52 for M stages (for M bits) through exclusive OR gates 53 .... The CRC operation unit 51 performs CRC operation by inputting operation data one bit at a time. The quotient of the calculation result is sequentially output from the last-stage D-type flip-flop 52, and the rest is output from each D-type flip-flop 52 at the time when the CRC calculation is completed.

The generator polynomial supply unit 61 includes a generator polynomial setting register 62 (generator polynomial holding means) of M bits wide in which the generator polynomial is stored, a selector 63, and an upper padding unit 64. The selector 63 selects the value (generator polynomial) stored in the generator polynomial setting register 62 or the value of all bits of the all-bits stored in the generator polynomial setting register 62 in the same manner as the selector 13 of the first embodiment in accordance with the output from the D- ("0") whose value is zero. When the number N of bits of the generator polynomial to be applied is smaller than the bit width M of the generator polynomial setting register 62, the upper padding unit 64 high-padds the generator polynomial, (62). Specifically, for example, it may be left-shifted by a shift register, or left-shifted by a shift instruction of a program or the like. Instead of providing the upper padding unit 64, a higher-padded generation polynomial may be input in advance.

When the number of bits N of the generator polynomial is smaller than the bit width M of the generator polynomial setting register 62, 0 is embedded in the generator polynomial setting register 62 for the lower bits than the N bits of the generator polynomial, The selector 63 outputs 0 regardless of the output from the D-type flip-flop 52 at the stage. Therefore, since the same value as the value output from the previous D-type flip-flop 52 is outputted from the exclusive OR gate 53 corresponding to the lower bit, the number of bits of the generator polynomial and the bit width of the generator polynomial setting register 62 And the number of stages of the D-type flip-flop 52 are equal to each other. Therefore, the flexibility of the generator polynomial that is applied to the number of bits can be improved.

As described above, according to the present invention, it is possible to use a constituent element of a processor or the like in general, so that it is possible to perform a high-speed CRC operation without causing a significant increase in circuit scale and to apply various generation polynomials flexibly Can be obtained.

Claims (11)

Generating polynomial supplying means for holding data representing a generating polynomial and selectively outputting data indicating the generating polynomial and zero data having a value of all bits O, A calculation data supply means for outputting calculation data for performing a CRC calculation; And arithmetic and logic operation means for performing an exclusive OR operation on the data or zero data indicating the generation polynomial and the operation data, Wherein the generating polynomial supplying means is configured to select data representing the generating polynomial and zero data according to a value of a most significant bit of a calculation result by the arithmetic logic calculating means, Wherein the operation data supply means sets the lower bit value to a higher bit value than the most significant bit of the arithmetic logic operation result by the arithmetic logic operation means and sets the value of the most significant bit of the data subject to the unprocessed CRC operation as the value of the least significant bit And outputs the data as the operation data. The method according to claim 1, Wherein the generating polynomial supplying means comprises: A first register for holding data representing the generator polynomial, And a selector for selectively outputting data representing the generation polynomial or the zero data, Wherein said calculation data supply means comprises: A second register for holding the operation result by the arithmetic logic unit, A shifter shifting the result of the operation held in the second register by one bit to the left, A memory for holding the data to be subjected to the unprocessed CRC calculation; And a shift register for holding a part of the data to be subjected to the unprocessed CRC calculation sent from the memory and for outputting the value of the most significant bit of the held data and for shifting the held data leftward by one bit CRC calculation unit. The method according to claim 1, Wherein said calculation instruction execution control means includes means for outputting data or zero data indicating said generation polynomial by said generation polynomial supply means in accordance with a predetermined calculation instruction, And outputs the data and the execution of the exclusive-OR operation by the arithmetic logic operation means. The method of claim 3, Wherein said calculation instruction execution control means comprises: a generation polynomial supply means for performing the exclusive-OR computation by said arithmetic logic operation means one time in accordance with a predetermined operation instruction; an operation by said operation data supply means and said arithmetic logic operation means; To the CRC calculation unit. The method of claim 3, Wherein the calculation instruction execution control means comprises the generating polynomial supply means for performing the exclusive OR operation by the arithmetic logic operation means on all of the data to be subjected to the unprocessed CRC operation in accordance with a predetermined operation instruction, And the operation by the supply means and the arithmetic logic operation means. 3. The method of claim 2, Wherein said arithmetic instruction execution control means includes means for executing said exclusive OR operation by said arithmetic logic operation means on the values of all bits held in said shift register in accordance with a predetermined arithmetic instruction, A generating polynomial supplying means, an operation data supplying means, and the arithmetic logic operating means. 3. The method of claim 2, And stores the value held in the second register in the memory after the exclusive OR operation by the arithmetic logic operation means is performed for all of the data to be subjected to the unprocessed CRC operation. Device. 3. The method of claim 2, Wherein the CRC operation is performed on the basis of whether or not the value held in the second register is 0 after the exclusive OR operation by the arithmetic logic operation means is performed on all of the data to be subjected to the unprocessed CRC operation, And to determine whether or not there is an error in the data. The method according to claim 1, Wherein the generator polynomial supply means holds data representing the generator polynomial in an upper padding when the number of bits of data representing the generator polynomial is smaller than the number of bits that the generator polynomial supply means can hold, The CRC calculation unit comprising: Generating polynomial holding means for holding data representing a generating polynomial, And CRC calculation means for performing a CRC calculation based on data indicating a generation polynomial and data to be CRC calculated, When the number of bits of data representing the generator polynomial is smaller than the number of bits that the generator polynomial holding means can hold, data indicating the generator polynomial is held in the generator polynomial holding means as upper padding, The CRC calculation unit is configured to hold the CRC calculation result. A generating polynomial supplying step of selectively outputting data indicating a generating polynomial and zero data having a value of all bits of 0, An operation data supply step of outputting operation data for performing a CRC operation; And an arithmetic and logic operation step of carrying out an exclusive logical OR operation of the data or zero data representing the generation polynomial and the operation data, Wherein the generator polynomial supplying step selects data or zero data representing the generator polynomial according to a value of a most significant bit of an operation result by the arithmetic logic operation step preceding, Wherein the operation data supply step sets a lower bit value to a value of a higher bit than a most significant bit of the operation result by the arithmetic logic operation step and sets a value of a most significant bit of data to be subjected to an unprocessed CRC operation as a value of a least significant bit And outputs the data as the operation data.

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