KR100743657B1 - Method of manufacturing semiconductor device - Google Patents

Method of manufacturing semiconductor device Download PDF

Info

Publication number
KR100743657B1
KR100743657B1 KR1020060059826A KR20060059826A KR100743657B1 KR 100743657 B1 KR100743657 B1 KR 100743657B1 KR 1020060059826 A KR1020060059826 A KR 1020060059826A KR 20060059826 A KR20060059826 A KR 20060059826A KR 100743657 B1 KR100743657 B1 KR 100743657B1
Authority
KR
South Korea
Prior art keywords
dielectric film
low dielectric
low
semiconductor device
film
Prior art date
Application number
KR1020060059826A
Other languages
Korean (ko)
Inventor
김찬배
정채오
이효석
구자춘
Original Assignee
주식회사 하이닉스반도체
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 주식회사 하이닉스반도체 filed Critical 주식회사 하이닉스반도체
Priority to KR1020060059826A priority Critical patent/KR100743657B1/en
Application granted granted Critical
Publication of KR100743657B1 publication Critical patent/KR100743657B1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76835—Combinations of two or more different dielectric layers having a low dielectric constant
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02282—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process liquid deposition, e.g. spin-coating, sol-gel techniques, spray coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H01L21/76828—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. thermal treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

A method for fabricating a semiconductor device is provided to prevent fail of a low-k dielectric film at wire bonding by forming the low-k dielectric film in a first low-k dielectric film and a second low-k dielectric film. A first low-k dielectric film(25) is formed on a substrate through a spin on method, and then is baked to cure the first low-k dielectric film. The baked first low-k dielectric film is annealed, and a second low-k dielectric film(26) is formed on the annealed first low-k dielectric through chemical vapor deposition. A capping layer(27) is formed on the second low-k dielectric film. Before the first low-k dielectric film is formed, a linear oxide layer(24) is formed on the entire surface of the substrate comprising a metallization(23).

Description

반도체 소자의 제조방법{METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE}Manufacturing method of semiconductor device {METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE}

도 1은 종래기술의 문제점을 보여주는 사진.1 is a photograph showing the problem of the prior art.

도 2a 내지 도 2e는 본 발명의 실시예에 따른 반도체 소자의 제조방법.2A to 2E illustrate a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

*도면의 주요 부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *

21 : 반도체 기판 22 : 절연막 21 semiconductor substrate 22 insulating film

23 : 금속배선 24 : 선형산화막23: metal wiring 24: linear oxide film

25 : 제1저유전막 26 : 제2저유전막25: first low dielectric film 26: second low dielectric film

27 : 캡핑막27: capping film

본 발명은, 반도체 소자의 제조방법에 관한 것으로, 보다 상세하게는, 금속배선의 매립을 위해 저유전막을 형성할 경우 유발되는 와이어 본딩(Wire Bonding)시의 페일(Fail)을 방지하여 후속 공정(Backend Process)을 안정화시킬 수 있는 반도체 소자의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to prevent a fail during wire bonding caused when a low dielectric film is formed for embedding metal wiring. The present invention relates to a method for manufacturing a semiconductor device capable of stabilizing a backend process).

일반적으로, 반도체 소자의 제조시 소자와 소자간, 또는, 배선과 배선간을 전기적으로 연결시키기 위해 금속배선을 사용하고 있다. 한편, 최근 반도체 소자의 고집적화가 진행함에 따라 금속배선의 폭 및 콘택 면적이 감소하여 콘택저항을 비롯한 금속배선의 저항이 점차 증가하게 되었다. 또한, 상기 금속배선 및 콘택플러그 간의 간격이 좁아짐에 따라 금속배선을 절연시키는 절연막으로 인해 유발되는 기생 캐패시턴스가 증가하게 되었으며, 아울러, 금속배선간 공간의 매립 공정이 어려워지게 되었다.In general, in the manufacture of semiconductor devices, metal wirings are used to electrically connect the devices with each other or between the wirings and the wirings. On the other hand, as the integration of semiconductor devices in recent years has progressed, the width and contact area of metal wirings have decreased, and the resistance of metal wirings including contact resistances has gradually increased. In addition, as the gap between the metal wiring and the contact plug becomes narrow, parasitic capacitance caused by the insulating film insulating the metal wiring increases, and also, the process of filling the space between the metal wiring becomes difficult.

이에, 상기 금속배선의 저항을 낮추고 기생 캐패시턴스를 감소시키기 위한 다양한 공정 기술들이 연구되고 있으며, 그 일환으로서, 상기 금속배선간 공간을 매립하기 위한 절연막 물질로 매립특성이 우수하며 유전상수 값(K)이 낮은 저유전막을 사용하려는 시도가 이루어지고 있다. 상기 금속배선의 매립을 위해 저유전막을 형성하면, 기생 캐패시턴스(Parasitic Capacitance)의 형성이 방지되어 반도체 소자의 동작속도가 개선된다는 장점이 있다.Accordingly, various process technologies for lowering the resistance of the metal wiring and reducing parasitic capacitance have been studied. As part of this, an insulating film material for filling the space between the metal wirings has excellent embedding properties and a dielectric constant value (K). Attempts have been made to use this low low dielectric film. When the low dielectric film is formed to fill the metal wiring, parasitic capacitance is prevented from being formed, thereby improving the operation speed of the semiconductor device.

그러나, 상기 저유전막은 산화막 비해 상대적으로 기계적 특성이 취약하다는 단점이 있다. 이때문에, 상기 금속배선의 매립을 위해 저유전막을 형성할 경우, 패키지 공정 중 와이어 본딩(Wire Bonding)시 상기 저유전막이 패드 영역 상부에 가하는 전단 응력 및 압축 응력으로 인하여, 도 1에 도시된 바와 같이, 상기 패드 영역이 떨어져 나가게 되며, 이로 인해, 페일(Fail)이 유발된다는 문제점이 있다.However, the low dielectric film has a disadvantage in that the mechanical properties are relatively weak compared to the oxide film. For this reason, when forming a low dielectric film for embedding the metal wiring, due to the shear stress and compressive stress applied to the upper portion of the pad region during the wire bonding during the packaging process, shown in FIG. As described above, the pad area is separated, which causes a problem of failing.

따라서, 본 발명은 상기와 같은 문제점을 해결하기 위해 안출된 것으로서, 금속배선의 매립물질로서 저유전막을 사용할 경우 상기 저유전막의 취약한 기계적 특성으로 인해 유발되는 와이어 본딩(Wire Bonding)시의 페일(Fail)을 방지할 수 있는 반도체 소자의 제조방법을 제공함에 그 목적이 있다.Therefore, the present invention has been made to solve the above problems, when using a low dielectric film as a buried material of the metal wiring when the wire bonding (Fail during wire bonding) caused by the weak mechanical properties of the low dielectric film (Fail) It is an object of the present invention to provide a method for manufacturing a semiconductor device that can prevent the).

또한, 본 발명은 상기 와이어 본딩시의 페일을 방지함으로써 후속 공정(Backend Process)을 안정화시킬 수 있는 반도체 소자의 제조방법을 제공함에 다른 목적이 있다.In addition, another object of the present invention is to provide a method for manufacturing a semiconductor device capable of stabilizing a backend process by preventing a failure during the wire bonding.

상기와 같은 목적을 달성하기 위한 본 발명의 반도체 소자의 제조방법은, 금속배선의 매립을 위해 저유전막을 형성하는 반도체 소자의 제조방법에 있어서, 상기 저유전막은, 스핀-온(Spin-On) 방식으로 제1저유전막을 형성하는 단계; 상기 제1저유전막이 경화되도록 베이크하는 단계; 상기 베이크된 제1저유전막을 열처리하는 단계; 상기 열처리된 제1저유전막 상에 CVD(Chemical Vapor Deposition) 방식으로 제2저유전막을 형성하는 단계; 및 상기 제2저유전막 상에 캡핑막을 형성하는 단계;를 통해 형성한다.
여기서, 상기 제1저유전막을 형성하는 단계 전, 상기 금속배선을 포함한 기판 전면 상에 선형산화막을 형성하는 단계;를 더 포함한다.
상기 제1저유전막은 SiOCH, 폴리머 및 기공 크기를 이용하여 2.5∼2.9의 절연상수 값을 갖도록 형성한다.
상기 제1저유전막은 2000∼3000Å의 두께로 형성한다.
상기 열처리는 N2 분위기와 400∼600℃의 온도에서 30∼60분 동안 수행한다.
상기 제1저유전막은 상기 금속배선의 상부를 500∼1000Å의 두께만큼 덮도록 형성한다.
상기 제2저유전막은 2.7∼3.3의 절연상수 값을 갖도록 형성한다.
상기 제2저유전막은 3000∼6000Å의 두께로 형성한다.
상기 CVD는 600∼2000W의 소오스 파워를 사용하여 100∼200초 동안 수행한다.
상기 캡핑막은 산화막으로 형성한다.In the method of manufacturing a semiconductor device of the present invention for achieving the above object, in the method of manufacturing a semiconductor device to form a low dielectric film for embedding the metal wiring, the low dielectric film is spin-on (Spin-On) Forming a first low dielectric film in a manner; Baking the first low-k dielectric layer to cure; Heat-treating the baked first low dielectric film; Forming a second low dielectric film on the heat treated first low dielectric film by chemical vapor deposition (CVD); And forming a capping film on the second low dielectric film.
Here, before the step of forming the first low dielectric film, forming a linear oxide film on the entire surface of the substrate including the metal wiring; further includes.
The first low dielectric layer is formed to have an insulation constant value of 2.5 to 2.9 using SiOCH, polymer, and pore size.
The first low dielectric film is formed to a thickness of 2000 to 3000 kPa.
The heat treatment is carried out for 30 to 60 minutes in an N 2 atmosphere and the temperature of 400 ~ 600 ℃.
The first low dielectric film is formed to cover the upper portion of the metal wiring by a thickness of 500 to 1000 Å.
The second low dielectric film is formed to have an insulation constant value of 2.7 to 3.3.
The second low dielectric film is formed to a thickness of 3000 to 6000 kPa.
The CVD is performed for 100 to 200 seconds using a source power of 600 to 2000 W.
The capping film is formed of an oxide film.

삭제delete

삭제delete

삭제delete

삭제delete

삭제delete

삭제delete

삭제delete

삭제delete

삭제delete

삭제delete

삭제delete

(실시예)(Example)

이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시예를 상세하게 설명하도록 한다. Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

먼저, 본 발명의 기술적 원리를 간략하게 설명하면, 본 발명은 금속배선의 매립을 위한 저유전막의 형성시, 상기 금속배선이 형성된 반도체 기판 상에 스핀-온(Spin-On) 방식으로 제1저유전막을 형성한 후, 상기 제1저유전막을 베이크하고 열처리한다.
그런 다음, 상기 열처리된 제1저유전막 상에 CVD(Chemical Vapor Deposition) 방식으로 제2저유전막을 형성하고, 그리고 나서, 상기 제2저유전막 상에 산화막 재질의 캡핑막을 형성한다.First, the technical principle of the present invention will be briefly described. According to the present invention, when the low dielectric film for embedding the metal interconnection is formed, the first low-voltage layer is formed on the semiconductor substrate on which the metal interconnection is formed in a spin-on manner. After the dielectric film is formed, the first low dielectric film is baked and heat treated.
Then, a second low dielectric film is formed on the heat treated first low dielectric film by CVD (Chemical Vapor Deposition) method, and then a capping film of an oxide film is formed on the second low dielectric film.

이렇게 하면, 상기 제1저유전막 상에 형성된 제2저유전막은 기계적 특성이 우수한 CVD 방식으로 형성되었으므로 상기 저유전막의 취약한 기계적 특성으로 인해 유발되는 와이어 본딩(Wire Bonding)시의 페일(Fail)을 방지할 수 있으며, 이를 통해, 후속 공정(Backend Process)을 안정화시킬 수 있다.
또한, 본 발명은 스핀-온 방식을 통해 형성된 제1저유전막 상에 CVD 방식을 통해 형성된 제2저유전막을 형성함으로써, 상기 제2저유전막 상에 형성되는 캡핑막을 종래보다 얇은 두께로 형성할 수 있으며, 이를 통해, 금속배선 간의 기생 캐패시턴스 및 상기 CVD 방식을 통해 형성된 제2저유전막의 두께 증가에 따른 기생 캐패시턴스를 감소시킬 수 있다.In this case, since the second low dielectric film formed on the first low dielectric film is formed by a CVD method having excellent mechanical properties, a fail during wire bonding caused by a weak mechanical property of the low dielectric film is prevented. In this way, the backend process can be stabilized.
In addition, the present invention by forming a second low-k dielectric film formed by the CVD method on the first low-k dielectric film formed by the spin-on method, it is possible to form a capping film formed on the second low-k dielectric film with a thinner thickness than the conventional In this way, the parasitic capacitance between the metal wiring and the parasitic capacitance due to the increase in the thickness of the second low-k dielectric layer formed through the CVD method can be reduced.

자세하게, 도 2a 내지 도 2e는 본 발명의 실시예에 따른 반도체 소자의 제조방법으로서, 이를 설명하면 다음과 같다.In detail, FIGS. 2A to 2E illustrate a method of manufacturing a semiconductor device according to an exemplary embodiment of the present invention.

도 2a를 참조하면, 하부 구조물(도시안됨)이 형성된 반도체 기판(21) 상에 절연막(22)을 증착한 다음, 상기 절연막(22) 상에 금속배선(23)을 형성한다. 다음으로, 상기 제1금속배선(23)이 형성된 기판(21) 전면 상에 선형산화막(24)을 형성한다.Referring to FIG. 2A, an insulating film 22 is deposited on a semiconductor substrate 21 on which a lower structure (not shown) is formed, and then metal wiring 23 is formed on the insulating film 22. Next, a linear oxide film 24 is formed on the entire surface of the substrate 21 on which the first metal wiring 23 is formed.

도 2b를 참조하면, 상기 선형산화막(24)이 형성된 기판(21) 결과물 상에 스핀-온(Spin-On) 방식으로 제1저유전막(25)을 형성한다. 이때, 상기 제1저유전막(25)은 상기 금속배선(23) 상부를 500∼1000Å의 두께만큼 덮도록, 예컨데, 2000∼3000Å 정도의 두께로 형성한다. 또한, 상기 제1저유전막(25)은 SiOCH, 폴리머 및 기공 크기를 이용하여 2.5∼2.9의 절연상수 값을 갖도록 형성한다.Referring to FIG. 2B, the first low dielectric layer 25 is formed on the resultant of the substrate 21 on which the linear oxide layer 24 is formed in a spin-on manner. In this case, the first low-k dielectric layer 25 is formed to have a thickness of about 2000 to 3000 kPa, so as to cover the upper portion of the metal wiring 23 by a thickness of 500 to 1000 kPa. In addition, the first low dielectric layer 25 is formed to have an insulation constant value of 2.5 to 2.9 by using SiOCH, polymer, and pore size.

도 2c를 참조하면, 상기 제1저유전막(25)이 경화되도록 베이크(도시안됨)한 다음, 상기 베이크된 제1저유전막(25)을 열처리한다. 이때, 상기 열처리는 N2 분위기와 400∼600℃ 정도의 온도에서 30∼60분 동안 수행한다.Referring to FIG. 2C, the first low dielectric film 25 is baked (not shown) to cure, and then the baked first low dielectric film 25 is heat treated. At this time, the heat treatment is carried out for 30 to 60 minutes in an N 2 atmosphere and the temperature of about 400 ~ 600 ℃.

여기서, 상기 제1저유전막(25)은 낮은 유전상수 값을 갖도록 형성되므로 기생 캐패시턴스(Parasitic Capacitance)의 형성을 방지할 수 있으며, 이를 통해, 반도체 소자의 동작속도를 개선할 수 있다.Here, since the first low dielectric film 25 is formed to have a low dielectric constant value, it is possible to prevent the formation of parasitic capacitance, thereby improving the operating speed of the semiconductor device.

도 2d를 참조하면, 상기 제1저유전막(25) 상에 CVD(Chemical Vapor Deposition) 방식으로 제2저유전막(26)을 형성한다. 이때, 상기 제2저유전막(26)은 2.7∼3.3 정도의 절연상수 값을 가지고, 3000∼6000Å 정도의 두께로 형성되며, 상기 CVD 공정은 600∼2000W의 소오스 파워를 사용하여 100∼200초 동안 수행한다.Referring to FIG. 2D, a second low dielectric layer 26 is formed on the first low dielectric layer 25 by chemical vapor deposition (CVD). In this case, the second low-k dielectric layer 26 has an insulation constant value of about 2.7 to 3.3 and is formed to a thickness of about 3000 to 6000 mW, and the CVD process is performed for 100 to 200 seconds using a source power of 600 to 2000 W. Perform.

여기서, 상기 제2저유전막(26)은 기계적 특성이 우수한 CVD 방식을 통해 형성되므로 와이어 본딩(Wire Bonding)시 패드 영역이 떨어져 나가는 페일(Fail)을 방지할 수 있으며, 후속 공정(Backend Process)을 안정화시킬 수 있다.Here, since the second low dielectric layer 26 is formed by a CVD method having excellent mechanical properties, the pad region may be prevented from falling off during the wire bonding, and a subsequent process may be performed. It can be stabilized.

도 2e를 참조하면, 상기 제2저유전막(26) 상에 산화막 재질의 캡핑막(27)을 형성한다. 이때, 상기 캡핑막(27)을 종래보다 얇은 두께로 형성하여 금속배선간의 기생 캐패시턴스 및 상기 CVD 방식을 통해 형성된 제2저유전막(26)의 두께 증가에 따른 기생 캐패시턴스를 감소시킨다.Referring to FIG. 2E, a capping film 27 made of an oxide film is formed on the second low dielectric film 26. In this case, the capping layer 27 is formed to a thickness thinner than that of the related art, thereby reducing the parasitic capacitance between the metal wirings and the parasitic capacitance caused by the increase in the thickness of the second low-k dielectric layer 26 formed by the CVD method.

이후, 도시하지는 않았으나, 공지의 후속 공정을 수행하여 본 발명의 반도체 소자를 완성한다.Thereafter, although not shown, the semiconductor device of the present invention is completed by performing a known subsequent process.

여기서, 본 발명은 금속배선(23)의 매립을 위해 저유전막을 형성하는 반도체 소자의 제조방법에 있어서, 상기 금속배선(23)이 형성된 기판(21) 결과물 상에 스핀-온 방식으로 제1저유전막(25)을 형성함으로써 기생 캐패시턴스의 형성을 방지함과 아울러, 상기 제1저유전막(25) 상에 기계적 특성이 우수한 CVD 방식을 통해 제2유전막(26)을 형성함으로써 상기 저유전막의 취약한 기계적 특성으로 인해 유발되는 와이어 본딩(Wire Bonding)시의 페일(Fail)을 방지할 수 있다. 따라서, 후속 공정(Backend Process)을 안정화시킬 수 있다.
이상, 여기에서는 본 발명을 특정 실시예에 관련하여 도시하고 설명하였지만, 본 발명이 그에 한정되는 것은 아니며, 이하의 특허청구의 범위는 본 발명의 정신과 분야를 이탈하지 않는 한도 내에서 본 발명이 다양하게 개조 및 변형될 수 있다는 것을 당업계에서 통상의 지식을 가진 자가 용이하게 알 수 있다.Here, the present invention is a method of manufacturing a semiconductor device to form a low dielectric film for embedding the metal wiring 23, the first low by a spin-on method on the resultant substrate 21 formed with the metal wiring 23 The formation of the dielectric film 25 prevents the formation of parasitic capacitance, and forms the second dielectric film 26 on the first low dielectric film 25 through a CVD method having excellent mechanical properties. Fail during wire bonding caused by the characteristics can be prevented. Thus, the backend process can be stabilized.
As mentioned above, although the present invention has been illustrated and described with reference to specific embodiments, the present invention is not limited thereto, and the following claims are not limited to the scope of the present invention without departing from the spirit and scope of the present invention. It can be easily understood by those skilled in the art that can be modified and modified.

삭제delete

이상에서와 같이, 본 발명은 금속배선의 매립을 위해 저유전막을 형성하는 반도체 소자의 제조방법에 있어서, 상기 저유전막을 스핀-온 방식을 통해 형성된 제1저유전막과 CVD 방식을 통해 형성된 제2유전막의 적층막으로 형성함으로써 상기 저유전막의 취약한 기계적 특성으로 인해 유발되는 와이어 본딩(Wire Bonding)시의 페일(Fail)을 방지할 수 있다.As described above, the present invention is a method of manufacturing a semiconductor device for forming a low dielectric film for embedding a metal wiring, the first low dielectric film formed by the spin-on method and the second low dielectric film formed by a CVD method By forming a laminated film of a dielectric film, it is possible to prevent a fail during wire bonding caused by the weak mechanical properties of the low dielectric film.

따라서, 본 발명은 상기 와이어 본딩시의 페일을 방지함으로써 반도체 소자의 후속 공정(Backend Process)을 안정화시킬 수 있다.Therefore, the present invention can stabilize the backend process of the semiconductor device by preventing the failing during the wire bonding.

Claims (12)

금속배선의 매립을 위해 저유전막을 형성하는 반도체 소자의 제조방법에 있어서,In the method of manufacturing a semiconductor device for forming a low dielectric film for embedding the metal wiring, 상기 저유전막은,The low dielectric film, 스핀-온(Spin-On) 방식으로 제1저유전막을 형성하는 단계; Forming a first low dielectric layer in a spin-on manner; 상기 제1저유전막이 경화되도록 베이크하는 단계; Baking the first low-k dielectric layer to cure; 상기 베이크된 제1저유전막을 열처리하는 단계; Heat-treating the baked first low dielectric film; 상기 열처리된 제1저유전막 상에 CVD(Chemical Vapor Deposition) 방식으로 제2저유전막을 형성하는 단계; 및Forming a second low dielectric film on the heat treated first low dielectric film by chemical vapor deposition (CVD); And 상기 제2저유전막 상에 캡핑막을 형성하는 단계;Forming a capping film on the second low dielectric film; 를 통해 형성하는 것을 특징으로 하는 반도체 소자의 제조방법.Method of manufacturing a semiconductor device, characterized in that formed through. 제 1 항에 있어서,The method of claim 1, 상기 제1저유전막을 형성하는 단계 전, Before forming the first low dielectric film, 상기 금속배선을 포함한 기판 전면 상에 선형산화막을 형성하는 단계;Forming a linear oxide film on the entire surface of the substrate including the metallization; 를 더 포함하는 것을 특징으로 하는 반도체 소자의 제조방법.Method of manufacturing a semiconductor device further comprising. 제 1 항에 있어서,The method of claim 1, 상기 제1저유전막은 SiOCH, 폴리머 및 기공 크기를 이용하여 2.5∼2.9의 절연상수 값을 갖도록 형성하는 것을 특징으로 하는 반도체 소자의 제조방법.The first low dielectric layer is formed using a SiOCH, a polymer and a pore size to have an insulation constant value of 2.5 to 2.9. 제 1 항에 있어서,The method of claim 1, 상기 제1저유전막은 2000∼3000Å의 두께로 형성하는 것을 특징으로 하는 반도체 소자의 제조방법.The first low dielectric film is a semiconductor device manufacturing method, characterized in that formed in a thickness of 2000 ~ 3000Å. 제 1 항에 있어서,The method of claim 1, 상기 열처리는 N2 분위기와 400∼600℃의 온도에서 30∼60분 동안 수행하는 것을 특징으로 하는 반도체 소자의 제조방법.The heat treatment is a method of manufacturing a semiconductor device, characterized in that performed for 30 to 60 minutes at a temperature of 400 to 600 ℃ N 2 atmosphere. 제 1 항에 있어서,The method of claim 1, 상기 제1저유전막은 상기 금속배선의 상부를 500∼1000Å의 두께만큼 덮도록 형성하는 것을 특징으로 하는 반도체 소자의 제조방법.And the first low dielectric film is formed so as to cover the upper portion of the metal wiring by a thickness of 500 to 1000 Å. 제 1 항에 있어서,The method of claim 1, 상기 제2저유전막은 2.7∼3.3의 절연상수 값을 갖도록 형성하는 것을 특징으로 하는 반도체 소자의 제조방법.And the second low dielectric film is formed to have an insulation constant value of 2.7 to 3.3. 제 1 항에 있어서,The method of claim 1, 상기 제2저유전막은 3000∼6000Å의 두께로 형성하는 것을 특징으로 하는 반도체 소자의 제조방법.The second low dielectric film is a semiconductor device manufacturing method, characterized in that formed to a thickness of 3000 ~ 6000Å. 제 1 항에 있어서,The method of claim 1, 상기 CVD는 600∼2000W의 소오스 파워를 사용하여 100∼200초 동안 수행하는 것을 특징으로 하는 반도체 소자의 제조방법.Wherein the CVD is performed for 100 to 200 seconds using a source power of 600 to 2000 W. 제 1 항에 있어서,The method of claim 1, 상기 캡핑막은 산화막으로 형성하는 것을 특징으로 하는 반도체 소자의 제조방법.The capping film is a manufacturing method of a semiconductor device, characterized in that formed by an oxide film. 삭제delete 삭제delete
KR1020060059826A 2006-06-29 2006-06-29 Method of manufacturing semiconductor device KR100743657B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020060059826A KR100743657B1 (en) 2006-06-29 2006-06-29 Method of manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020060059826A KR100743657B1 (en) 2006-06-29 2006-06-29 Method of manufacturing semiconductor device

Publications (1)

Publication Number Publication Date
KR100743657B1 true KR100743657B1 (en) 2007-07-30

Family

ID=38499799

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020060059826A KR100743657B1 (en) 2006-06-29 2006-06-29 Method of manufacturing semiconductor device

Country Status (1)

Country Link
KR (1) KR100743657B1 (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19990057064A (en) * 1997-12-29 1999-07-15 구본준 Wiring Formation Method of Semiconductor Device
KR20050009909A (en) * 2003-07-18 2005-01-26 주식회사 하이닉스반도체 Structure of inter-dielectric layer in semiconductor device and method of forming the same

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19990057064A (en) * 1997-12-29 1999-07-15 구본준 Wiring Formation Method of Semiconductor Device
KR20050009909A (en) * 2003-07-18 2005-01-26 주식회사 하이닉스반도체 Structure of inter-dielectric layer in semiconductor device and method of forming the same

Similar Documents

Publication Publication Date Title
US6057226A (en) Air gap based low dielectric constant interconnect structure and method of making same
KR101674057B1 (en) Semiconductor chip structure having a complex reinforced insulator and method of fabricating the same
JPH1074755A (en) Microelectronic structure and its forming method
US20090115019A1 (en) Semiconductor device having air gap and method for manufacturing the same
KR100743657B1 (en) Method of manufacturing semiconductor device
JP2005217142A (en) Process for fabricating semiconductor device
KR100973277B1 (en) Metal wiring of semiconductor device and method for forming the same
JP2003218114A (en) Semiconductor device and its manufacturing method
KR100945500B1 (en) Method of manufacturing semiconductor device
KR100565758B1 (en) Method for Forming Insulate Layer of Semi-conductor Device
KR100924542B1 (en) Pad of semiconductor device and manufacturing method of the same
KR100914976B1 (en) Method of manufacturing semiconductor device
KR101204742B1 (en) Method for forming semiconductor device
TWI414020B (en) Semiconductor device including barrier metal and coating film and method for manufacturing same
KR100546940B1 (en) Method of forming copper wiring in semiconductor device
KR0165758B1 (en) Manufacturing method of semiconductor device`
KR20100036008A (en) Method for forming metal wiring of semiconductor device
KR100866135B1 (en) Method of manufacturing semiconductor device
KR20090011950A (en) Method for manufacturing semiconductor device
KR100210898B1 (en) Process for forming metal interconnection in semiconductor device
KR100680500B1 (en) Method of forming a dielectric layer in a semiconductor device
KR20070048820A (en) Wiring structure in a semiconductor device and method of manufacturing the same
KR101029106B1 (en) Metal wiring of semiconductor device and method for forming the same
KR100652316B1 (en) Method for manufacturing inter metal dielectric layer of semiconductor device
KR101029105B1 (en) Metal wiring of semiconductor device and method for forming the same

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
G170 Publication of correction
FPAY Annual fee payment

Payment date: 20100624

Year of fee payment: 4

LAPS Lapse due to unpaid annual fee