KR100743075B1 - Plasma display panel and diving apparatus and method thereof - Google Patents

Abstract

A plasma display panel and an apparatus and a method for driving the same are provided to stabilize a discharge voltage by maximumly decreasing parasitic impendence and securing a passage of high current. A first scan bus electrode(Y1) is formed on a scan electrode to supply a first voltage waveform for unifying an initial stage of plural discharge cells, and to supply a second voltage waveform for selecting a discharge cell which maintains sustain discharge. A second scan bus electrode(Y2) is formed on the scan electrode and is arranged in parallel with the first scan bus electrode to supply a third voltage waveform for maintaining the sustain discharge of the selected discharge cell.

Description

Plasma Display Panel and Driving Device and Driving Method thereof {Plasma Display Panel and Diving Apparatus and Method}

1 is an exploded perspective view showing the structure of a conventional three-electrode AC surface discharge type plasma display panel.

FIG. 2 is a diagram illustrating an overall configuration of an electrode line and a PDP apparatus of the PDP shown in FIG. 1.

3 is a diagram illustrating an example of a driving waveform according to the PDP driving method illustrated in FIG. 2.

FIG. 4 shows an example of a scan electrode driving apparatus for supplying a scan waveform applied to the scan electrode Y among the drive waveforms shown in FIG. 3.

5 is an exploded perspective view illustrating a structure of a plasma display panel according to an exemplary embodiment of the present invention.

FIG. 6 is a diagram illustrating an overall configuration of an electrode line and a PDP apparatus of the PDP shown in FIG. 5.

7 shows a first scan electrode drive device 22A according to a preferred embodiment of the present invention.

FIG. 8 is a diagram illustrating variability of a reset waveform by the first scan electrode driving apparatus of FIG. 7.

FIG. 9 shows an example of an integrated device incorporating the second scan electrode drive device 22B and the sustain electrode drive device 23 according to one preferred embodiment of the present invention.

FIG. 10 is a waveform diagram illustrating voltages applied to the second scan bus electrode, the sustain electrode, and the panel capacitor by the integrated device shown in FIG. 9.

<Brief description of the symbols in the drawings>

20: discharge cell `21: plasma display panel

22, 22A, 22B: scan electrode drive device 23: sustain electrode drive device

44, 74: scan drive IC Y: scan electrode

3, Y1, Y2: bus electrode Z: sustain electrode

X: address electrode 70: automatic voltage regulator

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plasma display panel, and a driving device and a driving method thereof. In particular, the sustain voltage waveform generation function supplied to the scan electrode is separated from the sustain voltage waveform generation function supplied to the scan electrode and supplied to the sustain electrode. The present invention relates to a plasma display panel, and a driving device and a driving method thereof for stabilizing a discharge by integrating therewith.

Plasma Display Panel (hereinafter, also referred to as "PDP") is a display device using a phenomenon in which visible light is generated when ultraviolet rays generated by gas discharge excite phosphors. Compared to the above, it is thin and light, and it is possible to realize a high definition large screen, etc. In general, a PDP is composed of a plurality of discharge cells arranged in a matrix, and one discharge cell is disposed on one subpixel of the screen. Corresponding.

1 is an exploded perspective view showing the structure of a conventional three-electrode AC surface discharge type plasma display panel. Referring to FIG. 1, each discharge cell includes a scan electrode Y and a sustain electrode Z formed on the upper substrate 1, and an address electrode X formed on the lower substrate 10. The scan electrode (Y) and the sustain electrode (Z) are usually made of indium tin oxide (hereinafter referred to as 'ITO'), and they are placed on them in order to reduce voltage drop due to their high resistance characteristics. Bus electrodes 3 made of at least one of metals such as Ag, Cu, and Cr are formed, respectively.

The upper dielectric layer 4 and the passivation layer 5 are stacked on the upper substrate 1 having the scan electrode Y and the sustain electrode Z side by side. The protective film 5 is usually made of magnesium oxide (MgO) in order to prevent damage to the upper dielectric layer 4 by sputtering generated during plasma discharge and to improve emission efficiency of secondary electrons.

The lower dielectric layer 8 and the partition wall 6 are formed on the lower substrate 9 on which the address electrode X is formed, and the phosphor 7 is coated on the surfaces of the lower dielectric layer 8 and the partition wall 6. The address electrode X is formed in a direction perpendicular to the scan electrode Y and the sustain electrode Z, and the partition wall 6 is formed in a direction parallel to the address electrode X to generate ultraviolet rays generated by discharge and Prevent visible light from leaking to adjacent discharge cells. The phosphor 7 is excited by ultraviolet rays generated during plasma discharge to generate visible light of any one of red (R), green (G), and blue (B). In the discharge space provided by the upper substrate 1, the lower substrate 9, and the partition wall 6, Ne + Xe, a penning gas, and the like for gas discharge are sealed.

In the PDP having the above-described structure, the discharge cell is selected by the counter discharge between the address electrode X and the scan electrode Y, and then the discharge of the selected discharge cell is maintained by the surface discharge between the scan electrode Y and the sustain electrode Z. To be. In such a discharge cell, visible light is emitted to the outside of the cell by emitting the phosphor 7 by ultraviolet rays generated during the sustain discharge. As a result, the discharge cells adjust the period during which the discharge is maintained to implement gray scale, and the PDP in which the discharge cells are arranged in a matrix form can display an image.

FIG. 2 is a diagram illustrating an overall configuration of an electrode line and a PDP apparatus of the PDP shown in FIG. 1. Referring to FIG. 2, in the conventional three-electrode AC surface discharge PDP driving apparatus, m × n discharge cells 20 may include scan electrode lines Y1 to Ym, sustain electrode lines Z1 to Zm, and address electrodes. A PDP 21 arranged in a matrix form to be connected to the lines X1 to Xn, a scan driving device 22 for driving the scan electrode lines Y1 to Ym, and sustain electrode lines Z1 to Zm. ), A sustain drive device 23 for driving), an address drive device 24 for driving address electrode lines X1 to Xn, display data D from the outside, a horizontal synchronization signal H, And a control circuit section 25 for supplying control signals to the respective driving devices based on the vertical synchronizing signal V, the clock signal, and the like.

The scan drive device 22 includes a reset voltage waveform for uniformizing the initial state of all discharge cells in the scan electrode lines Y1 to Ym, a scan (address) pulse waveform for selecting a discharge cell, and the number of discharges. As a result, a sustain pulse waveform that implements gradation is sequentially supplied to allow the discharge cells 20 to be sequentially scanned in line units and to sustain discharge in each of the m × n discharge cells 20. The sustain driving device 23 supplies sustain pulses alternately with the sustain pulses supplied to the scan electrode lines Y1 to Ym to all of the sustain electrode lines Z1 to Zm to cause sustain discharge for the selected cell. The address driver 24 serves to select a cell to be discharged by supplying a scan pulse synchronized with a scan pulse supplied to the scan electrode lines Y1 to Ym.

3 is a diagram illustrating an example of a driving waveform according to the PDP driving method illustrated in FIG. 2. Referring to FIG. 3, in the setup period SU of the reset period, a rising ramp waveform Ramp-up rising from the positive voltage to the setup voltage Vsetup is simultaneously supplied to all the scan electrodes Y. At the same time, the ground voltage GND is supplied to the sustain electrode Z and the address electrode X. Due to the rising ramp waveform Ramp-up, a setup discharge occurs in a weak discharge between the scan electrode Y, the sustain electrode Z, and the address electrode X in the discharge cells of the full screen. As a result, positive wall charges are accumulated on the address electrode X and the sustain electrode Z, and negative wall charges are accumulated on the scan electrode Y. In the set-down period SD of the reset period, a falling ramp waveform Ramp-down that falls from the set-up voltage Vsetup to a predetermined positive voltage and then falls with a slope from the positive voltage to the set-down voltage (-Vry) It is supplied to the scan electrodes (Y). While the falling ramp waveform Ramp-down is supplied, the positive bias voltage Vdc is supplied to the sustain electrode Z, and the ground voltage GND is supplied to the address electrode X. Due to the ramp ramp down, a setdown discharge occurs between the scan electrode Y, the sustain electrode Z, and the address electrode X with weak discharge, and the wall charges formed during the setup discharge by the setdown discharge. Excessive wall charges unnecessary for the address discharge are erased.

Looking at the wall charge change in the reset period, there is almost no wall charge change on the address electrode (X), and the negative wall charges on the scan electrode (Y) that were formed during the setup discharge are partially reduced by the setdown discharge. The negative charge is accumulated on the sustain electrode Z by this decrease.

In the address period, the scan reference voltage Vsc is supplied and the negative scan pulse voltage -Vy is sequentially supplied to the scan electrodes Y, and the address electrode is synchronized with the application of the scan pulse voltage -Vy. A positive data pulse voltage Va is supplied to (X). As the voltage difference between the scan pulse voltage -Vy and the data pulse voltage Va and the wall voltage generated in the reset period are added, an address discharge is generated in the cell to which the data pulse voltage Va is applied. In the cells selected by the address discharge, wall charges are formed such that a discharge can occur when the sustain pulse voltage Vs is supplied in the sustain discharge period. The positive bias voltage Vdc is continuously supplied to the sustain electrode Z during the address period.

In the sustain discharge period, the sustain pulse voltage Vs is alternately supplied to the scan electrode 2Y and the sustain electrode 2Z. Each time the sustain pulse voltage Vs is applied, the cells selected by the address discharge are sustain discharge, i.e., between the scan electrode Y and the sustain electrode Z while the wall voltage and the sustain pulse voltage Vs in the cell are added. Display discharge is generated.

After the sustain discharge is completed, the erasing period may follow. In the erasing period, an erase mamp waveform Ramp-er having a small pulse width and a low voltage level is supplied to, for example, the sustain electrode Z to erase wall charge remaining in the cells of the full screen.

FIG. 4 shows an example of a scan electrode driving apparatus for supplying a scan waveform applied to the scan electrode Y among the drive waveforms shown in FIG. 3. Referring to FIG. 4, a scan electrode driving apparatus for supplying scan waveforms to a PDP panel according to the related art includes an energy recovery circuit 40, a sustain pulse supply unit 41, a scan reference voltage supply unit 42, and a scan pulse voltage. And a supply unit 45, a scan driver IC 46, a setup voltage supply unit 42 and a set down voltage supply unit 43.

The energy recovery circuit 40 is charged with the energy supplied from the panel, and the external capacitor Cs for supplying the charged voltage to the panel, and the first and second for forming the charge and discharge paths of the external capacitor Cs. The inductor Ls constituting the series LC circuit with the switches S1 and S2 and the first and second diodes D1 and D2 for blocking the reverse current and the panel capacitor Cp which is the capacitance in the discharge cell. It is composed. Note that the term switch is used herein to briefly describe a transistor including a body diode, except where otherwise indicated.

The sustain pulse supply unit 41 supplies third and fourth switches S3 and S4 for supplying the sustain pulse voltage Vs and the ground voltage GND to the scan electrode Y in accordance with a control signal supplied during the sustain discharge period. It is made, including.

The scan reference voltage supply part 42 includes a third diode D3, a sixth switch S6, and a seventh switch connected in series between the voltage source supplying the scan reference voltage Vsc and the scan pulse voltage supply part 43. S7) and a first capacitor C1 connected in parallel with the sixth and seventh switches S6 and S7 connected in series. The sixth switch S6 switches in response to the control signal supplied in the address period, thereby supplying the scan reference voltage Vsc to the scan driving IC 44. At this time, the first capacitor C1 connected to the voltage source supplying the scan reference voltage Vsc through the third diode D3 and one side thereof and the other end connected to the scan pulse voltage supply part 43 is the scan reference voltage Vsc. ) To create a different voltage level while keeping the charged voltage at the floating level. The seventh switch S7 switches the scan reference voltage Vsc supplied to the scan driver IC 44 in response to the control signal.

The scan pulse voltage supply unit 43 includes a tenth switch S10 connected in series between the scan driving IC 44 and a voltage source for supplying the scan pulse voltage (−Vy). The tenth switch S10 switches in response to a control signal supplied in an address period, thereby providing a scan pulse voltage (−Vy) to the panel.

The scan drive IC 44 has eighth and ninth switches S8 and S9 connected in a push-pull form. The eighth and ninth switches S8 and S9 are provided from the sustain pulse supply part 41, the scan reference voltage supply part 42, the scan pulse voltage supply part 43, and the setup and setdown voltage supply parts 45 and 46 which will be described later. The voltage signal of is selectively supplied to the scan electrode 2Y of the panel.

The setup voltage supply part 45 includes a fourth diode D4 and an eleventh switch S11 connected in series with a voltage source for supplying a setup voltage Vsetup to supply a voltage of a rising ramp waveform Ramp-up. Is done. The slope of the rising ramp waveform Ramp-up is adjusted by adjusting the resistance value of the control terminal of the eleventh switch S11, that is, the variable resistor R1 connected to the gate terminal. The fourth diode D4 blocks the reverse current flowing toward the voltage source supplying the setup voltage Vsetup.

The fifth switch S5 connected between the set-up voltage supply part 45 and the sustain pulse supply part 41 is turned on during the sustain discharge period so as to sustain pulses from the sustain pulse supply part 41 to the scan driving IC 44. It forms the path of supply.

The setdown voltage supply unit 46 includes a twelfth switch S12 connected in series with a voltage source supplying a setdown voltage (-Vry) to supply a voltage of a ramp down ramp waveform shown in FIG. 3. It is done by The slope of the falling ramp waveform Ramp-down is adjusted by adjusting the resistance value of the variable resistor R2 connected to the gate terminal of the twelfth switch S12. A thirteenth switch S13 connected between the set-up voltage supply part 45 and the set-down voltage supply part 46 has a rising ramp waveform Ramp-up and a falling ramp waveform Ramp-down at the scan electrode 2Y. It serves to switch the supply. Although the setdown voltage (--Vry) and the scan pulse voltage (-Vy) have the same value in the drawing, the setdown voltage (-Vry) and the scan pulse voltage (-Vy) have different values. In this case, a voltage source for supplying the set-down voltage (-Vry) and a voltage source for supplying the scan pulse voltage (-Vy) may be provided separately. Like the fifth switch S5, the thirteenth switch S13 is a high breakdown voltage switch capable of passing a high voltage, and several FETs are used together with a body diode.

Although the detailed illustration is abbreviate | omitted, the sustain electrode drive apparatus 23 has the energy recovery circuit and the sustain pulse voltage which have the same structure as the structure of the energy recovery circuit 40 and the sustain pulse voltage supply part 41 of the said scan electrode drive apparatus. The sustain pulse voltage Vs is supplied to the sustain electrode Z, including the supply unit. In addition, the sustain electrode driver 23 may include an erase voltage supply unit having a configuration similar to that of the setup voltage supply unit 45 of the scan electrode driver in order to supply an erase pulse to the sustain electrode Z when necessary. .

However, according to the PDP driving apparatus according to the related art as described above, in particular, in the case of a scan driving apparatus, in order to supply a voltage of a scan waveform to one scan electrode Y, a setup voltage Vsetup and a setdown voltage (-Vry) are provided. Since it is configured to supply various kinds of voltages such as scan pulse voltage (-Vy), scan reference voltage (Vsc) and sustain pulse voltage (Vs), the configuration of the scan electrode driving device is complicated and the PCB configuration is implemented. There is a problem that the parasitic impedance, which hinders the stabilization of the circuit, increases due to the degree of freedom of the. In addition, the interference and noise characteristics are not good with the increase of the impedance, there is a problem that inhibits the voltage and discharge stabilization. In particular, when the sustain pulse is supplied, a path through which a large current passes must be sufficiently secured to reduce ringing due to impedance, and according to the aforementioned scan electrode driving apparatus, the fifth switch S5 and the thirteenth switch As shown in S13, there is a problem in that a switch having a high breakdown voltage cannot be used.

The present invention has been made to solve the above-described problems of the prior art, by separating the function for sustain discharge to drive the scan electrode can simplify the configuration of the overall drive device and increase the PCB freedom, circuit An object of the present invention is to provide a plasma display panel and a driving device and method thereof capable of stabilizing a discharge voltage by securing a path through which a large current passes while reducing parasitic impedance that hinders stabilization of the battery.

In addition, an object of the present invention is to provide an apparatus for driving a plasma display panel which can reduce the number of various components by integrating a device for sustain discharge.

In order to achieve the above object, a plasma display panel according to a first aspect of the present invention includes a plurality of discharge cells arranged in a matrix form, and is made to uniformize initial states of all of the plurality of discharge cells. A first scan bus electrode formed on the scan electrode to supply a first voltage waveform and to supply a second voltage waveform for selecting a discharge cell to sustain the sustain discharge among the plurality of discharge cells; And a second scan bus electrode formed on the scan electrode in parallel with the first scan bus electrode to supply a third voltage waveform for maintaining a sustain discharge of the selected discharge cell.

In addition, in order to achieve the above object, the apparatus for driving a plasma display panel according to the second aspect of the present invention includes the first and the first and second scan bus electrodes connected to the scan electrode to drive the plasma display panel. A first scan electrode drive device for supplying a second voltage waveform; And a second scan electrode driving device for supplying the third voltage waveform to the scan electrode through the second scan bus electrode.

Herein, a part of the first and second voltage waveforms may include an operational amplifier in which an inverting input terminal is connected to one terminal of a variable resistor and a first capacitor, a non-inverting input terminal is grounded, and the other terminal of the first capacitor is connected to an output terminal. The integrator comprising, and the other terminal of the resistor is preferably generated using an automatic voltage regulator which is grounded via an automatic voltage regulator and supplied via a scan driving IC.

The other part of the first and second voltage waveforms may be selectively turned on by connecting the first and second switches connected between one terminal of the second and third capacitors and the automatic voltage regulator, respectively. It is preferable that a voltage precharged to the second or third capacitor is supplied via the scan driving IC.

In addition, in order to achieve the above object, the plasma display panel driving apparatus according to the third aspect of the present invention is configured to drive the plasma display panel to the scan electrode through the first scan bus electrode. A first scan electrode driving device for supplying first and second voltage waveforms; And a second scan electrode driving device for supplying the third voltage waveform to the scan electrode through the second scan bus electrode. And a sustain electrode driving device for supplying a fourth voltage waveform for maintaining the sustain discharge of the selected discharge cell to the sustain electrode through the sustain bus electrode.

Here, the third and fourth voltage waveforms are preferably supplied using the second scan electrode driving device and the sustain electrode driving device each including an energy recovery circuit.

Further, the third and fourth voltage waveforms are preferably applied between the second scan bus electrode and the sustain electrode as one integrated voltage waveform using an integrated device including one energy recovery circuit.

Wherein the integrated device comprises: an energy recovery capacitor and an energy recovery inductor (Ls) connected in series; A first bidirectional switch connected between one terminal of the energy recovery inductor and the second scan bus electrode; A second bidirectional switch connected between one terminal of the energy recovery inductor and the sustain electrode; A twelfth switch and a fourteenth switch connected to the second scan bus electrode and used to supply a sustain pulse voltage or a base voltage to the second scan bus electrode; And an eleventh switch and a thirteenth switch connected to the sustain electrode and used to supply a sustain pulse voltage or a base voltage to the sustain electrode.

In addition, in order to achieve the above object, a method of driving a plasma display panel according to a fourth aspect of the present invention comprises: discharging a plurality of discharge cells through a first scan bus electrode formed on a scan electrode to be formed in the discharge cell. Supplying a first voltage waveform to cancel wall charge; Supplying a second voltage waveform for selecting a discharge cell to sustain sustain discharge among the plurality of discharge cells through the first scan bus electrode; And supplying a third voltage waveform to maintain the sustain discharge to the selected discharge cell through a second scan bus electrode formed on the scan electrode in parallel with the first scan bus electrode.

Wherein the other part of the first and second voltage waveforms is selectively turned on by the automatic voltage regulator by selectively turning on the first and second switches connected between one terminal of the second and third capacitors and the automatic voltage regulator, respectively. It is preferable that a voltage precharged to the second or third capacitor is supplied via the scan driving IC.

The driving method may further include supplying a sustain voltage to the sustain electrode through a sustain bus electrode, and supplying a fourth voltage waveform to sustain the sustain discharge to the selected discharge cell. The voltage waveform is preferably applied between the second scan bus electrode and the sustain electrode as one integrated voltage waveform.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to FIGS. 5 to 9.

FIG. 5 is an exploded perspective view illustrating a structure of a plasma display panel according to an exemplary embodiment of the present invention, and FIG. 6 is a diagram illustrating an overall configuration of an electrode line and a PDP apparatus of the PDP shown in FIG. 5. In FIG. 5 and FIG. 6, components that are responsible for the same function are denoted by the same reference numerals of FIGS. 1 and 2, and a detailed description thereof is omitted for convenience.

5 and 6 differs from the conventional PDP and driving apparatus shown in FIGS. 1 and 2 on the scan electrode Y formed on the upper substrate 1 of the PDP. The first scan bus electrode Y1 used to apply the voltage of the reset waveform and the address waveform to the panel, i.e., the second scan bus electrode Y2 used to apply the voltage of the sustain pulse waveform to the panel. ) Is formed separately, and the first scan electrode driver 22A and the second scan bus electrode lines 22 for supplying a predetermined voltage waveform to the first scan bus electrode lines Y1 ₁ to Y1 _m . The second scan electrode drive device 22B for supplying a predetermined voltage waveform to Y2 ₁ to Y2 _m ) is separately provided. That is, according to the present exemplary embodiment, the voltages of the rising ramp waveform Ramp-up and the falling ramp waveform Ramp-down during the reset period and the scan pulse waveform of the address period among the scan driving waveforms shown as an example in FIG. The first scan bus electrode Y1 is supplied through the first scan electrode driver 22A, and the voltage of the sustain pulse waveform is supplied to the second scan bus electrode Y2 through the second scan electrode driver 22B. .

As described above, by separately separating the bus electrode and the driving device for applying the voltage of the sustain pulse waveform to the scan electrode Y from the bus electrode and the driving device for applying the voltage of the reset waveform and the voltage of the address pulse waveform, When implementing these two functions in driving a PDP according to the prior art, it is not necessary to include a high capacity switch (s) to block other functions, so that the scan electrode driving device can be configured more simply. The degree of freedom of the circuit is improved, and the parasitic impedance that reduces the stabilization of the circuit is reduced. Accordingly, the interference and noise characteristics are further improved along with the reduction of the impedance to stabilize the voltage and the discharge, and also reduce the ringing caused by the impedance.

FIG. 7 illustrates a first scan electrode driving device 22A according to a preferred embodiment of the present invention. However, it will be apparent to those skilled in the art that the present invention can be configured to include only that portion of the conventional scan electrode drive shown in FIG.

Referring to FIG. 7, the first scan electrode driving apparatus 22A of the present invention includes a setup voltage Vsetup, a setdown voltage (-Vry), and a scan reference voltage, which are used to supply voltages of the reset waveform and the scan pulse waveform. Vsc) and the first to fourth switches S71, S72, S73, and S74, the second and third capacitors C71 and C72, and the automatic voltage to perform a function of supplying the scan pulse voltage (-Vy) to the panel. A controlled voltage generator 70, an integrator consisting of a variable resistor R70, a first capacitor C70 and an operational amplifier Amp, and fifth and sixth switches S75 and S76 connected in a push-pull form. It comprises a scan drive IC (74) consisting of a).

The operational amplifier Amp has one terminal of the variable resistor R70 and the first capacitor C70 connected to the inverting input terminal thereof, the non-inverting input terminal thereof is grounded, and the other end of the first capacitor C70 connected to the output terminal thereof. The terminals are connected to form an integrator. In addition, the other terminal of the resistor is grounded via an automatic voltage regulator 70, is connected to a sixth switch (S76) of the scan driving IC 74 via a fourth switch (S74) and the output terminal of the operational amplifier is scanned It is configured to be connected to the sixth switch S76 of the driving IC 74. The connection point of the fourth switch S74 and the sixth switch 76 of the scan driver IC 74 is connected to the third capacitor C73 via the second switch S72 and via the third switch S73. Grounded. In addition, a connection point of the fourth switch S74 and the sixth switch S76 of the scan driver IC 74 is connected to the second capacitor C72 through the first switch S71 and is connected to the scan driver IC 74. It is connected to the fifth switch S75.

Referring to the operation of the first scan electrode driver shown in FIG. 7 in detail, first, when the voltage of the sustain pulse waveform is applied through the second scan bus electrode and the sustain bus electrode in the sustain discharge period, the first scan electrode driver Prepares a voltage source for supplying the reset of the next subfield and the voltage of the address pulse waveform. That is, in the sustain discharge period, the output voltage of the automatic voltage regulator 70 is adjusted at an appropriate timing in accordance with a predetermined control signal, and the fourth switch S74 is turned on and the first switch S71 or the second switch ( S72 is turned on to store the scan reference voltage Vsc and the sustain pulse voltage Vs in the second capacitor C71 and the third capacitor C72, respectively.

First, the third switch S73 and the sixth switch S76 are turned on during the initial period of the reset period to supply the base voltage GND to the panel. Thereafter, during the setup period, the third switch S73 is turned off and the second switch S72 is turned on to increase the sustain pulse voltage Vs stored in the third capacitor C72 through the sixth switch S76. After supplying the panel as an initial value of the ramp waveform, the integrator including the variable resistor R70 and the first capacitor C70 by turning off the second switch S72 and adjusting the output voltage of the automatic voltage regulator 70. The voltage of the rising ramp waveform, which rises from the sustain pulse voltage (Vs) to the setup voltage (Vsetup), is supplied to the panel.

Subsequently, in the set-down period, the second switch S72 is turned on in the same manner as in the setup period by the control signal of the control circuit, and the sustain pulse voltage Vs is supplied to the panel as an initial value of the falling ramp waveform. By turning off (S72) and adjusting the output voltage of the automatic voltage regulator 70, the output voltage of the integrator including the variable resistor (R70) and the first capacitor (C70) is set from the sustain pulse voltage (Vs) to the setdown voltage (-). The voltage of the falling ramp waveform falling to Vry) is supplied to the panel. The set-up voltage (Vsetup) and the set-down voltage (-Vry) can be controlled by adjusting the output voltage and time of the automatic voltage regulator 70 according to the control signal, in this case the lamp by adjusting the resistance of the variable resistor (R70) The slopes of the waveforms can be adjusted individually.

In the address period, the scan reference voltage Vsc previously charged in the second capacitor C71 is scanned by turning on the sixth switch S76 and turning on the first switch S71 and the fifth switch S5. It is supplied to the panel via the fifth switch S75 of the driving IC 74, during which the output voltage of the automatic voltage regulator 70 is adjusted to be the scan pulse voltage (-Vy). Accordingly, when the first switch S71 is turned off in response to the control signal and the fourth switch S74 and the sixth switch S76 are turned on, the scan pulse voltage −Vy may be supplied to the panel.

According to the first scan driving device of the preferred embodiment of the present invention shown in FIG. 7, the slope of the rising ramp waveform, the slope of the falling ramp waveform, and the setup voltage Vsetup and the setdown voltage (−) as shown in FIG. 8. Since the magnitudes of Vry, the scan reference voltage Vsc and the scan pulse voltage (-Vy) can be controlled in real time according to the adjustment values of the automatic voltage regulator 70 and the variable resistor R70, as an example in FIG. In addition to the voltage waveforms shown, various other types of waveforms can be supplied to the scan electrodes.

 Therefore, unlike the prior art in which a fixed voltage is supplied to several DC-DC converters, according to the present invention, a voltage source is implemented using a variable voltage generator and power capacitors, and the voltages of the rising ramp waveform and the falling ramp waveform are automatically adjusted. By implementing to occur with one ramp waveform generator consisting of a regulator and an integrator, the scan drive device can be much simplified than the conventional scan drive device. In addition, in the related art, it was difficult to change the setup and setdown voltages for each subfield in addition to the switching timing. However, according to the scan driving apparatus of the present invention, as shown in FIG. This enables precise reset and addressing, which contributes to improved image quality and reliability.

Meanwhile, the second scan electrode driver 22B according to an exemplary embodiment of the present invention may be installed separately from the sustain electrode driver 23 to include only a corresponding portion of the conventional scan electrode driver. As shown in Fig. 2, an integrated device incorporating the second scan electrode drive device 22B and the sustain electrode drive device 23 of the present invention may be provided.

9, the integrated device according to an embodiment of the present invention is an energy recovery capacitor (Cs) and inductor (Ls), two BiDirectional Switch (hereinafter also referred to as "BDS") (BDS1, BDS2) And eleventh to fourteenth switches S91 to S94 for applying a voltage of the sustain pulse waveform. In the figure, the bidirectional switch is illustrated in which two transistors are connected in series via a resistor. However, the bidirectional switch is not limited thereto and may have any configuration. In this figure, the panel capacitor Cp may include the second scan electrode Y2. And the sum of the capacitance components present in the discharge space and the substrate between the sustain electrode and the sustain electrode Z equivalently.

In an integrated device according to an embodiment of the present invention, the energy recovery capacitor Cs and the energy recovery inductor Ls are connected in series, and the second BDS BDS2 is connected in parallel with the inductor Ls. The connection point of the second BDS (BDS2) is connected to the second scan bus electrode Y2 via the first BDS (BDS1) as shown in FIG. 9, and the connection point of the capacitor Cs and the second BDS (BDS2). Is configured to be connected to the sustain electrode (Z). In addition, the voltage source for supplying the sustain pulse voltage Vs is connected to the second scan bus electrode Y2 and the sustain electrode Z, respectively, through the twelfth switch S92 and the eleventh switch S91, and the second scan. The base voltage is supplied to the bus electrode Y2 and the sustain electrode Z through the fourteenth switch S94 and the thirteenth switch S13, respectively.

Referring to the operation of the integrated device described above, first, when the BDS2 is turned off and the BDS1 is turned on in the sustain discharge period, when the S92 and S93 are turned on at the same time as the second scan bus electrode ( The sustain pulse voltage Vs is applied to Y2) and the ground voltage is applied to the sustain electrode Z, so that the voltage Vcp across the panel capacitor Cp becomes Vs.

Subsequently, when BDS1 is turned off and BDS2 is turned on, when S92 and S93 are turned off and S91 and S94 are turned on, a ground voltage is applied to the second scan bus electrode Y2 and the sustain electrode Z is sustained. The pulse voltage Vs is applied so that the voltage Vcp across the panel capacitor Cp becomes -Vs. FIG. 10 shows voltage waveforms applied to the second scan bus electrode Y2 and the sustain electrode Z by the integrated device described above, and voltage waveforms applied to the panel capacitor Cp as one voltage waveform. It is a wave form figure.

According to the integrated device according to the preferred embodiment of the present invention as described above, the energy recovery inductor and the capacitor, which are included in the scan electrode driving device and the sustain electrode driving device, are reduced by one. Of course, in the case of implementing the aforementioned integrated device, when the risk of impedance increase occurs, the second scan electrode driving device and the sustain driving device may be separately implemented.

Although preferred embodiments of the present invention have been described above, the plasma display panel, the driving device and the driving method thereof according to the present invention can be modified and applied in various forms within the scope of the technical idea of the present invention. For example, although the embodiment shown in FIG. 7 uses two capacitors to provide the scan reference voltage and the initial voltage value of the reset period, this is to implement an example of the waveform shown in FIG. The first scan electrode driving apparatus of the present invention may have various circuit configurations according to the waveform applied to the scan electrode, the number of capacitors, and the type of voltage charged thereto. After all, the embodiments and drawings are merely for the purpose of describing the details of the invention, and are not intended to limit the scope of the technical idea of the invention, the scope of the present invention is not limited to the claims to be described later and It should be judged to include an even range.

According to the present invention, by separately configuring the device for sustain discharge to configure the scan electrode driving device, the overall configuration is simplified and the PCB freedom is increased. In addition, the parasitic impedance that inhibits the stabilization of the circuit can be minimized, and a path through which a large current passes can be secured to stabilize the discharge voltage.

In addition, according to the present invention, the voltage of the reset waveform and the voltage of the address waveform can be changed for each subfill, so that when tuning the waveform with timing control as in the prior art, a more precise reset voltage waveform according to the phenomenon There is an effect that can form.

In addition, according to the present invention, it is possible to reduce the number of DC-DC converter and various components by integrating the device for sustain discharge.

Claims (14)

In the plasma display panel comprising a plurality of discharge cells arranged in a matrix form, A first voltage waveform for supplying a uniform initial state of all of the plurality of discharge cells and a second voltage waveform for selecting a discharge cell for maintaining a sustain discharge among the plurality of discharge cells; A first scan bus electrode formed; And And a second scan bus electrode formed on the scan electrode in parallel with the first scan bus electrode to supply a third voltage waveform for maintaining a sustain discharge of the selected discharge cell. A first voltage waveform for supplying a uniform initial state of all of the plurality of discharge cells and a second voltage waveform for selecting a discharge cell for maintaining a sustain discharge among the plurality of discharge cells. A first scan bus electrode; And a second scan bus electrode formed on the scan electrode in parallel with the first scan bus electrode to supply a third voltage waveform for maintaining a sustain discharge of the selected discharge cell. In the apparatus, A first scan electrode driving device for supplying the first and second voltage waveforms to the scan electrode through the first scan bus electrode; And And a second scan electrode driving device for supplying the third voltage waveform to the scan electrode through the second scan bus electrode. The method of claim 2, Part of the first and second voltage waveforms includes an operational amplifier having an inverting input terminal connected to one terminal of the variable resistor and the first capacitor, a non-inverting input terminal grounded, and the other terminal of the first capacitor connected to the output terminal. And an automatic voltage regulator connected to the integrator and the other terminal of the variable resistor and supplied via a scan driving IC. The method of claim 3, wherein The other part of the first and second voltage waveforms is selectively turned on by the automatic voltage regulator by selectively turning on the first and second switches connected between one terminal of the second and third capacitors and the automatic voltage regulator, respectively. And a voltage previously charged to the second or third capacitor is supplied via the scan driving IC. The method of claim 2, The second scan electrode driving apparatus includes an energy recovery circuit, and the third voltage waveform is supplied using the energy recovery circuit. A first voltage waveform for supplying a uniform initial state of all of the plurality of discharge cells and a second voltage waveform for selecting a discharge cell for maintaining a sustain discharge among the plurality of discharge cells. A first scan bus electrode; And a second scan bus electrode formed on the scan electrode in parallel with the first scan bus electrode to supply a third voltage waveform for maintaining a sustain discharge of the selected discharge cell. In the apparatus, A first scan electrode driving device for supplying the first and second voltage waveforms to the scan electrode through the first scan bus electrode; And A second scan electrode driving device for supplying the third voltage waveform to the scan electrode through the second scan bus electrode; And And a sustain electrode driving device for supplying a fourth voltage waveform for maintaining the sustain discharge of the selected discharge cell to the sustain electrode through the sustain bus electrode. The method of claim 6, And the third and fourth voltage waveforms are respectively supplied using the second scan electrode driving device and the sustain electrode driving device each including an energy recovery circuit. The method of claim 6, And the third and fourth voltage waveforms are applied between the second scan bus electrode and the sustain electrode using an integrated device including one energy recovery circuit. The method of claim 8, The integrated device, An energy recovery capacitor and an energy recovery inductor Ls connected in series; A first bidirectional switch connected between one terminal of the energy recovery inductor and the second scan bus electrode; A second bidirectional switch connected between one terminal of the energy recovery inductor and the sustain electrode; A twelfth switch and a fourteenth switch connected to the second scan bus electrode and used to supply a sustain pulse voltage or a base voltage to the second scan bus electrode; And And an eleventh switch and a thirteenth switch connected to the sustain electrode and used to supply a sustain pulse voltage or a base voltage to the sustain electrode. Supplying a first voltage waveform for discharging wall charges already formed in the discharge cells by discharging a plurality of discharge cells through a first scan bus electrode formed on the scan electrode; Supplying a second voltage waveform for selecting a discharge cell to sustain sustain discharge among the plurality of discharge cells through the first scan bus electrode; And And supplying a third voltage waveform for maintaining sustain discharge to the selected discharge cell through a second scan bus electrode formed on the scan electrode in parallel with the first scan bus electrode. How to drive the panel. The method of claim 10, Part of the first and second voltage waveforms includes an operational amplifier having an inverting input terminal connected to one terminal of the variable resistor and the first capacitor, a non-inverting input terminal grounded, and the other terminal of the first capacitor connected to the output terminal. And an automatic voltage regulator connected to the integrator and the other terminal of the variable resistor and supplied via a scan driving IC. The method of claim 11, The other part of the first and second voltage waveforms is selectively turned on by the automatic voltage regulator by selectively turning on the first and second switches connected between one terminal of the second and third capacitors and the automatic voltage regulator, respectively. And a voltage previously charged to the second or third capacitor is supplied via the scan driving IC. The method of claim 10, And supplying a fourth voltage waveform to the selected discharge cell through the sustain bus electrode to maintain the sustain discharge in the selected discharge cell. The method of claim 13, Wherein the third and fourth voltage waveforms are applied between the second scan bus electrode and the sustain electrode as one integrated voltage waveform using an integrated device comprising one energy recovery circuit. How to drive the display panel.

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