KR100737703B1 - Plasma Display Apparatus and Driving Method thereof - Google Patents

Abstract

The present invention relates to a plasma display device and a driving method thereof.

The plasma display panel driving apparatus and driving method according to the present invention are related to a plasma display apparatus and a driving method for preventing mis-discharge, miss discharge and abnormal discharge, increasing dark room contrast and widening operation margin. The plasma display device and its driving method include applying a negative voltage to a first electrode and a positive voltage to a second electrode in a preliminary reset period to accumulate positive wall charges on the first electrode, and to generate the first electrode. The discharge cells are initialized in the reset period by using the wall charge distribution of the discharge cells in which the negative wall charges are accumulated on the two electrodes.

Description

Plasma display device and driving method thereof {Plasma Display Apparatus and Driving Method}

FIG. 1 is a diagram illustrating a subfield pattern of an 8 bit default code for implementing 256 gray levels in a plasma display.

2 is a plan view schematically showing an electrode arrangement of a three-electrode alternating surface discharge plasma display panel.

3 is a waveform diagram showing driving waveforms of a conventional plasma display panel.

4A through 4E are diagrams showing the wall charge distribution in the discharge cells that are changed by the driving waveform shown in FIG. 3 step by step.

FIG. 5 is a diagram illustrating a change in the external applied voltage between the scan electrode and the sustain electrodes and the gap voltage in the discharge cell during the setup period when the plasma display panel is driven by the driving waveform shown in FIG. 3.

6 is a waveform diagram showing a driving waveform of a first subfield period in the method of driving a plasma display device according to the first embodiment of the present invention.

7A to 7E are diagrams illustrating the wall charge distribution in the discharge cells that are changed by the driving waveform shown in FIG. 6 in steps.

8 is a waveform diagram showing driving waveforms of the remaining subfield periods other than the first subfield period in the method of driving the plasma display device according to the first embodiment of the present invention.

FIG. 9 is a diagram showing a wall charge distribution formed in the discharge cell immediately after the sustain period by the driving waveform shown in FIG.

FIG. 10 is a diagram showing the wall charge distribution and the gap voltage in the discharge cells formed before the setup period by the driving waveforms of FIGS. 6 and 8.

FIG. 11 is a diagram illustrating a change in the external applied voltage between the scan electrode and the sustain electrodes and the gap voltage in the discharge cell during the setup period when the plasma display panel is driven by the driving waveforms of FIGS. 6 and 8.

FIG. 12 is a view illustrating a change in polarity of wall charges on the sustain electrode during the erase period and the reset period by the conventional driving waveform shown in FIG. 3.

FIG. 13 is a view showing a change in polarity of wall charges on the sustain electrode during the reset period by the driving waveforms shown in FIGS. 6 and 8.

14 is a waveform diagram illustrating a method of driving a plasma display device according to a second embodiment of the present invention.

FIG. 15 is a waveform diagram illustrating a driving waveform of a first subfield in a method of driving a plasma display device according to a third exemplary embodiment of the present invention.

Fig. 16 is a waveform diagram showing driving waveforms of the remaining subfield periods other than the first subfield period in the plasma display device driving method according to the third embodiment of the present invention.

17 is a waveform diagram showing a drive waveform of one frame period to which the drive waveforms of FIGS. 15 and 16 are applied.

18 is a waveform diagram illustrating a method of driving a plasma display device according to a fourth embodiment of the present invention.

19 is a waveform diagram illustrating a method of driving a plasma display device according to a fifth embodiment of the present invention.

FIG. 20 is a waveform diagram illustrating driving waveforms of a first subfield period in a method of driving a plasma display device according to a sixth embodiment of the present invention.

21 is a waveform diagram showing driving waveforms of the remaining subfield periods other than the first subfield period in the plasma display device driving method according to the sixth embodiment of the present invention.

FIG. 22 is a waveform diagram illustrating driving waveforms of a first subfield period in a method of driving a plasma display device according to a seventh exemplary embodiment of the present invention.

FIG. 23 is a waveform diagram showing driving waveforms of the remaining subfield periods other than the first subfield period in the plasma display device driving method according to the seventh embodiment of the present invention.

FIG. 24 is a waveform diagram illustrating driving waveforms of a first subfield period in a method of driving a plasma display device according to an eighth embodiment of the present invention.

25 is a waveform diagram showing driving waveforms of the remaining subfield periods other than the first subfield period in the plasma display device driving method according to the eighth embodiment of the present invention.

26 is a waveform diagram illustrating a method of driving a plasma display device according to a ninth embodiment of the present invention.

FIG. 27 is a waveform diagram illustrating a portion of a driving waveform applied to subfields other than the first subfield in the driving waveform of the plasma display device according to the ninth embodiment of the present invention.

28A to 28D are diagrams showing the wall charge distribution in the discharge cells that are changed by the driving waveform of FIG. 27 step by step.

FIG. 29 is a waveform diagram illustrating an externally applied voltage difference between the scan electrode and the sustain electrode and a discharge cell gap voltage between the scan electrode and the sustain electrode in the driving waveform of FIG. 27.

FIG. 30 is a waveform diagram illustrating an externally applied voltage difference between the scan electrode and the address electrode and a discharge cell gap voltage between the scan electrode and the address electrode in the driving waveform of FIG. 26.

31 is a waveform diagram illustrating a driving waveform applied to subfields of one frame period in the driving waveform of the plasma display device according to the tenth embodiment of the present invention.

32 is a block diagram illustrating a plasma display device according to an exemplary embodiment of the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plasma display panel, and more particularly, to an apparatus and method for driving a plasma display panel capable of improving gray scale display power of a plasma display panel.

In general, a plasma display device displays an image by exciting an phosphor by using ultraviolet rays generated when an inert mixed gas such as He + Xe, Ne + Xe, He + Xe + Ne is discharged. The plasma display device is not only thin and large in size, but also has improved in image quality due to recent technology development.

Such a plasma display device is time-divisionally driven by dividing one frame into several subfields having different number of emission times in order to realize gray level of an image. Each subfield is divided into a reset period for initializing the full screen, an address period for selecting a scan line and selecting a discharge cell in the selected scan line, and a sustain period for implementing gradation according to the number of discharges. For example, when the image is to be displayed with 256 gray levels, the frame period (16.67 ms) corresponding to 1/60 second is divided into eight subfields SF1 to SF8 as shown in FIG. As described above, each of the eight subfields SF1 to SF8 is divided into an initialization period, an address period, and a sustain period. The initialization period and the address period of each subfield are the same for each subfield, while the sustain period and the number of sustain pulses allocated thereto are 2n (n = 0,1,2,3,4,5,6, 7) is increased in proportion.

2 schematically shows an electrode arrangement of a conventional three-electrode alternating surface discharge plasma display panel (hereinafter referred to as "PDP"). Referring to FIG. 2, the conventional three-electrode AC surface discharge type PDP includes scan electrodes Y1 to Yn and sustain electrodes Z, scan electrodes Y1 to Yn, and sustain electrodes Z formed on an upper plate. Address electrodes X1 to Xm formed on the lower plate to be orthogonal to each other. At the intersections of the scan electrodes Y1 to Yn, the sustain electrodes Z and the address electrodes X1 to Xm, discharge cells 1 for displaying any one of red, green and blue are arranged in a matrix form. Is placed. On the top plate on which the scan electrodes Y1 to Yn and the sustain electrodes Z are formed, a dielectric layer and an MgO protective layer (not shown) are stacked. On the lower plate where the address electrodes X1 to Xm are formed, partition walls are formed between the discharge cells 1 to prevent optical and electrical interference. On the lower plate and the partition wall surface, phosphors are excited by ultraviolet rays and emit visible light. An inert mixed gas such as He + Xe, Ne + Xe, He + Xe + Ne is injected into the discharge space between the upper and lower plates of the PDP.

3 illustrates a driving waveform supplied to the PDP as shown in FIG. 2. The driving waveform of FIG. 3 will be described with reference to the wall charge distribution of FIGS. 4A to 4E. Referring to FIG. 3, each of the subfields SFn-1 and SFn includes a reset period RP for initializing the discharge cells 1 of the full screen, an address period AP for selecting a discharge cell, A sustain period SP for maintaining the discharge of the selected discharge cells 1 and an erasing period EP for erasing the wall charges in the discharge cell 1. The erase ramp waveform ERR is applied to the sustain electrodes Z in the erase period EP of the n−1 th subfield SFn−1. 0V is applied to the scan electrodes Y and the address electrodes X during the erase period EP. The erase ramp waveform ERR is a positive ramp waveform in which the voltage gradually rises from 0V to the positive sustain voltage Vs. The erase discharge is generated between the scan electrode Y and the sustain electrode Z in the on-cells in which the sustain discharge has been caused by the erase ramp waveform ERR. By this erase discharge, wall charges in the on cells are erased. As a result, each of the discharge cells 1 has a wall charge distribution as shown in FIG. 4A immediately after the erasing period EP.

In the setup period SU of the reset period RP at which the nth subfield SFn starts, the positive ramp waveform PR is applied to all the scan electrodes Y, and the sustain electrodes Z and the address electrodes are applied. 0 (V) is applied to (X). Due to the positive ramp waveform PR in the setup period UP, the voltage on the scan electrodes Y gradually rises from the positive sustain voltage Vs to a higher reset voltage Vr. The positive ramp waveform PR generates dark discharge in which light is hardly generated between the scan electrodes Y and the address electrodes X in the discharge cells of the full screen. Dark discharge also occurs between the field Y and the sustain electrodes Z. FIG. As a result of this dark discharge, positive wall charges remain on the address electrodes X and the sustain electrodes Z immediately after the setup period SU, as shown in FIG. 4B, and on the scan electrodes Y. Wall charges remain. The gap voltage Vg between the scan electrodes Y and the sustain electrodes Z and the scan electrodes Y and the address electrodes X during the dark discharge are generated during the setup period SU. The gap voltage between them is initialized to a voltage close to the discharge ignition voltage Vf, which can cause discharge.

Following the setup period SU, the negative ramp waveform NR is applied to the scan electrodes Y in the setdown period SD of the reset period RP. At the same time, a positive sustain voltage Vs is applied to the sustain electrodes Z, and 0 [V] is applied to the address electrodes X. Due to the negative ramp waveform NR, the voltage on the scan electrodes Y is gradually lowered from the positive sustain voltage Vs to the negative erase voltage Ve. By the negative ramp waveform NR, dark discharge is generated between the scan electrodes Y and the address electrodes X in the discharge cells of the full screen, and at almost the same time, the scan electrodes Y and the sustain electrodes ( A dark discharge occurs between Z). As a result of the dark discharge during this set-down period SD, the wall charge distribution in each of the discharge cells 1 is changed to an addressable condition as shown in FIG. 4C. At this time, unnecessary transient wall charges are erased on the scan electrodes Y and the address electrodes X in each of the discharge cells 1, and a certain amount of wall charges remains. The wall charges on the sustain electrodes Z are inverted from the positive to the negative polarity as the negative wall charges transferred from the scan electrodes Y accumulate. The gap voltage between the scan electrodes Y and the sustain electrodes Z, the scan electrodes Y and the address electrodes X during the dark discharge is generated in the set down period SD of the reset period RP. The gap voltage between them becomes close to the discharge ignition voltage Vf.

In the address period AP, the negative scan pulse -SCNP is sequentially applied to the scan electrodes Y, and the positive data pulses are applied to the address electrodes X in synchronization with the scan pulse -SCNP. DP) is applied. The voltage of the scan pulse (-SCNP) is the scan voltage (Vsc) lowered from the negative scan bias voltage (Vyb) of 0 V or close thereto to the negative scan voltage (-Vy). The voltage of the data pulse DP is the positive data voltage Va. During this address period (AP), the sustain electrodes Z are supplied with a positive Z bias voltage Vzb lower than the positive sustain voltage Vs. Scan in the on-cells to which the scan voltage Vsc and the data voltage Va are applied while the gap voltage is adjusted to be close to the discharge ignition voltage Vf immediately after the reset period RP. The primary address discharge is generated between the electrodes Y and X while the gap voltage between the electrodes Y and the address electrodes X exceeds the discharge ignition voltage Vf. Here, the primary address discharge of the scan electrode Y and the address electrode X occurs near the edge far from the gap between the scan electrode Y and the sustain electrode Z. The primary address discharge between the scan electrodes Y and the address electrodes X generates priming charged particles in the discharge cell, and thus the secondary between the scan electrodes Y and the sustain electrodes Z as shown in FIG. 4D. Induce discharge. The wall charge distribution in the on cells where the address discharge is generated is shown in FIG. 4E.

On the other hand, the wall charge distribution in the off-cells where no address discharge has occurred remains substantially in the state of FIG. 4C.

In the sustain period SP, sustain pulses SUSP of the positive sustain voltage Vs are alternately applied to the scan electrodes Y and the sustain electrodes Z. FIG. Then, the on-cells selected by the address discharge generate a sustain discharge between the scan electrodes Y and the sustain electrodes Z at each sustain pulse SUSP with the help of the wall charge distribution of FIG. 4E. In contrast, the off-cells do not discharge during the sustain period. This is because the wall charge distribution of the off cells is maintained in the state of FIG. 4C so that the gap between the scan electrodes Y and the sustain electrodes Z is applied when the initial positive sustain voltage Vs is applied to the scan electrodes Y. FIG. This is because the voltage cannot exceed the discharge ignition voltage Vf.

However, the conventional plasma display device performs initialization and initialization of the discharge cells 1 through the erase period EP of the n-1 th subfield SFn-1 and the reset period RP of the n th subfield SFn. Since the discharge is generated several times for the wall charge control, there is a problem that the darkroom contrast value is lowered, thereby lowering the contrast ratio. Table 1 below summarizes the types and number of discharges generated in the erase period EP and the reset period RP of the previous subfield SFn-1 in the conventional plasma display device.

As can be seen from Table 1, the scan electrodes Y and the sustain electrodes Z are subjected to the erase period EP and the reset period RP in the on cells that are turned on in the n-1 th subfield SFn-1. The surface discharge between the three electrodes) occurs three times, and the opposite discharge between the scan electrodes Y and the address electrodes X occurs twice. In the off-cells turned off in the previous subfield SFn, two surface discharges occur between the scan electrodes Y and the sustain electrodes Z through the erase period EP and the reset period RP. The opposite discharge between the scan electrodes Y and the address electrodes X occurs twice.

The discharges generated several times in the erasing period and the reset period cause the darkroom contrast value to be lowered by increasing the amount of light emission in the erasing period and the reset period in which the amount of light emission possible should be minimized in consideration of the contrast characteristic. In particular, the surface discharge between the scan electrodes (Y) and the sustain electrodes (Z) has a larger amount of light emission than the counter discharge between the scan electrodes (Y) and the address electrodes (X). Greater adverse effect on darkroom contrast.

In addition, in the conventional plasma display device, wall charges are not erased well in the erasing period EP of the n-1 th subfield SFn-1, so that the negative wall charges are excessively accumulated on the scan electrodes Y. In this case, dark discharge does not occur in the setup period SU of the nth subfield SFn. If dark discharge does not occur normally in the setup period SU, the discharge cells are not initialized. In this case, the reset voltage Vr must be higher in order to allow discharge to occur in the setup period. If dark discharge does not occur in the setup period SU, abnormal discharge or false discharge occurs because the condition in the discharge cell immediately after the reset period does not become an address optimum condition. Further, when the positive wall charges are excessively accumulated on the scan electrodes Y immediately after the erasing period EP of the n−1th subfield SFn-1, the setup period of the nth subfield SFn ( In SU, when the positive sustain voltage Vs, which is the start voltage of the positive lamp PR, is applied to the scan electrodes Y, the discharge is strongly generated, so that initialization is not uniform in all the cells. Such problems will be described in detail with reference to FIG. 5.

5 shows the externally applied voltage Vyz between the scan electrodes Y and the sustain electrodes Z and the gap voltage Vg in the discharge cell during the setup period SU. Here, the externally applied voltage Vyz indicated by the solid line in FIG. 5 is an external voltage applied to each of the scan electrodes Y and the sustain electrodes Z, so that 0 V is applied to the sustain electrodes Z, thereby being substantially positive. It is equal to the voltage of the ramp waveform PR. In Fig. 5, the dotted lines 1, 2, and 3 are gap voltages Vg formed in the discharge gas by wall charges in the discharge cells. The gap voltage Vg is changed like the dotted lines of 1, 2, and 3 because the wall charge in the discharge cell varies depending on whether or not a discharge has occurred in the previous subfield. The relationship between the externally applied voltage Vyz between the scan electrodes Y and the sustain electrodes Z and the gap voltage Vg formed in the discharge gas in the discharge cell is expressed by Equation 1 below.

Vyz = Vg + Vw

In FIG. 5, the gap voltage Vg of ① is a case where the wall charge is sufficiently erased in the discharge cell and the wall charge is sufficiently small. The gap voltage Vg increases in proportion to the externally applied voltage Vyz, and then the discharge ignition voltage ( When Vf) is reached, dark discharge occurs. By this dark discharge, the gap voltage in the discharge cells is initialized to the discharge ignition voltage Vf.

In FIG. 5, the gap voltage Vg in FIG. 5 is a case where strong discharge occurs during the erase period EP of the n−1 th subfield SF, thereby inverting the polarity of the wall charges in the wall charge distribution in the discharge cells. At this time, the polarities of the wall charges accumulated on the scan electrodes Y immediately after the erasing period EP are reversed to positive polarities due to the strong discharge. This case is caused when the uniformity of the discharge cells is low or the slope of the erase ramp waveform ERR changes according to the temperature change when the size of the PDP is large. In this case, since the initial gap voltage Vg becomes excessively high as shown in ② of FIG. 5, the positive sustain low voltage Vs is applied to the scan electrodes Y during the setup period SU, and the gap voltage Vg is simultaneously applied. Strong discharge is generated in excess of the discharge ignition voltage Vf. This strong discharge causes the address discharge in the off-cells to be turned off in the setup period SU and the set-down period SD since the discharge cells are not initialized to the wall charge distribution of the address optimum condition, that is, the wall charge distribution of FIG. 4C. Can happen. That is, erroneous discharge may occur when the erase discharge is strongly generated in the erase period before the reset period.

In FIG. 5, the gap voltage Vg of ③ is a discharge cell formed as a result of the sustain discharge occurring immediately before the erase discharge because the erase discharge does not occur or is very weak during the erase period EP of the n−1 th subfield SF. This is the case when the wall charge distribution in the field is kept as it is. In detail, the last sustain discharge occurs when the sustain pulse SSUS is applied to the scan electrodes Y as shown in FIG. 3. As a result of this last sustain discharge, negative wall charges remain on the scan electrodes Y, and positive wall charges remain on the sustain electrodes Z, but these wall charges are not normally initialized in the next subfield. It should be erased, but if the erase discharge does not occur or the erase discharge occurs very weakly, its polarity is maintained. The reason why the erase discharge does not occur or occurs very weakly is caused by the uniformity of the discharge cells in the PDP or the inclination of the erase ramp waveform ERR according to the temperature change. In this case, since the initial gap voltage Vg is very low as shown in Fig. 5 ③, even if the positive ramp waveform PR rises to the reset voltage Vr in the setup period, the gap voltage Vg in the discharge cells is increased. Since the discharge ignition voltage Vf is not reached, dark discharge does not occur in the setup period SU and the setdown period SD. As a result, when the erase discharge does not occur in the erase period preceding the reset period or very weakly, the initialization is not normally performed, and thus false discharge or abnormal discharge occurs.

In the case of ② of FIG. 5, the relationship between the gap voltage Vg and the discharge ignition voltage is represented by Equation 2, and in the case of ③ of FIG. 5, the relationship between the gap voltage Vg and the discharge ignition voltage is represented by Equation 3 below. Same as

Vgini + Vs> Vf

Vgini + Vr <Vf

Here, Vgini is an initial gap voltage just before the start of the setup period SU, as shown in FIG. In consideration of the above problems, the gap voltage condition (or wall voltage condition) for the initialization to proceed normally in the erase period EP and the reset period RP is represented by Equations 4 and 3 below. same.

Vf-Vr <Vgini <Vf-Vs

As a result, if the initial gap voltage Vgini does not satisfy the condition of Equation 4 before the set-up period SU, the conventional plasma display device may cause mis-discharge, mis-discharge, or abnormal discharge, and the operating margin becomes narrow. In other words, in order to secure the operation reliability and the operation margin in the conventional plasma display device, the erasing operation should be performed normally in the erasing period EP. Can be.

In addition, in the conventional plasma display device, since the wall charges accumulated on the scan electrode Y and the sustain electrode Z before the reset period are insufficient, the reset voltage Vr 100 V or more higher than the sustain voltage Vs is set. ) Happen in the vicinity. For this reason, the conventional plasma display device has a high voltage applied from the outside for the set-up discharge, and as a result, a high voltage device and a high voltage element must be included in the scan drive circuit. .

In the conventional plasma display apparatus, as shown in FIG. 4D, the address discharge is the primary discharge between the scan electrode Y and the address electrode X, and the scan electrode Y and the sustain electrode Z using the primary discharge. The time required for this is relatively long because it includes the secondary discharge in between. For this reason, when the plasma display device of the related art is driven by the driving waveform shown in FIG. 3, a problem arises in that the address period becomes shorter as the PDP or PDP increases in size with an increase in the number of lines. This problem is more serious in the high content Xe PDP with a large jitter value, that is, a discharge delay value.

Accordingly, an object of the present invention is to provide a plasma display device and a driving method thereof to prevent mis-discharge, miss discharge and abnormal discharge, increase dark-room contrast, and widen operating margin.

Another object of the present invention is to provide a plasma display device and a method of driving the same, which lower the setup discharge.

It is still another object of the present invention to provide a plasma display device and a driving method thereof which shorten the time required for address discharge.

According to an embodiment of the present invention, a plasma display device includes a surface discharge electrode pair including a first electrode and a second electrode, a third electrode crossing the surface discharge electrode pair, and the surface discharge electrode pair; A plurality of discharge cells disposed at intersections with the third electrodes, the first waveform being applied to the first electrode in a pre-reset period prior to a reset period for initializing the discharge cells, A first driving part configured to apply a first ramp waveform having a reverse polarity with the first waveform to the first electrode, and then apply a second ramp waveform having a reverse polarity with the first ramp waveform, and the pre-reset period Apply a second waveform having a reverse polarity to the second waveform to the second electrode, and in the reset period, the second electrode has the same polarity as the second ramp waveform in synchronization with the second ramp waveform. The second driving unit for applying the third ramp waveform of the The.

In another embodiment, a plasma display device includes a surface discharge electrode pair including a first electrode and a second electrode, a third electrode crossing the surface discharge electrode pair, and the surface discharge electrode pair and the third electrode. And a plurality of discharge cells disposed at the intersection with each other, applying a first waveform to the first electrode in a pre-reset period prior to a reset period for initializing the discharge cells, and in the reset period, the first waveform. A first driving part for applying a first ramp waveform having a reverse polarity with the first waveform to the electrode, and then applying a second ramp waveform having a reverse polarity with the first ramp waveform, and in the pre-reset period, A second waveform having a reverse polarity from the first waveform is applied to two electrodes, and in the reset period, a third lamp having the same polarity as the second ramp waveform in synchronization with the second ramp waveform to the second electrode. And a second driver configured to apply a waveform, wherein the pre-reset unit At least one of the first waveform applied to the first electrode and the second waveform applied to the first electrode and the second waveform of reverse polarity is present in one frame.

In another embodiment, a plasma display device includes a surface discharge electrode pair including a first electrode and a second electrode, a third electrode crossing the surface discharge electrode pair, and the surface discharge electrode pair and the third electrode. And a plurality of discharge cells disposed at the intersection with each other, applying a first waveform to the first electrode in a pre-reset period prior to a reset period for initializing the discharge cells, and in the reset period, the first waveform. A first driving part for applying a first ramp waveform having a reverse polarity with the first waveform to the electrode, and then applying a second ramp waveform having a reverse polarity with the first ramp waveform, and in the pre-reset period, And a second driver for applying a second waveform having a reverse polarity to one waveform and applying a third ramp waveform having the same polarity as the second ramp waveform in synchronization with the second ramp waveform in the reset period. The second driving unit is applied to the second ramp waveform Before it is characterized by holding the second electrode and exit the application of the third ramp waveform as a reference voltage.

According to another exemplary embodiment of the present invention, a plasma display device includes a surface discharge electrode pair including a first electrode and a second electrode, a third electrode crossing the surface discharge electrode pair, and the surface discharge electrode pair and the third electrode; And a plurality of discharge cells disposed at the intersections of the first electrodes and applying a first waveform to the first electrodes in a pre-reset period prior to a reset period for initializing the discharge cells. A first driving unit configured to apply a first ramp waveform having a reverse polarity to the first waveform, and to apply a second ramp waveform having a reverse polarity to the first ramp waveform, and to perform the second reset waveform during the preset period. And a second driver for applying a first square wave having a reverse polarity to the first waveform and applying a second square wave having a reverse polarity to the second ramp waveform in the reset period.

In another embodiment, a plasma display device includes a surface discharge electrode pair including a first electrode and a second electrode, a third electrode crossing the surface discharge electrode pair, and the surface discharge electrode pair and the third electrode; And a plurality of discharge cells disposed at the intersections of the first electrodes, the first waveforms being applied to the first electrodes in a pre-reset period prior to the reset period, and in the reset periods for initializing the discharge cells. A first driving unit configured to apply a first ramp waveform having a reverse polarity to the first waveform, and to apply a second ramp waveform having a reverse polarity to the first ramp waveform, and to perform the second reset waveform during the preset period. And a second driver configured to apply a first square wave having a reverse polarity to the first waveform to the electrode, and apply a second square wave having a reverse polarity to the second ramp waveform during the reset period. The voltage level of the waveform is the voltage level of the second lamp waveform. Characterized in that the same or higher than that.

In another embodiment, a plasma display device includes a surface discharge electrode pair including a first electrode and a second electrode, a third electrode crossing the surface discharge electrode pair, and the surface discharge electrode pair and the third electrode; And a reference voltage applied to the first electrode in a pre-reset period prior to a reset period in which the discharge cell is initialized, wherein the reference voltage is applied to the first electrode in the reset period. A first driving unit for applying a second ramp waveform having a reverse polarity to the first ramp waveform after applying a first ramp waveform, and having the same polarity as the first ramp waveform to the second electrode during the pre-reset period; Applies a third ramp waveform, and applies a fourth ramp waveform having the same polarity as the second ramp waveform, and in the reset period, a fifth ramp waveform having the same polarity as the second ramp waveform to the second electrode. It is provided with a second driving unit for applying.

In another embodiment, a plasma display device includes a surface discharge electrode pair including a first electrode and a second electrode, a third electrode crossing the surface discharge electrode pair, and the surface discharge electrode pair and the third electrode; A plurality of discharge cells disposed at the intersections of the first electrodes; and a first waveform applied to the first electrode in a pre-reset period prior to a reset period for initializing the discharge cells, and in the reset period, the first electrode. A first driving unit configured to apply a first ramp waveform having a reverse polarity to the first waveform, and to apply a second ramp waveform having a reverse polarity to the first ramp waveform, and to perform the second reset waveform during the preset period. And a second driver for applying a reference voltage to the electrode and applying a third ramp waveform having the same polarity as the second ramp waveform to the second electrode in the reset period.

In another embodiment, a plasma display device includes a surface discharge electrode pair including a first electrode and a second electrode, a third electrode crossing the surface discharge electrode pair, and the surface discharge electrode pair and the third electrode; A plurality of discharge cells disposed at the intersections of the first electrodes; and a first waveform applied to the first electrode in a pre-reset period prior to a reset period for initializing the discharge cells, and in the reset period, the first electrode. A first driving unit which applies a first ramp waveform having a reverse polarity to the first waveform, and then applies a second ramp waveform having a reverse polarity to the first ramp waveform starting from a reference voltage; And applying a second waveform having a reverse polarity to the first waveform to the second electrode, and applying a third ramp waveform having the same polarity as the second ramp waveform to the second electrode during the reset period. A second driving unit is provided.

In another embodiment, a plasma display device includes a surface discharge electrode pair including a first electrode and a second electrode, a third electrode crossing the surface discharge electrode pair, and the surface discharge electrode pair and the third electrode; A plurality of discharge cells disposed at the intersections of the first electrodes; and a first waveform applied to the first electrode in a pre-reset period prior to a reset period for initializing the discharge cells, and in the reset period, the first electrode. A first driving unit which applies a first ramp waveform having a reverse polarity to the first waveform, and then applies a second ramp waveform having a reverse polarity to the first ramp waveform starting from a reference voltage; And a second driver configured to apply a second waveform having a reverse polarity to the first waveform to the second electrode and to apply a reference voltage to the second electrode in the reset period.

In another embodiment, a plasma display device includes a surface discharge electrode pair including a first electrode and a second electrode, a third electrode crossing the surface discharge electrode pair, and the surface discharge electrode pair and the third electrode; And a plurality of discharge cells disposed at the intersections of the first electrodes and applying a first waveform to the first electrodes in a pre-reset period prior to a reset period for initializing the discharge cells. A first driving unit configured to apply a first ramp waveform having a reverse polarity to the first waveform, and to apply a second ramp waveform having a reverse polarity to the first ramp waveform, and to perform the second reset waveform during the preset period. A second driver for applying a second waveform having a reverse polarity to the first waveform to the electrode and applying a third ramp waveform having the same polarity as the second ramp waveform to the second electrode in the reset period; In the reset period, the third electrode to the second ramp waveform Gihayeo said second ramp and is provided with a third driver for applying a third square-wave of opposite polarity.

In another embodiment, a plasma display device includes a surface discharge electrode pair including a first electrode and a second electrode, a third electrode intersecting the surface discharge electrode pair, and a pair of the surface discharge electrode pair and the third electrode. A plurality of discharge cells disposed at the intersections, the first waveform being applied to the first electrode in a pre-reset period prior to the reset period for initializing the discharge cells, and in the reset period, A first driving part configured to apply a first ramp waveform having a reverse polarity with the first waveform, and then apply a second ramp waveform having a reverse polarity with the first ramp waveform, and the second electrode in the preset period. And a second driver configured to apply a second waveform having a reverse polarity to the first waveform and apply a reference voltage to the second electrode during the reset period.

In another embodiment, a plasma display device includes a surface discharge electrode pair including a first electrode and a second electrode, a third electrode crossing the surface discharge electrode pair, and the surface discharge electrode pair and the third electrode; A plurality of discharge cells disposed at the intersections of the first electrodes; and a first waveform applied to the first electrode in a pre-reset period prior to a reset period for initializing the discharge cells, and in the reset period, the first electrode. A first driving unit configured to apply a first ramp waveform having a reverse polarity to the first waveform, and to apply a second ramp waveform having a reverse polarity to the first ramp waveform, and to perform the second reset waveform during the preset period. And a second driver for applying a first square wave of reverse polarity to the first waveform and applying a reference voltage to the second electrode in the reset period.

In another embodiment, a plasma display device includes a surface discharge electrode pair including a first electrode and a second electrode, a third electrode crossing the surface discharge electrode pair, and the surface discharge electrode pair and the third electrode; The electrode pair driving unit includes a plurality of discharge cells disposed at the intersections of the electrodes, an electrode pair driving unit for driving the surface discharge electrode pairs, and a pre-reset period prior to a reset period for initializing the discharge cells. A first waveform is applied between the surface discharge electrode pairs, and during the reset period, the electrode pair driver applies a first ramp waveform having a reverse polarity to the first waveform between the surface discharge electrode pairs. And discharging the discharge cell while maintaining the polarity of the charge on at least one of the charges accumulated in the surface discharge electrode pair in the pre-reset period.

In another embodiment, a plasma display device includes a first substrate including at least one electrode, a second substrate including at least one electrode, and a plurality of substrates disposed between the first substrate and the second substrate. A first waveform is applied to the first substrate in a pre-reset period prior to a reset period for initializing a discharge cell and the discharge cell, and a first polarity opposite to the first waveform to the first substrate in the reset period. The discharge cell may be initialized by applying a ramp waveform.

In another embodiment, a plasma display device includes a first substrate including at least one electrode, a second substrate including at least one electrode, and a plurality of substrates disposed between the first substrate and the second substrate. In a pre-reset period prior to a discharge cell and a reset period for initializing the discharge cell, a first waveform and a second waveform having reverse polarity with the first waveform are applied to the first substrate, and the first substrate is in the reset period. The discharge cell may be initialized by applying a first ramp waveform having a reverse polarity to the first waveform.

In another embodiment, a plasma display device includes a first substrate including at least one electrode, a second substrate including at least one electrode, and a plurality of substrates disposed between the first substrate and the second substrate. A first waveform is applied to the first substrate in a pre-reset period prior to a reset period for initializing a discharge cell and the discharge cell, and a first polarity opposite to the first waveform to the first substrate in the reset period; At least one of the charges accumulated in the electrode of the first substrate by applying the ramp waveform is characterized in that the discharge cell is initialized while maintaining the polarity of the charge.

In another embodiment, a plasma display device includes a first substrate including at least one electrode, a second substrate including at least one electrode, and a plurality of substrates disposed between the first substrate and the second substrate. A reference voltage is applied to some of the electrodes of the first substrate in a discharge cell and a reset period for initializing the discharge cell.

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

FIG. 6 illustrates driving waveforms supplied to the PDP as shown in FIG. 2 during the first subfield period in the plasma display device driving method according to the first embodiment of the present invention. The driving waveform of FIG. 6 will be described with reference to the wall charge distribution of FIGS. 7A to 7E. Referring to FIG. 6, in the method of driving a plasma display device according to the present invention, a first subfield forms positive wall charges on scan electrodes Y and negative wall charges on sustain electrodes Z. FIG. Pre-setting period PRERE for forming, reset period RP for initializing the discharge cells of the full screen using the wall charge distribution formed by the pre-resetting period PRERE, and address period for selecting the discharge cells (AP) and a sustain period SP for maintaining the discharge of the selected discharge cells. In this embodiment, as shown in Fig. 7A, positive charges of the scan electrodes are sufficiently accumulated by the surface discharge between the scan electrodes and the sustain electrodes that occur during the pre-reset period, and negative charges are sufficiently accumulated on the sustain electrodes. . As a result, the Y reset voltage Vry can be reduced in the reset period, and the contrast can be improved.

In the pre-reset period PRERP, the Z positive ramp waveform PRZ is applied to all the sustain electrodes Z to increase the voltage from the positive sustain voltage Vs to the positive Z reset voltage Vrz. The first Y negative ramp waveform NRY1 whose voltage is lowered from 0 V or the base voltage reference voltage GND to the negative -V1 voltage is applied to the field Y. While the voltage of the sustain electrodes Z is increased by the positive ramp waveform PRZ, the voltage of the scan electrodes Y is lowered by the first Y negative ramp waveform NRY1, and the voltage V1 is maintained for a predetermined time. do. 0 V is applied to the address electrodes X during this pre-reset period PRERP. The Z positive ramp waveform PRZ and the first Y negative ramp waveform NRY1 are disposed between the scan electrodes Y and the sustain electrodes Z, the sustain electrodes Z and the address electrodes in all discharge cells. X) Causes a dark discharge between. As a result of this discharge, positive wall charges are accumulated on the scan electrodes Y in all the discharge cells immediately after the pre-reset period PRERP, as shown in FIG. 7A, and negative wall charges on the sustain electrodes Z. Will accumulate a lot. Positive wall charges are accumulated on the address electrodes X. Due to the wall charge distribution of FIG. 7A, a sufficiently large positive gap voltage is formed between the scan electrodes Y and the sustain electrodes Z in the internal discharge gas spaces of all the discharge cells, and scan electrodes Y are formed in each discharge cell. An electric field is formed toward the sustain electrodes Z from the side. As such, at least one ramp waveform applied to the scan electrodes or the sustain electrodes in the preset period is supplied in the subfield of one frame. Preferably, the ramp waveforms applied to the scan electrodes or the sustain electrodes in the preset period are supplied to the first subfield in one frame. This is because the first subfield in a frame is more difficult than other subfields in initializing a cell. That is, the first subfield of space charge in the cell is relatively small compared to the other subfields, making it difficult to initialize. In particular, this phenomenon is more likely to occur when the temperature inside the panel is high. Therefore, it is more preferable to apply ramp waveforms to the scan electrodes or the sustain electrodes in the pre-reset period when the temperature is higher than the threshold temperature, that is, 40 ° C or higher. In addition, the voltage of the sustain electrode Z is gradually lowered to 0V or the reference voltage GND by the first negative ramp waveform NRZ1, so that the voltage of the scan electrode Y and the sustain electrode during the set-up period. The difference with the voltage of Z) is increased to enhance the wall charge formation. This reduces misdischarge at high temperatures.

In the setup period SU of the reset period RP, the first Y positive ramp waveform PRY1 and the second Y positive ramp waveform PRY2 are successively applied to all the scan electrodes Y, and the sustain electrodes Z are applied. ) And address electrodes X are applied with 0 [V]. The voltage of the first Y positive ramp waveform PRY1 rises from 0V to the positive sustain voltage Vs, and the voltage of the second Y positive ramp waveform PRY2 is higher than the positive sustain voltage Vs. The voltage rises to the Y reset voltage Vry. The positive Y reset voltage Vry is a voltage less than or equal to the positive Z reset voltage Vrz, and is determined as a voltage between the positive Z reset voltage Vrz and the positive sustain voltage Vs. The slopes of the first Y positive ramp waveform PRY1 and the second Y positive ramp waveform PRY2 may be set to be the same. However, as shown in FIG. 6, the inclination of the second Y positive ramp waveform PRY2 is preferably set lower than the first Y positive ramp waveform PRY1. The reason for this is to prevent the occurrence of the strong discharge in the setup period of the reset period, that is, the setting of the slope of the second Y positive ramp waveform PRY2 is higher than the slope of the first Y positive ramp waveform PRY1. This is because strong discharge causes the contrast characteristic. In addition, the voltages of the electric field formed between the scan electrodes Y and the sustain electrodes Z in the first Y positive ramp waveform PRY1 and the discharge cells are added to the scan electrodes Y and the sustain electrodes in all the discharge cells. Dark discharge is generated between the electrodes Z and between the scan electrodes Y and the address electrodes X. FIG. As a result of this discharge, negative wall charges accumulate on the scan electrodes Y in all the discharge cells immediately after the setup period SU, as shown in FIG. 7B, and the polarity thereof is reversed from positive to negative. More positive wall charges are accumulated on the field X. The wall charges accumulated on the sustain electrodes Z are reduced in the amount of negative wall charges toward the scan electrodes Y, but the polarities thereof remain negative.

On the other hand, since the positive gap voltage is large enough in all the discharge cells before the dark discharge occurs in the set-down period SU due to the wall charge distribution immediately after the pre-reset period PRERP, the Y reset voltage Vr is shown in FIG. It may be lower than the same conventional reset voltage (Vr). As a result of initializing the wall charge distribution of all the discharge cells immediately before the setup discharge as shown in FIG. 7A, the setup discharge is the voltage below the sustain voltage Vs in all the discharge cells, that is, in the period of the first Y positive ramp waveform PRY1. It was confirmed that the drug discharge occurred. For this reason, in the driving waveform of FIG. 6, the second Y positive ramp waveform PRY2 may be unnecessary and the voltage applied to the scan electrodes Y in the setup period SU is applied to the first Y positive ramp waveform PRY1. Therefore, even if only the sustain voltage (Vs) rises, the setup discharge can be stably generated.

During the pre-reset period PRERE and the setup period SU, the positive electrode is sufficiently stacked on the address electrodes X, thereby lowering the external voltages required for address discharge, that is, the absolute values of the data voltage and the scan voltage. .

Following the setup period SU, in the set down period SD of the reset period RP, the second Y negative ramp waveform NRY2 is applied to the scan electrodes Y, and at the same time, the second sustain voltage is applied to the sustain electrodes Z. Z negative ramp waveform NRZ2 is applied. The voltage of the second Y negative ramp waveform NRY2 is lowered from the positive sustain voltage Vs to the negative -V2 voltage. The voltage of the second Z negative ramp waveform NRZ2 is lowered from the positive sustain voltage Vs to 0 V or the base voltage reference voltage. The -V2 voltage may be set equal to or different from the -V1 voltage of the pre-reset period PRERP. During this set-down period SD, the voltages of the scan electrodes Y and the sustain electrodes Z decrease at the same time so that no discharge occurs between them, while between the scan electrodes Y and the address electrodes X. Dark discharge occurs. The dark discharge erases the excess wall charges among the negative wall charges accumulated on the scan electrodes Y, and the excess wall charges among the positive wall charges accumulated on the address electrodes X. As a result, all the discharge cells have a uniform wall charge distribution as shown in FIG. 7C. In the wall charge distribution of FIG. 7C, since the negative wall charges are sufficiently accumulated on the scan electrodes Y and the positive wall charges are sufficiently stacked on the address electrodes X, the scan electrodes Y and the address electrodes are stacked. The gap voltage between (X) is raised close to the discharge ignition voltage Vf. Therefore, the wall charge distribution of all the discharge cells is adjusted to the address optimum condition immediately after the setdown period SD.

In the address period AP, the negative scan pulse -SCNP is sequentially applied to the scan electrodes Y, and the positive data pulses are applied to the address electrodes X in synchronization with the scan pulse -SCNP. DP) is applied. The voltage of the scan pulse (-SCNP) is the scan voltage (Vsc) lowered from the negative scan bias voltage (Vyb) of 0 V or close thereto to the negative scan voltage (-Vy). The voltage of the data pulse DP is the positive data voltage Va. During this address period (AP), the sustain electrodes Z are supplied with a positive Z bias voltage Vzb lower than the positive sustain voltage Vs. The positive Z bias voltage Vzb is preferably supplied between the set down end of the reset period and the application time of the first scan pulse applied to the scan electrodes Y. As such, the reason for applying the positive Z bias voltage Vzb to the setdown end point of the reset period is to reduce the potential difference between the scan electrodes Y and the sustain electrodes Z in the setdown period of the reset period. The discharge can be suppressed to improve the contrast characteristics. In addition, the reason why the positive Z bias voltage Vzb is applied within the application point of the first scan pulse applied to the scan electrodes Y is to not affect the address discharge generated in the address period. That is, to improve the jitter characteristic in the address period, the driving margin can be secured by reducing the width of the scan pulse applied to the scan electrodes Y in the conventional address period. Immediately after the reset period RP, in a state where the gap voltage is adjusted to the address optimum condition, the scan electrodes V and the address are in the on cells to which the scan voltage Vsc and the data voltage Va are applied. The address discharge occurs only between the electrodes Y and X while the gap voltage between the electrodes X exceeds the discharge ignition voltage Vf. The wall charge distribution in the on cells where the address discharge is generated is shown in FIG. 7D. Immediately after the address discharge occurs, the wall charge distribution in the on-cells changes as shown in FIG. 7E as the positive wall charges are accumulated on the scan electrodes Y and the negative wall charges are accumulated on the address electrodes X by the address discharge. .

In the address discharge, since the discharge occurs only between the scan electrode Y and the address electrode X as shown in FIG. 7D, the time required for the address discharge is greatly reduced.

On the other hand, the gap voltage is less than the discharge ignition voltage for off-cells in which 0 V or a base voltage reference voltage is applied to the address electrodes X or 0 V or a scan bias voltage Vyb is applied to the scan electrodes Y. Thus, the off-cells in which the address discharge has not occurred have their wall charge distribution substantially maintained in the state of FIG. 7C.

In the sustain period SP, sustain pulses FIRSTSUSP, SUSP, and LSTSUSP of the positive sustain voltage Vs are alternately applied to the scan electrodes Y and the sustain electrodes Z. FIG. During the sustain period SP, 0 V or a base voltage reference voltage is supplied to the address electrodes X. The first sustain pulse FSTSUSP applied to each of the scan electrodes Y and the sustain electrodes Z is set to have a wider pulse width than the normal sustain pulse SSUS so that the start of the sustain discharge is stable. Also, the last sustain pulse LSTSUSP is applied to the sustain electrodes Z. In the initial state of the setup period SU, the pulse width of the sustain pulse LSTSUSP is normal to sufficiently accumulate negative wall charges on the sustain electrodes Z. It is set wider than the pulse SUSP. On the cells selected by the address discharge during this sustain period, sustain discharge occurs between the scan electrodes Y and the sustain electrodes Z at each sustain pulse SUSP with the help of the wall charge distribution of FIG. 7E. On the contrary, since the initial wall charge distribution of the sustain period SP is the same as that of FIG. No discharge occurs.

Meanwhile, the driving waveform of FIG. 6 is not limited to the first subfield but may be applied to several initial subfields including the first subfield, and may be applied to all subfields included in one frame period.

8 shows a sustain period SP and an nth subfield of an n-1 (where n is a positive integer of 2 or more) th subfield SFn in the method of driving a plasma display device according to the first embodiment of the present invention. The driving waveform supplied to the PDP as shown in FIG. 2 during SFn is shown. The driving waveform of FIG. 8 will be described with reference to the wall charge distribution of FIG. 9. Referring to FIG. 8, the nth subfield SFn initializes all discharge cells of the PDP using a wall charge distribution formed immediately after the sustain period in the n−1th subfield SFn-1. Each of the n-1 th subfield SFn-1 and the n th subfield SFn is used to initialize all the discharge cells with the help of the wall charge distribution in which the negative wall charges are sufficiently accumulated on the sustain electrodes Z. A reset period RP, an address period AP for selecting the discharge cells, and a sustain period SP for maintaining the discharge of the selected discharge cells. In the sustain period of the n-1 th subfield SFn-1, the last sustain pulse SUSP is applied to the sustain electrodes Z. At this time, 0 V or a base voltage reference voltage is applied to the scan electrodes Y and the address electrodes X. FIG. The last sustain pulse LSTSUSP causes a last sustain discharge between the scan electrodes Y and the sustain electrodes Z in the discharge cells, and as shown in FIG. 9, a positive wall charge is applied on the scan electrodes Y. They are sufficiently stacked and the negative wall charges are accumulated on the sustain electrodes Z. During the setup period SU of the n-th subfield SFn, a dark discharge is generated in all the discharge cells by using the wall charge distribution of FIG. 9, and the wall charge distribution of all the discharge cells is precharged by the wall charge distribution as shown in FIG. 7B. Initialize the cells. This setup period SU and subsequent setdown initialization, address and sustain operations are substantially the same as the first subfield of FIG.

The plasma display device and its driving method according to the present invention, as described above, follow the last sustain discharge of the previous subfield without the erasing period for erasing the wall charge between the sustain period of the previous subfield and the reset period of the next subfield. This is followed by the setup period of the next subfield. Since the sustain discharge is a strong glow discharge, a large amount of wall charges are accumulated on the scan electrodes Y and the sustain electrodes Z, and the positive wall charges and the sustain electrodes Z on the scan electrodes Y are accumulated. The polarity of each of the negative wall charges of the phase can be kept stable.

Fig. 10 shows the gap voltage state of the discharge cells formed by the last sustain discharge or the discharge during the pre-reset period PRERP. Referring to FIG. 10, discharge is generated between the scan electrode Y and the sustain electrode Z by the waveforms NRY1, PRZ and NRZ1 of the last sustain pulse LSTSUSP or the pre-reset period PRERP. An initial gap voltage (Vgini-yz) between the YZs is formed within the Y electrode from the scan electrode (Y) to the sustain electrode (Z) immediately before the setup period (SU), and the address electrode (X) from the scan electrode (Y). The initial gap voltage (Vgini-yx) between the YZs is formed. As shown in FIG. 10, since the initial gap voltage Vgini-yz between YZs is formed by the wall charge distribution as shown in FIG. 10 before the setup period SU, the initial gap voltage between discharge ignition voltage Vf and YZ ( When voltage is applied externally by the difference of Vgini-yz), dark discharge is generated in the discharge cell during the setup period SU. This may be expressed as Equation 5 below.

Vyz = Vf- (Vgini-yz)

Here, 'Vyz' is an external voltage applied to the scan electrodes Y and the sustain electrodes Z during the setup period SU (hereinafter, referred to as “external YZ external voltage”). In the example, the voltages of the positive ramp waveforms PRY1 and PRY2 applied to the scan electrodes Y and 0V applied to the sustain electrodes Z are applied.

As can be seen from Equation 5 and FIG. 11, when the external voltage Vyz between YZ is sufficiently higher than the difference between the discharge ignition voltage Vf and the initial gap voltage Vgini-yz between YZ during the setup period SU, As a driving margin, dark discharge may occur stably in the surface discharge cell.

In the plasma display device according to the embodiment of the present invention, the amount of light emitted in each subfield reset period is much smaller than in the related art. This is because the number of discharges generated in the discharge cells during the reset periods of the respective subfields is smaller than in the prior art, and in particular, the number of surface discharges is small.

Table 2 summarizes the types and number of occurrences of discharges generated in the pre-reset period PRERP and the reset period RP of the first subfield described in the embodiment of FIG. 6, and Table 3 is an embodiment of FIG. 8. The types and number of occurrences of discharges generated in the reset period RP of each of the remaining subfields without the pre-reset period PRERP described in FIG.

As can be seen from Table 2, the first subfield of FIG. 6 generates a maximum of three counter discharges and two surface discharges during a pre-reset period (PRERP) and a reset period (RP). In the subsequent subfields, one counter discharge and up to two surface discharges occur during the reset period RP as shown in Table 3, and only one counter discharge occurs in the case of off-cells that are turned off in the previous subfield. Due to the difference in the number of discharges and the type of discharge, the plasma display device of the present invention has a luminance of 1/3 or less when the time division driving of one frame period into 12 subfields is performed. Lowers. Accordingly, the plasma display device according to the present invention can display a black screen with a lower dark room contrast value than in the related art, so that an image can be displayed more clearly.

On the other hand, the small number of discharges generated in the reset period RP means that the variation of the wall charges or the polarity change in the discharge cells are small.

For example, in the conventional plasma display device, as shown in FIG. 12, the sustain is performed from immediately after the last sustain discharge of the n-th subfield SFn-1 to immediately after the dark discharge of the set-down period SD of the n-th subfield SFn. The wall charges on the electrodes Z change in polarity from positive polarity to erase (FIG. 4A) to positive polarity (FIG. 4B) to negative polarity (FIG. 4C). In contrast, in the plasma display device according to the present invention, as shown in FIG. 13, immediately after the last sustain discharge of the n-th subfield SFn-1 to immediately after the dark discharge of the set-down period SD of the n-th subfield SFn. The wall charge polarity on the sustain electrodes Z is kept negative. That is, in the plasma display device according to the present invention, the wall charge polarity on the sustain electrodes X is maintained as shown in FIGS. 7A, 7B, and 7C during the initialization process, and proceeds to the address period AP. 14 is a waveform diagram illustrating a method of driving a plasma display device according to a second embodiment of the present invention. Referring to FIG. 14, in the method of driving the plasma display device according to the present invention, the second Z negative ramp waveform NRZ2 is less than the point of time when the second Y negative ramp waveform NRY2 reaches the base voltage reference voltage GND. Faster time to reach the low voltage reference voltage (GND). In this embodiment, the preset period PRERE, the setup period SU of the reset period RP, the address period AP, and the sustain period SP are substantially the same as those of the above-described embodiments, so a detailed description thereof will be given. It will be omitted.

During the set down period SD of the reset period RP, the second Y negative ramp waveform NRY2 is applied to the scan electrodes Y, and the second Z negative ramp waveform NRZ2 is applied to the sustain electrodes Z. ) Is applied. The voltage of the second Y negative ramp waveform NRY2 is lowered from the positive sustain voltage Vs to the negative -V2 voltage. The voltage of the second Z negative ramp waveform NRZ2 is lowered from the positive polarity Z bias voltage Vzb to 0V or the ground voltage reference voltage GND. After the second Z negative ramp waveform NRZ2 reaches the ground voltage reference voltage GND and the predetermined time difference Δtbottom elapses, the second Y negative ramp waveform NRY2 reaches the ground voltage reference voltage GND. do. When the voltage of the second Y negative ramp waveform NRY2 reaches the base voltage reference voltage GND while the voltage of the second Z negative ramp waveform NRZ2 is maintained at the base voltage reference voltage, the scan electrode Y Due to the coupling of the sustain electrode Z, the voltage variation of the scan electrode Y can be prevented to keep the voltage -V2 constant so that the driving margin can be stably secured. During this set down period SD, dark discharge is generated between the scan electrodes Y and the address electrodes X. FIG. The dark discharge erases the excess wall charges among the negative wall charges accumulated on the scan electrodes Y, and the excess wall charges among the positive wall charges accumulated on the address electrodes X. As a result, all the discharge cells have a uniform wall charge distribution under the address optimum condition.

FIG. 15 is a waveform diagram illustrating a method of driving a plasma display device according to a third exemplary embodiment of the present invention. FIG. 15 is a driving waveform of a subfield applied to a first subfield. Referring to FIG. 15, in the driving method of the plasma display device according to the present invention, the sustain waveform is supplied by supplying the square wave of the sustain voltage without supplying the ramp waveform to the sustain electrode Z during the pre-reset period PRERP. Accumulate and accumulate negative wall charges on the phase, and apply a square wave to the sustain electrode (Z) during the set-down period (SD) so that the sustain voltage (Z) is a positive bias voltage and the ground voltage (GND). Or 0V (Vzb).

In the pre-reset period PRERP, the positive sustain voltage Vs is supplied to all the sustain electrodes Z before the first Y negative ramp waveform NRY1 supplied to the scan electrodes Y. That is, the first Y negative ramp waveform NRY1 is applied to the scan electrodes Y within a period when the square wave of the sustain voltage is applied to the sustain electrode Z. This is to prevent noise that may be generated by the interaction between the square wave and the first Y negative ramp waveform NRY1 by applying the first Y negative ramp waveform NRY1 while the square wave is being applied. The first Y negative ramp waveform NRY1 is a waveform in which the voltage across the scan electrodes Y is lowered from 0 V or the base voltage reference voltage GND to the negative -V1 voltage. The negative -V1 voltage will be described later. It is higher than the negative -V2 voltage level of the second Y negative ramp waveform NRY2 to be applied to the scan electrodes Y. Preferably, it may be set equal to the negative -V2 voltage level of the second Y negative ramp waveform NRY2. In this case, since the same voltage source can be used for the voltage source according to the voltage level of the first Y negative ramp waveform NRY1 and the second Y negative ramp waveform NRY2, cost reduction can be obtained. In addition, the voltage of the square wave applied to the sustain electrodes Z is greater than the bias voltage VZb applied to the sustain electrodes Z in an address section to be described later. 0 V is applied to the address electrodes X during the pre-reset period PRERP. The positive sustain voltage Vs supplied to the sustain electrode Z and the first Y negative ramp waveform NRY1 supplied to the scan electrode Y are the scan electrodes Y and the sustain electrodes in all discharge cells. A dark discharge is generated between Z) and between the sustain electrodes Z and the address electrodes X. FIG. As a result of this discharge, immediately after the pre-reset period PRERP, all discharge cells are initialized to the wall charge distribution as shown in Fig. 7A. In the setup period SU of the reset period RP, the first Y positive ramp waveform PRY1 and the second Y positive ramp waveform PRY2 are successively applied to all the scan electrodes Y, and the sustain electrodes Z are applied. ) And address electrodes X are applied with 0 [V]. The voltage of the first Y positive ramp waveform PRY1 rises from 0V to the positive sustain voltage Vs, and the voltage of the second Y positive ramp waveform PRY2 is higher than the positive sustain voltage Vs. The voltage rises to the Y reset voltage Vry. The slopes of the first and second Y positive ramp waveforms PRY1 and PRY2 are the same. The scan electrodes Y and the sustain in all the discharge cells are added as the first Y positive ramp waveform PRY1 and the voltage of the electric field formed between the scan electrodes Y and the sustain electrodes Z in the discharge cell are added. Dark discharge is generated between the electrodes Z and between the scan electrodes Y and the address electrodes X. FIG. As a result of this discharge, immediately after the setup period SU, all the discharge cells accumulate wall charges in the wall charge distribution as shown in FIG. 7B. In the set-down period SD of the reset period RP, the second Y negative ramp waveform NRY2 is applied to the scan electrodes Y and the square wave positive sustain voltage of the Z bias voltage Vzb is applied to the sustain electrodes Z. (Vs) is supplied. The second Z negative ramp waveform NRZ2 is applied. The voltage of the second Y negative ramp waveform NRY2 is lowered from the positive sustain voltage Vs to the negative -V2 voltage. During this set-down period SD, dark discharge occurs intensively between the scan electrodes Y and the sustain electrodes Z with the help of the wall charges of the previous subfield accumulated in the discharge cells in the pre-reset period. As a result of this dark discharge, the discharge cells are initialized to the wall charge distribution as shown in Fig. 7C. In the address period AP, the negative scan pulse -SCNP is sequentially applied to the scan electrodes Y, and the positive data pulses are applied to the address electrodes X in synchronization with the scan pulse -SCNP. DP) is applied. During this address period (AP), the sustain electrodes Z are supplied with a positive Z bias voltage Vzb lower than the positive sustain voltage Vs. Immediately after the reset period RP, in a state where the gap voltage is adjusted to the address optimum condition, the scan electrodes V and the address are in the on cells to which the scan voltage Vsc and the data voltage Va are applied. The address discharge occurs only between the electrodes Y and X while the gap voltage between the electrodes X exceeds the discharge ignition voltage Vf. The wall charge distribution in the on cells where the address discharge is generated is shown in FIG. 7D. Immediately after the address discharge occurs, the wall charge distribution in the on-cells changes as shown in FIG. 7E as the positive wall charges are accumulated on the scan electrodes Y and the negative wall charges are accumulated on the address electrodes X by the address discharge. . The sustain period SP is substantially the same as in the above-described embodiment.

FIG. 16 is a waveform diagram illustrating a method of driving a plasma display device according to a third exemplary embodiment of the present invention. FIG. 16 is a view illustrating driving of a subfield applied to the second to nth subfields where n is a positive integer of 2 or more. Waveform. Referring to FIG. 16, the driving method of the plasma display device according to the present invention does not allocate a separate pre-reset period, and scans a voltage lowered from 0 V or the base voltage reference voltage GND during the set-down period SD. Is applied to (Y) and the voltage on the sustain electrodes Z is maintained at 0V or the ground voltage reference voltage (GND). There is no erase discharge between the sustain period of the n-th subfield and the pre-reset period PRER of the n-th subfield. In each of the second to nth subfields SFn2 and SFn, the second Y negative ramp waveform NRY2 is supplied to the scan electrodes Y in the setdown period SD of the reset period RP, and the sustain electrodes The base voltage reference voltage GND or 0V is supplied to the Z and the address electrodes X. The setup period SU, the address period AP, and the sustain period SP are substantially the same as the embodiment of FIG. 8, and thus detailed description thereof is omitted. The reset voltage Vry of the setup period SU is set to a voltage lower than that of the first subfield because more wall charges are accumulated in the discharge cells than the first subfield. The voltage of the second Y negative ramp waveform NRY2 is lowered from 0 V or the base voltage reference voltage GND to the negative -V2 voltage, unlike the above-described embodiments, to reduce the set down period. During this set-down period SD, dark discharge is generated between the scan electrodes Y and the address electrodes X with the help of the wall charges on the address electrodes X accumulated by the sustain discharge of the previous subfield. The dark discharge erases the excess wall charges among the negative wall charges accumulated on the scan electrodes Y, and the excess wall charges among the positive wall charges accumulated on the address electrodes X. When the voltage of the second Y negative ramp waveform NRY2 is lowered from 0 V or the base voltage reference voltage, the set-down period SD is shorter than in the above-described embodiments. In addition, since the voltage difference between the scan electrodes Y and the sustain electrodes Y is small even when the voltage of the second Y negative ramp waveform NRY2 is lowered from 0 V or the base voltage reference voltage, the plasma display device of this embodiment scans. The initialization can be made more stable while more effectively suppressing the discharge between the electrodes Y and the sustain electrodes Z. FIG. Therefore, in this embodiment, the driving time can be further secured due to the reduction of the set down period SD, and the initialization operation of the set down period SD is made more stable.

15 and 16, since the ramp waveform is not supplied to the sustain electrode Z, the sustain driving circuit of FIG. 15 and FIG. 16 may be implemented by using the existing sustain electrode driving circuit as it is and only controlling timing. Therefore, the sustain driving circuit in this embodiment has no increase in circuit cost. Meanwhile, in order to use the wall charges on the address electrodes X accumulated by the sustain discharge of the previous subfield, between the sustain period of the last subfield of the previous frame and the prereset period PREPR of the first subfield of the current frame. There is no erase discharge, and there is no erase discharge between the sustain period SP of the first subfield and the setup period SU of the next subfield.

FIG. 17 shows an example in which a driving waveform during one frame period is applied to the driving waveforms of FIGS. 15 and 16.

18 is a waveform diagram illustrating a method of driving a plasma display device according to a fourth embodiment of the present invention. Referring to FIG. 18, the driving method of the plasma display device according to the present invention applies the ramp waveform only to the sustain electrodes Z during the pre-reset period PRERP. In this embodiment, since the reset period RP, the address period AP, and the sustain period SP are substantially the same as those of the embodiment of FIG. 6, detailed description thereof will be omitted. In the pre-reset period PRERP, a Z positive ramp waveform PRZ is applied to all of the sustain electrodes Z with the voltage rising from the positive sustain voltage Vs to the positive Z reset voltage Vrz. During this pre-reset period PRERP, 0 V or the ground voltage reference voltage GND is applied to the scan electrodes Y and the address electrodes X. FIG. The Z positive ramp waveform PRZ causes dark discharge between the scan electrodes Y and the sustain electrodes Z and between the sustain electrodes Z and the address electrodes X in all the discharge cells. As a result of this discharge, positive wall charges are accumulated on the scan electrodes Y in all the discharge cells immediately after the pre-reset period PRERP, and a large amount of negative wall charges are accumulated on the sustain electrodes Z. . Positive wall charges are accumulated on the address electrodes X. The discharge of the pre-reset period RERP and its effect are similar to those of the embodiment of FIG. 6 described above. Accordingly, this embodiment has an advantage of easier control of the scan electrode driving circuit because a ramp waveform is applied only to the sustain electrodes Z while having a discharge effect of the pre-reset period PRERP compared to the embodiment of FIG. 6.

19 is a waveform diagram illustrating a method of driving a plasma display device according to a fifth embodiment of the present invention. Referring to FIG. 19, the driving method of the plasma display device according to the present invention applies the ramp waveform only to the scan electrodes Y during the pre-reset period PRERP. In this embodiment, since the reset period RP, the address period AP, and the sustain period SP are substantially the same as those of the embodiment of FIG. 6, detailed description thereof will be omitted. In the pre-reset period PRERP, the first Y negative ramp waveform NRY1 is applied to all of the scan electrodes Y from 0 V or the base voltage reference voltage GND to the negative -V1 voltage. During the pre-reset period PRERP, 0 V or the ground voltage reference voltage GND is applied to the sustain electrodes Z and the address electrodes X. The first Y negative ramp waveform NRY1 causes dark discharge between the scan electrodes Y and the sustain electrodes Z and between the sustain electrodes Z and the address electrodes X in all the discharge cells. . As a result of this discharge, positive wall charges are accumulated on the scan electrodes Y in all the discharge cells immediately after the pre-reset period PRERP, and negative wall charges are accumulated on the sustain electrodes Z. Positive wall charges are accumulated on the address electrodes X. The discharge of the pre-reset period RERP and its effect are similar to those of the embodiment of FIG. 6 described above. Therefore, this embodiment has the advantage of easier control of the sustain electrode driving circuit because the lamp waveform is applied only to the scan electrodes Y while the discharge effect of the pre-reset period PRERP is compared with the embodiment of FIG. 6. The driving waveforms of FIGS. 18 and 19 are not limited to only the first subfield, but may be applied to several initial subfields including the first subfield as in the embodiment of FIG. 6 and included in one frame period. It may be applied to all subfields. 8, the pre-reset period PRER may be omitted in the second and subsequent subfields.

20 shows driving waveforms of the first subfield period in the plasma display device driving method according to the sixth embodiment of the present invention. 21 shows a sustain period SP and an nth subfield of an n-1 (where n is a positive integer of 2 or more) th subfield SFn in the method of driving a plasma display device according to the sixth embodiment of the present invention. The driving waveform during (SFn) is shown. 20 and 21, in the method of driving the plasma display device according to the present invention, each of the subfields scans a voltage lowered from 0 V or the base voltage reference voltage GND during the setdown period SD. ) To uniformize the wall charge distribution of all discharge cells initialized in the setup period SU.

The first subfield includes a pre-reset period PRERP, a reset period RP, an address rejection AP, and a sustain period SP as shown in FIG. 20, and the other subfields SFn are shown in FIG. 201. The reset period RP, the address rejection period AP, and the sustain period SP are included. That is, the pre-reset period PRER may be omitted in the subfields other than the first.

The operations of the pre-reset period PRERP, the setup period SU, the address period AP, and the sustain period SP are substantially the same as those of the above-described embodiments. In the set-down period SD of the reset period RP in each of the subfields SFn-1 and SFn, the second Y negative ramp waveform NRY2 is applied to the scan electrodes Y and the sustain electrodes Z are applied. Is applied to the second Z negative ramp waveform NRZ2. Unlike the above-described embodiments, the voltage of the second Y negative ramp waveform NRY2 is lowered from 0V or the base voltage reference voltage GND to a negative -V2 voltage. The voltage of the second Z negative ramp waveform NRZ2 is lowered from the positive sustain voltage Vs to 0 V or the base voltage reference voltage. During this set-down period SD, the voltages of the scan electrodes Y and the sustain electrodes Z decrease at the same time so that no discharge occurs between them, while between the scan electrodes Y and the address electrodes X. Dark discharge occurs. The dark discharge erases the excess wall charges among the negative wall charges accumulated on the scan electrodes Y, and the excess wall charges among the positive wall charges accumulated on the address electrodes X. When the voltage of the second Y negative ramp waveform NRY2 is lowered from 0 V or the base voltage reference voltage, the set-down period SD is shorter than in the above-described embodiments. In addition, since the voltage difference between the scan electrodes Y and the sustain electrodes Y is small even when the voltage of the second Y negative ramp waveform NRY2 is lowered from 0 V or the base voltage reference voltage, the plasma display device of this embodiment scans. The initialization can be made more stable while more effectively suppressing the discharge between the electrodes Y and the sustain electrodes Z. FIG. Therefore, in this embodiment, the driving time can be further secured due to the reduction of the set down period SD, and the initialization operation of the set down period SD is made more stable. Fig. 22 shows driving waveforms of the first subfield period in the plasma display device driving method according to the seventh embodiment of the present invention. FIG. 23 shows driving waveforms during the sustain period SP of the n-1 th subfield SFn and the n th subfield SFn in the driving method of the plasma display device according to the seventh embodiment of the present invention. 22 and 23, in the method of driving the plasma display device according to the present invention, each of the subfields scans a voltage lowered from 0 V or the base voltage reference voltage GND during the setdown period SD. ) And maintains the voltage on the sustain electrodes Z at 0 V or the ground voltage reference voltage GND to uniform the wall charge distribution of all discharge cells initialized in the setup period SU. The first subfield includes a pre-reset period PRERP, a reset period RP, an address delay period AP, and a sustain period SP as shown in FIG. 22, and the other subfields SFn are shown in FIG. The reset period RP, the address rejection period AP, and the sustain period SP are included. In other words, the pre-reset interval PRERE may be omitted in the subfields other than the first. The operations of the pre-reset period PRERP, the setup period SU, the address period AP, and the sustain period SP are substantially the same as those of the above-described embodiments of FIGS. 20 and 21.

22 and 23, in the method of driving the plasma display device according to the present invention, a voltage lowered at OV or reference voltage GND is applied to the scan electrode Y during the set down period SD. The voltage on the sustain electrode Z is maintained at OV or reference voltage GND. There is no erase discharge during the sustain period of the n-1 (n is 2 or more) subfield and the pre-reset period PREPR of the nth subfield.

In each subfield, the second Y negative ramp waveform NRY2 is applied to the scan electrode Y in the set down period SD of the reset period RP. The voltage of the second Y negative ramp waveform NRY2 is lowered from OV and reference voltage GND to a negative V2 voltage. In the second and subsequent subfields, the arm between the scan electrode Y and the address electrode X is assisted by the wall charges on the address electrode X accumulated by the sustain discharge of the previous subfield during the set down period SD. Discharge is generated. This dark discharge erases the transient wall charges from the negative wall charges accumulated on the scan electrode Y, and erases the transient wall charges from the positive wall charges accumulated on the address electrode X. In the first subfield, during the set down period SD, dark discharge occurs between the scan electrode and the address electrode with the help of the wall charges accumulated on the address electrode X in the pre-reset period PRERP. . This dark discharge erases excess wall charges among the negative wall charges on the scan electrode, and erases excessive wall charges among the positive wall charges on the address electrode. The second Y negative ramp waveform NRY2 is applied to the scan electrodes Y in the setdown period SD of the reset period RP in the SFn-1 and SFn. During this set down period SD, 0 V or the ground voltage GND is applied to the sustain electrodes Z and the address electrodes X. The voltage of the second Y negative ramp waveform NRY2 is lowered from 0V or the base voltage GND to the negative -V2 voltage. During this set-down period SD, the voltages of the scan electrodes Y and the sustain electrodes Z decrease at the same time so that no discharge occurs between them, while between the scan electrodes Y and the address electrodes X. Dark discharge occurs. The dark discharge erases the excess wall charges among the negative wall charges accumulated on the scan electrodes Y, and the excess wall charges among the positive wall charges accumulated on the address electrodes X.

When the voltage of the second Y negative ramp waveform NRY2 is lowered from 0 V or the base voltage reference voltage, the set-down period SD is shortened as compared with the above-described embodiments. In addition, since the voltage difference between the scan electrodes Y and the sustain electrodes Y is small even when the voltage of the second Y negative ramp waveform NRY2 is lowered from 0 V or the base voltage reference voltage, the plasma display device of this embodiment scans. The initialization can be made more stable while more effectively suppressing the discharge between the electrodes Y and the sustain electrodes Z. FIG. In addition, in this embodiment, since the ramp waveform is applied only to the scan electrodes Y during the setdown period SD, the control of the sustain electrode driving circuit is easier than in the embodiment of FIGS. 20 and 21. Therefore, in this embodiment, the driving time can be further secured due to the reduction of the setdown period SD, and the control of the sustain electrode driving circuit is easier.

24 shows driving waveforms of a first subfield period in the plasma display device driving method according to the eighth embodiment of the present invention. FIG. 25 shows the sustain period SP of the n-1 th subfield SFn and the driving waveform of the n th subfield SFn in the method of driving a plasma display device according to the eighth embodiment of the present invention. 24 and 25, in the method of driving the plasma display device according to the present invention, each of the subfields applies a positive bias voltage to the address electrodes X during the setdown period SD.

The first subfield includes a pre-reset period PRERP, a reset period RP, an address rejection AP, and a sustain period SP as shown in FIG. 24, and the other subfields SFn are shown in FIG. Similarly, the reset period RP, the address rejection AP, and the sustain period SP are included. That is, the pre-reset period PRERP may be omitted in the subfields other than the first.

The operations of the pre-reset period PRERP, the setup period SU, the address period AP, and the sustain period SP are substantially the same as in the above-described embodiment of FIG. In the set-down period SD of the reset period RP in each of the subfields SFn-1 and SFn, the second Y negative ramp waveform NRY2 is applied to the scan electrodes Y and the sustain electrodes Z are applied. Is applied to the second Z negative ramp waveform NRZ2. The voltage of the second Y negative ramp waveform NRY2 is lowered from the positive sustain voltage Vs to the negative -V2 voltage. In addition, the voltage of the second Y negative ramp waveform NRY2 may be lowered from 0 V or the base voltage reference voltage as in the embodiment of FIGS. 20 to 23. The voltage of the second Z negative ramp waveform NRZ2 is lowered from the positive sustain voltage Vs to 0 V or the base voltage reference voltage. During this set down period SD, the positive bias voltage is supplied to the address electrodes X. FIG. For example, the same voltage as the data voltage Va may be supplied to the address electrodes X with a positive bias voltage. Since the voltages of the scan electrodes Y and the sustain electrodes Z are simultaneously lowered, no discharge occurs between them, while dark discharge is generated between the scan electrodes Y and the address electrodes X. FIG. The positive bias voltages of the address electrodes X increase the voltage difference between the address electrodes X and the scan electrodes Y, so that dark discharge can occur more quickly during the erasing period SD. Even if the discharge time is long, dark discharge occurs once in all the discharge cells even when the discharge characteristic variation in each discharge cell is severe, thereby increasing the uniformity of the wall charge distribution in all the discharge cells. Meanwhile, the driving waveforms of FIGS. 20, 22, and 24 are not limited to the first subfield but may be applied to several initial subfields including the first subfield, and all subfields included in one frame period. It may be applied to these fields.

26 is a waveform diagram illustrating a method of driving a plasma display device according to a ninth embodiment of the present invention. Referring to FIG. 26, the driving method of the plasma display device according to the present invention maintains the voltages of the sustain electrodes Z as the base voltage reference voltage during the reset period RP. In this embodiment, the preset period PRERE, the setup period SU of the reset period RP, the address period AP, and the sustain period SP are substantially the same as the above-described embodiment, and thus detailed description thereof is omitted. Let's do it. Meanwhile, only the sustain voltage Vs may be supplied to the sustain electrode Z without the Z positive ramp waveform PRZ in the preset period PRERP. During the set down period SD of the reset period RP, the second Y negative ramp waveform NRY2 is applied to the scan electrodes Y and the ground voltage reference voltage GND is applied to the sustain electrodes Z. . During this set down period SD, dark discharge is generated between the scan electrodes Y and the address electrodes X. FIG. The dark discharge erases the excess wall charges among the negative wall charges accumulated on the scan electrodes Y, and the excess wall charges among the positive wall charges accumulated on the address electrodes X. As a result, all the discharge cells have a uniform wall charge distribution under the address optimum condition. This embodiment induces dark discharge generated during the setdown period SD only between the scan electrode Y and the address electrode X. FIG. As a result, the address discharge occurs only between the scan electrode Y and the address electrode X due to the wall charge distribution in the discharge cell formed by the discharge in the setdown period SD, thereby reducing the time required for the address. Detailed description thereof will be described in detail with reference to FIGS. 26 to 29.

6, 7, 18 and 26, during the address period (AP), the positive electrode Z bias voltage Vzb supplied to the sustain electrodes Z has the address discharge scan electrode Y and the sustain electrode. It is lower than the sustain voltage Vs and the scan voltage Vsc so that it can occur only between the address electrodes XZ.

27 shows a part of a driving waveform applied to subfields other than the first subfield in the driving waveform of the plasma display device according to the ninth embodiment of the present invention. 28A to 28D are diagrams showing the wall charge distribution in the discharge cells that are changed by the driving waveform of FIG. 27 step by step. Referring to FIG. 27, when the last sustain pulse LSTSUSP having a wide pulse width is applied to the sustain electrodes Z in the previous subfield, the scan electrodes Y and the sustain may be applied. Sustain discharge occurs between the electrodes Z. Due to this last sustain discharge, the positive wall charges on the scan electrodes Y, the negative wall charges on the sustain electrodes Z, and the positive wall on the address electrodes X are shown in FIG. 27A. An electric charge is formed. In the setup period SU of the reset period RP, the first Y positive ramp waveform PRY1 and the second Y positive ramp waveform PRY2 are successively applied to all the scan electrodes Y, and the sustain electrodes Z are applied. ) And address electrodes X are applied with 0 [V]. The voltage of the first Y positive ramp waveform PRY1 rises from 0V to the positive sustain voltage Vs, and the voltage of the second Y positive ramp waveform PRY2 is higher than the positive sustain voltage Vs. The voltage rises to the Y reset voltage Vry. The positive Y reset voltage Vry is a voltage less than or equal to the positive Z reset voltage Vrz, and is determined as a voltage between the positive Z reset voltage Vrz and the positive sustain voltage Vs. The slope of the second Y positive ramp waveform PRY2 is lower than the first Y positive ramp waveform PRY1. The scan electrodes Y and the sustain electrodes in all the discharge cells are added as the voltage of the electric field formed between the scan electrodes Y and the sustain electrodes Z is added to the first Y positive ramp waveform PRY1 and the discharge cells. Dark discharge is generated between the electrodes Z and between the scan electrodes Y and the address electrodes X. FIG. As a result of this discharge, immediately after the set-up period SU, in all the discharge cells, the scan electrodes Y on the vicinity of the gap between the scan electrodes Y and the sustain electrodes Z, as shown in FIG. As the negative wall charges are accumulated in the polarity, the polarity is reversed from the positive to the negative polarity, and the positive wall charges are further accumulated on the address electrodes X. The wall charges accumulated on the sustain electrodes Z are reduced in the amount of negative wall charges toward the scan electrodes Y, but the polarities thereof remain negative.

Following the setup period SU, in the set down period SD of the reset period RP, the second Y negative ramp waveform NRY2 is applied to the scan electrodes Y, and the sustain electrodes Z and the address electrodes are simultaneously applied. Ground voltage reference voltage (GND) or 0V. The voltage of the second Y negative ramp waveform NRY2 is lowered from the positive sustain voltage Vs to the negative -V2 voltage. In the set down period SD to which the driving voltages are applied, since the dark discharge accumulates the positive wall charges on the address electrodes X, only between the scan electrodes Y and the address electrodes X as shown in FIG. 28C. Is generated. The dark discharge erases the excess wall charges among the negative wall charges accumulated on the scan electrodes Y, and the excess wall charges among the positive wall charges accumulated on the address electrodes X. As a result, all the discharge cells have a uniform wall charge distribution under the address optimum condition as shown in FIG. 28C.

In the address period AP, the negative scan pulse -SCNP is sequentially applied to the scan electrodes Y, and the positive data pulses are applied to the address electrodes X in synchronization with the scan pulse -SCNP. DP) is applied. The voltage of the scan pulse (-SCNP) is the scan voltage (Vsc) lowered from the negative scan bias voltage (Vyb) of 0 V or close thereto to the negative scan voltage (-Vy). The voltage of the data pulse DP is the positive data voltage Va. During this address period (AP), the sustain electrodes Z are supplied with a positive Z bias voltage Vzb that is lower than the scan voltage Vsc and lower than the positive sustain voltage Vs. Immediately after the reset period RP, in a state where the gap voltage is adjusted to the address optimum condition, the scan electrodes V and the address are in the on cells to which the scan voltage Vsc and the data voltage Va are applied. The address discharge occurs only between the electrodes Y and X while the gap voltage between the electrodes X exceeds the discharge ignition voltage Vf. Here, the address discharge is generated between one side of the scan electrode Y and the address electrode X in the vicinity of the gap between the scan electrode Y and the sustain electrode Z, so that the discharge delay time is shortened. The wall charge distribution in the on cells during the address discharge changes as shown in FIG. 278D.

On the other hand, the gap voltage is less than the discharge ignition voltage for off-cells in which 0 V or a base voltage reference voltage is applied to the address electrodes X or 0 V or a scan bias voltage Vyb is applied to the scan electrodes Y. Thus, the off-cells in which the address discharge has not occurred have their wall charge distribution substantially maintained in the state of Fig. 28C.

Since the sustain period SP is substantially the same as the above-described embodiments, a detailed description thereof will be omitted.

FIG. 29 illustrates that the positive sustain voltage (Vs) is 80 V, the positive Y reset voltage (Vry) is 180 V, the negative scan bias voltage (-Vy) is 200 V, and the Z bias voltage (Vzb) is 100 V in the driving waveform of FIG. 27. In this case, the external applied voltage difference between the scan electrode Y and the sustain electrode Z and the discharge cell gap voltage between the scan electrode Y and the sustain electrode Z are shown. In FIG. 29, "VYZf" and "VZYf" are discharge ignition voltages between the scan electrode Y and the sustain electrode Z. In FIG.

FIG. 30 illustrates that the positive sustain voltage (Vs) is 80V, the positive Y reset voltage (Vry) is 180V, the negative scan bias voltage (-Vy) is 200V, and the Z bias voltage (Vzb) is 100V in the driving waveform of FIG. In this case, the external applied voltage difference between the scan electrode Y and the address electrode X and the discharge cell gap voltage between the scan electrode Y and the address electrode X are shown. In Fig. 30, "VYXf" and "VXYf" are discharge ignition voltages between the scan electrode Y and the address electrode X.

31 shows a portion of a driving waveform applied to subfields other than the first subfield in the driving waveform of the plasma display device according to the tenth embodiment of the present invention. Referring to FIG. 31, in the driving method of the plasma display device according to the present invention, there is no erase discharge between the sustain period SP and the reset period RP, and the address electrode is caused by the sustain discharge generated in the previous subfield every subfield. The positive wall charges accumulated in the wall cause set-down discharge and address discharge. The plasma display device driving method according to the present invention maintains the voltage of the sustain electrode (Z) at the ground voltage reference voltage (GND) or 0V during the set-down period (SD) and the wall on the address electrode (X) stacked in the previous subfield. By using electric charges, the set-down discharge and the address discharge are caused only between the scan electrode Y and the address electrode X. Further, in the plasma display device according to the present invention, since the wall charges are sufficiently accumulated in each discharge cell before the setup period SD, the reset voltage Vry in the subfields SF2 to SFn other than the initial subfield SF1. Can be lowered. In addition, the subfields SF2 to SFn other than the initial subfield SF1 may generate a setup discharge in all the discharge cells with only the sustain voltage Vs without raising the voltage to the reset voltage Vry. As a result of applying the drive waveform of FIG. 31 to the PDP, it was confirmed that the address discharge delay value, i.e., the jitter value, is significantly shortened to the next subfield. In the first subfield of FIG. 31, similarly to FIG. 15, during the pre-reset period PRERP, the first Y-negative ramp waveform NRY1 is applied to the scan electrode, and the positive bias voltage VS ( Square wave) is applied. In addition, in the setup period SU of the reset period RP, the first Y positive ramp waveform PRY1 and the second Y positive ramp waveform PRY2 are successively applied to the scan electrode, and then the set down period SD is applied. In this case, the second negative ramp waveform NRY2 is applied. However, in this embodiment, the sustain electrode is kept at 0 V or the reference voltage in the set down period SD.

32 is a block diagram illustrating a plasma display device according to an exemplary embodiment of the present invention. Referring to FIG. 32, a plasma display device according to an exemplary embodiment of the present invention includes a PDP 180, a data driver 182 for supplying data to address electrodes X1 to Xm of the PDP 180, and a PDP. A scan driver 183 for driving the scan electrodes Y1 to Yn of 180, a sustain driver 184 for driving the sustain electrodes Z of the PDP 180, and each driver 182. A timing controller 181 for controlling the 183 and 184 and a driving voltage generator 185 for generating the driving voltage required for each of the driving units 182, 183 and 184 are provided.

The data driver 182 is subjected to inverse gamma correction and error diffusion by an inverse gamma correction circuit, an error diffusion circuit, and the like, and then data mapped to a subfield pattern preset by the subfield mapping circuit is supplied. As shown in Figs. 6, 8, 14 to 26, 27, and 31, the data driver 182 has 0 V or a base voltage in the pre-reset period PRERP, reset period RP, and sustain period SP. The reference voltage is applied to the address electrodes X1 to Xm. In addition, the data driver 182 applies the positive bias voltage from the driving voltage generator 185, for example, the data voltage Va, in the set down period SD of the reset period RP as shown in FIGS. 24 and 25. It may be supplied to the address electrodes X1 to Xm. In addition, the data driver 182 samples and latches data under the control of the timing controller 181, and then supplies the data to the address electrodes X1 to Xm during the address period AP.

The scan driver 183 is configured to discharge all cells in the pre-reset period PRERP and the reset period RP as shown in FIGS. 6, 8, 14 to 26, 27, and 31 under the control of the timing controller 181. After the ramp waveforms NRY1, PRY1, PRY2, and NRY2 are supplied to the scan electrodes Y1 to Yn to initialize them, the scan pulse SCNP is used to select a scan line to which data is supplied in the address period AP. Are sequentially supplied to the scan electrodes Y1 to Yn. In addition, the scan driver 183 supplies the sustain pulses FSTSUSP and SUSP to the scan electrodes Y1 to Yn in order to enable sustain discharge to occur in the selected on cells during the sustain period SP.

The sustain driver 184 controls all the discharge cells in the pre-reset period PRERP and the reset period RP as shown in FIGS. 6, 8, 14-26, 27, and 31 under the control of the timing controller 181. After the ramp waveforms PRZ, NRZ1 and NRZ2 are supplied to the sustain electrodes Z to initialize the signals, the Z bias voltage Vzb is supplied to the sustain electrodes Z in the address period AP. The sustain driver 184 alternately operates with the scan driver 183 in the sustain period SP to supply the sustain pulses FSTSUSP, SUSP, and LSTSUSP to the sustain electrodes Z.

The timing controller 181 receives the vertical / horizontal synchronization signal and the clock signal to generate the timing control signals CTRX, CTRY, and CTRZ required for each of the driving units 182, 183, and 184, and the timing control signals CTRX, CTRY, Each drive unit 182, 183, 184 is controlled by supplying CTRZ to the drive units 182, 183, 184. The timing control signal CTRX supplied to the data driver 182 includes a sampling clock for latching data, a latch control signal, a switch control signal for controlling the on / off time of the energy recovery circuit and the driving switch element. The timing control signal CTRY applied to the scan driver 183 includes a switch control signal for controlling on / off time of the energy recovery circuit and the driving switch element in the scan driver 183. The timing control signal CTRZ applied to the sustain driver 184 includes a switch control signal for controlling on / off time of the energy recovery circuit and the driving switch element in the sustain driver 184.

The driving voltage generator 185 may include driving voltages supplied to the PDP 180, that is, Vry, Vrz, Vs, -V1, shown in FIGS. 6, 8, 14 to 26, 27, and 31. -V2, -Vy, Va, Vyb, Vzb and so on. On the other hand, these driving voltages may vary depending on the discharge characteristics or the discharge gas composition that varies depending on the resolution, model, etc. of the PDP 180.

 As described above, it will be understood by those skilled in the art that the above-described technical configuration may be implemented in other specific forms without changing the technical spirit or essential features of the present invention. Therefore, the above-described embodiments are to be understood as illustrative and not restrictive in all respects, and the scope of the present invention is indicated by the appended claims rather than the detailed description, and the meaning and scope of the claims and All changes or modifications derived from the equivalent concept should be interpreted as being included in the scope of the present invention.

As described above, the plasma display device and the driving method thereof according to the present invention sufficiently accumulate positive wall charges on the scan electrodes in the discharge cells and initialize the negative wall charges sufficiently on the sustain electrodes before initializing the discharge cells. By stacking it can prevent mis-discharge, miss discharge and abnormal discharge, reduce the number of discharges generated during the initialization process to increase the darkroom contrast and increase the operating margin. Furthermore, the driving time can be secured by reducing the setdown period by lowering the voltage of the negative ramp waveform generated during the setdown period from 0 V or the base voltage reference voltage according to the present invention, and applying a positive bias voltage to the address electrode during the setdown period. As a result, the discharge time of the dark discharge generated between the scan electrode and the address electrode is lengthened, so that the wall charge distribution in all the discharge cells can be made uniform.

In addition, the plasma display device and the driving method thereof according to the present invention form a sufficient wall charge in the discharge cells before the reset period so that all the discharge cells can be set up and discharged within the sustain voltage, thereby reducing the reset voltage required for the setup operation. have. In addition, the plasma display device and the driving method thereof according to the present invention can shorten the time required for address discharge by inducing discharge only between the scan electrode and the address electrode during the set-down period and the address period.

Claims (14)

A surface discharge electrode pair including a first electrode and a second electrode, a third electrode intersecting the surface discharge electrode pair, and a plurality of discharge cells disposed at an intersection of the surface discharge electrode pair and the third electrode; In the plasma display device, An electrode pair driver for driving the surface discharge electrode pairs; In the pre-reset period prior to the reset period for initializing the discharge cells, the electrode pair driver applies a first waveform to the first electrode and a second waveform of reverse polarity to the first waveform to the second electrode. Is authorized, In the reset period, the electrode pair driver applies a first ramp waveform having a polarity opposite to that of the first waveform to the first electrode, and the first pair of charges accumulated in the surface discharge electrode pair during the preset period. And discharging the discharge cells while maintaining the polarity of the charges on the two electrodes. A first substrate comprising at least one electrode, A second substrate comprising at least one electrode, A plurality of discharge cells provided between the first substrate and the second substrate, In the pre-reset period prior to the reset period for initializing the discharge cells, the electrode pair driver applies a first waveform to the first electrode and a second waveform of reverse polarity to the first waveform to the second electrode. Is authorized, And a reference voltage is applied to the second electrode during a reset period of initializing the discharge cells. The plasma display device of claim 2, wherein the reference voltage is 0V or a ground level voltage. A plasma display device comprising a first substrate including at least one first and second electrodes, a second substrate including at least one electrode, and a plurality of discharge cells provided between the first substrate and the second substrate. In the driving method of, Applying a first waveform to the first electrode in a pre-reset period prior to a reset period for initializing the discharge cells; In the reset period, at least one of the charges accumulated in the first and second electrodes in the pre-reset period by applying a first ramp waveform having a polarity opposite to that of the first waveform, is the polarity of the charge. And initializing the discharge cells while maintaining the state. A driving method of a plasma display device having a first substrate and a second substrate including at least one electrode and a plurality of discharge cells provided between the first substrate and the second substrate. Applying a first waveform to the first electrode and a second waveform having a reverse polarity to the first waveform to the second electrode in a pre-reset period prior to the reset period for initializing the discharge cell, And a reference voltage is applied to the second electrode during the reset period of initializing the discharge cells. The method of claim 5, The reference voltage is a driving method of the plasma display device, characterized in that 0V or ground (GND) level voltage. delete delete delete delete delete delete delete delete

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