KR100656710B1 - Plasma display apparatus and driving method thereof - Google Patents

Abstract

A plasma display device and a driving method thereof are provided to improve a spot of a monochromatic pattern and to prevent complementary afterimage. A plasma display device includes a plasma display panel(400) having a plurality of sustain electrode pairs including scan electrodes(Y1~Yn) and sustain electrodes(Z); a driving unit(430) for driving the sustain electrode pairs; and a driving pulse control unit(440) for controlling the driving unit to apply set-down pulse to the scan electrode after applying falling pulse, during a reset period and apply positive pulse to the sustain electrode while applying the falling pulse. The voltage level of the falling pulse is 10~50V, and the width of the falling pulse is 10~30mus.

Description

Plasma Display Apparatus and Driving Method Thereof

1 illustrates a structure of a general plasma display panel.

2 is a diagram illustrating a method of implementing an image of a conventional plasma display apparatus.

3A is a view showing a driving waveform of a conventional plasma display device.

3B is a diagram for explaining wall charges distributed in a discharge cell according to a conventional driving waveform.

4 is a view for explaining the structure of a plasma display device according to an embodiment of the present invention.

5A is a view showing a driving waveform of the plasma display device according to an embodiment of the present invention.

5B is a view for explaining wall charges distributed in a discharge cell according to a driving waveform according to an embodiment of the present invention.

6 is a waveform diagram illustrating a relationship between a setup pulse and a falling pulse according to an embodiment of the present invention.

7 is a view showing a modified waveform of the plasma display device according to an embodiment of the present invention.

8 is a waveform diagram illustrating a waveform including a pre-reset pulse according to an embodiment of the present invention.

***** Explanation of symbols for main parts of drawing *****

400; Plasma display panel 410; Data driver

420; A scan driver 430; Sustain drive

440; A driving pulse controller 450; Drive voltage generator

The present invention relates to a plasma display device, and more particularly, to a plasma display device and a driving method thereof capable of preventing afterimage erroneous discharge generated during driving.

In general, a plasma display device includes a plasma display panel in which a partition wall formed between a front substrate and a rear substrate forms one unit cell. Each cell is filled with a main discharge gas such as neon (Ne), helium (He) or a mixture of neon and helium (Ne + He) and an inert gas containing a small amount of xenon. When discharged by a high frequency voltage, the inert gas generates vacuum ultraviolet rays and emits phosphors formed between the partition walls to realize an image. Such a plasma display device has a spotlight as a next generation display device because of its thin and light configuration.

1 illustrates a structure of a general plasma display panel.

As shown in FIG. 1, a plasma display panel includes a front substrate in which a plurality of sustain electrode pairs formed by pairing a scan electrode 102 and a sustain electrode 103 are formed on a front glass 101, which is a display surface on which an image is displayed. A rear substrate 110 having a plurality of address electrodes 113 arranged so as to intersect the plurality of sustain electrode pairs on the back glass 111 forming the back surface 100 and the rear surface is coupled in parallel with a predetermined distance therebetween. .

The front substrate 100 may include a scan electrode 102 and a sustain electrode 103, that is, a transparent electrode a made of a transparent indium thin oxide (ITO) material for mutual discharge in one discharge cell and maintaining light emission of the cell. It is covered by one or more dielectric layers 104 which limit the discharge current of the scan electrode and the sustain electrode 103 provided with the bus electrode b made of a metal material and insulate the electrode pairs. A protective layer 105 in which magnesium oxide (MgO) is deposited is formed on the entire surface of the dielectric layer 104 to facilitate discharge conditions.

The rear substrate 110 is arranged in such a manner that a plurality of discharge spaces, that is, barrier ribs 112 of a stripe type (or well type) for forming discharge cells are maintained in parallel. In addition, a plurality of address electrodes 113 for performing address discharge are arranged in parallel with the partition wall 112. On the upper side of the rear substrate 110, R, G and B phosphors 114 which emit visible light for displaying an image during sustain discharge are coated. A dielectric layer 115 is formed between the address electrode 113 and the phosphor 114 to protect the address electrode 113.

2 is a diagram illustrating a method of implementing an image of a conventional plasma display apparatus.

As shown in FIG. 2, the plasma display apparatus divides one frame period into a plurality of subfields having different discharge times, and emits a plasma display panel in a subfield period corresponding to a gray value of an input image signal. An image is implemented.

Each subfield is divided into a reset period for uniformly generating a discharge, an address period for selecting a discharge cell, and a sustain period for implementing gray scale according to the number of discharges. For example, when the image is to be displayed with 256 gray levels, the frame period (16.67 ms) corresponding to 1/60 second is divided into eight subfields.

In addition, each of the eight subfields is divided into a reset period, an address period, and a sustain period. Here, the sustain period is increased at the ratio of 2 ⁿ (n = 0,1,2,3,4,5,6,7) in each subfield. As described above, since the sustain period is changed in each subfield, gray levels of an image can be realized. The driving principle of the plasma display apparatus will be described with reference to FIGS. 3A and 3B.

3A is a view showing a driving waveform of a conventional plasma display device.

As shown in Fig. 3A, the plasma display apparatus erases a reset period for initializing all cells, an address period for selecting a cell to be discharged, a sustain period for maintaining the discharge of the selected cell, and wall charges in the discharged cell. It is divided into an erase period for driving.

In the reset period, a ramp-up waveform is simultaneously applied to all scan electrodes. This rising ramp waveform causes weak dark discharge within the full discharge cells. By this setup discharge, positive wall charges are accumulated on the address electrode and the sustain electrode, and negative wall charges are accumulated on the scan electrode.

In the set-down period, after the rising ramp waveform is supplied, the ramp-down waveform begins to fall from the positive voltage lower than the peak voltage of the rising ramp waveform and falls to a specific voltage level below the ground (GND) level voltage. By generating a weak erase discharge therein, the wall charges excessively formed on the scan electrodes are sufficiently erased. By this set-down discharge, wall charges such that the address discharge can stably occur remain uniformly in the cells.

In the address period, the negative scan pulses are sequentially applied to the scan electrodes, and the positive address pulses are applied to the address electrodes in synchronization with the scan pulses. As the voltage difference between the scan pulse and the address pulse and the wall voltage generated in the reset period are added, address discharge is generated in the discharge cell to which the address pulse is applied. In the cells selected by the address discharge, wall charges are formed such that a discharge can occur when the sustain voltage Vs is applied. The sustain electrode is supplied with a positive bias voltage Vzb during the set down period and the address period so that the voltage difference with the scan electrode is reduced to prevent mis-discharge with the scan electrode.

In the sustain period, a sustain pulse Su is applied to the scan electrode and the sustain electrodes alternately. In the cell selected by the address discharge, as the wall voltage and the sustain pulse in the cell are added, a sustain discharge, that is, a display discharge, occurs between the scan electrode and the sustain electrode every time the sustain pulse is applied.

After the sustain discharge is completed, in the erase period, a voltage of an erase ramp (Ramp-ers) waveform having a small pulse width and a low voltage level is supplied to the sustain electrode to erase the wall charge remaining in the cells of the full screen.

The wall charges distributed in the discharge cells by the driving pulses will be described with reference to FIG. 3B.

3B is a diagram for explaining wall charges distributed in a discharge cell according to a conventional driving waveform.

3B, in the setup period of the reset period, the pulse of the positive rising ramp is supplied to the scan electrode Y, and the sustain electrode Z and the address electrode X are supplied to the scan electrode Y described above. A pulse of a relatively lower potential is supplied so that negative charges are positioned on the scan electrode Y, and positive charges are positioned on the sustain electrode Z and the address electrode X as shown in FIG. 3B.

Subsequently, in the set-down period, the pulse of the falling ramp is supplied to the scan electrode Y, and the sustain electrode Z and the address electrode X are supplied with a predetermined bias voltage, preferably a ground level GND. As shown in FIG. 3B, the wall charges excessively accumulated in the discharge cells during the setup period are partially erased. Through such an erase process, the distribution of wall charges in each discharge cell is even.

Thereafter, in the address period, the address discharge is generated as shown in (c) by the scan pulse supplied to the scan electrode Y and the address pulse supplied to the address electrode X.

Subsequently, in the sustain period, an alternating sustain pulse is applied between the scan electrode Y and the sustain electrode Z to generate sustain discharge as shown in (d).

Meanwhile, conventionally, wall charges formed in the setup period are mainly erased between the scan electrode Y and the address electrode X through the set down period. Accordingly, the wall charge formed between the scan electrode Y and the sustain electrode Z is still maintained.

In addition, the cells of R (Red), G (Green), and B (Blue) form one pixel, and when the pixel has a monochrome pattern, that is, when a cell that is not turned on when driving is continued, Charged particles diffused in the cell are transferred to the cell that is not turned on.

As described above, in the cells that should not be turned on due to the fixed wall charges and the charges diffused in the neighboring cells, misdischarge is generated between the scan electrode Y and the sustain electrode Z during the address period. This is called. Conventional plasma display apparatuses have a problem in that bright spots are generated due to such residual latent discharge.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object thereof is to provide a plasma display apparatus capable of suppressing afterimage erroneous discharge by improving the plasma display apparatus and its driving method.

In addition, another object of the present invention is to provide a plasma display device that can improve the problem of bright spots in a monochrome pattern implemented by improving the plasma display device and its driving method.

In order to achieve the above object, the plasma display device of the present invention comprises a plasma display panel having a plurality of sustain electrodes including a scan electrode and a sustain electrode; A driving unit for driving the plurality of sustain electrodes; And a driving pulse controller controlling the driving unit to apply a falling pulse having a voltage smaller than that of the set down pulse to the scan electrode, and then applying a set down pulse, and applying a positive pulse to the sustain electrode while the falling pulse is applied. Characterized in that it comprises a.

The voltage magnitude of the falling pulse of the present invention is characterized by being 10 V or more and 50 V or less.

The width of the falling pulse of the present invention is characterized by being 10 Hz or more and 30 Hz or less.

The present invention is characterized in that the voltage magnitude of the falling pulse is controlled according to the voltage magnitude of the setup pulse applied to the scan electrode.

The falling pulse of the present invention is characterized by being a negative pulse.

The falling pulse of the present invention is characterized in that it is applied to at least one subfield period.

The falling pulse of the present invention is characterized by using a voltage supplied from the same voltage source as the setdown pulse.

The falling pulse of the present invention is characterized in that less than 30% of the voltage magnitude of the setdown pulse.

The positive pulse of the present invention is characterized by using a voltage having the same magnitude as the sustain pulse.

The driving pulse controller of the present invention is configured to apply a negative polarity pulse gradually falling to the scan electrode, and to apply a pre-reset pulse to which the positive polarity pulse is applied to the sustain electrode while the negative polarity pulse is applied. It is done.

The voltage magnitude of the falling pulse of the first subfield of the present invention is different from the voltage magnitude of the falling pulse of the remaining subfields.

The voltage magnitude of the falling pulse of the first subfield of the present invention is 10 V or more and 20 V or less, and the voltage magnitude of the falling pulse of the remaining subfields is 10 V or more and 50 V or less.

The width of the falling pulse of the first subfield of the present invention is 10 kW or more and 20 kW or less, and the width of the falling pulse of the remaining subfields is 20 kW or more and 30 kW or less.

The voltage magnitude of the setup pulse of the first subfield applied to the scan electrode of the present invention is different from the voltage magnitude of the setup pulse of the remaining subfields.

Hereinafter, with reference to the accompanying drawings, a specific embodiment according to the present invention will be described.

4 is a view for explaining the structure of a plasma display device according to an embodiment of the present invention.

As shown in FIG. 4, the plasma display apparatus according to an exemplary embodiment of the present invention includes a plasma display panel 400, a data driver 410, a scan driver 420, a sustain driver 430, and a driving pulse controller 440. ) And a driving voltage generator 450.

The plasma display panel 400 includes scan electrodes Y ₁ to Yn and a sustain electrode Z, and a plurality of address electrodes X ₁ to Xm intersecting the scan electrodes Y ₁ to Yn and the sustain electrode Z. ) Is formed.

The data driver 410 applies data to the address electrodes X ₁ to Xm formed in the plasma display panel 400. Here, the data is video signal data processed by a video signal processor (not shown) for processing a video signal input from the outside.

The data driver 410 samples and latches data in response to the data timing control signal CTRX from the driving pulse controller 440, and then stores an address pulse having an address voltage Va to each of the address electrodes X _1. To Xm).

The scan driver 420 drives the scan electrodes Y ₁ to Yn formed in the plasma display panel 400. First, the scan driver 420 supplies the scan electrodes Y ₁ to Yn to the set-up pulse and the set-down pulse which form a ramp waveform by a combination of Vs, Vsetup, and -Vy under the control of the drive pulse controller 450 during the reset period. do.

The scan driver 420 according to the exemplary embodiment of the present invention supplies a predetermined falling pulse before the setdown pulse. The falling pulse is a pulse for erasing wall charges stuck between the scan electrodes Y ₁ to Yn and the sustain electrode Z of a cell that is not turned on. The sustain driver 430 supplies the positive polarity pulse to the sustain electrode Z while the falling pulse is applied to erase some of the wall charges. A more detailed description thereof will be described later with reference to FIGS. 5A to 8.

Thereafter, a scan pulse applied from the scan reference voltage Vsc to the scan voltage -Vy during the address period is sequentially supplied to each of the scan electrodes Y1 to Yn.

Thereafter, the scan driver 420 supplies at least one sustain pulse to the scan electrodes Y1 to Yn for sustain discharge applied to the sustain voltage Vs at the ground GND level during the sustain period.

The sustain driver 430 drives the sustain electrodes Z formed as a common electrode on the plasma display panel 400.

The sustain driver 430 according to an embodiment of the present invention supplies the positive pulse to the sustain electrode Z while the falling pulse is applied to the scan electrodes Y ₁ to Yn under the control of the driving pulse controller 450. . In addition, at least one sustain pulse for supplying a bias voltage Vzb to the sustain electrodes Z during the address period and applying a sustain discharge applied to the sustain voltage Vs at the ground GND level during the sustain period is sustained. Supply to the electrodes (Z).

The driving pulse controller 440 controls the data driver 410, the scan driver 420, and the sustain driver 430 when the plasma display panel 400 is driven. That is, the driving pulse controller 440 controls timing of operation and synchronization of the data driver 410, the scan driver 420, and the sustain driver 430 in the reset period, the address period, and the sustain period as described above. The signals CTRX, CTRY, and CTRZ are generated, and the timing control signals CTRX, CTRY, and CTRZ are transmitted to the driving units 410, 420, and 430, respectively.

In this case, the data control signal CTRX includes a sampling clock for sampling data, a latch control signal, an energy recovery circuit in the data driver 410, and a switch control signal for controlling on / off time of the driving switch element. The scan control signal CTRY includes an energy recovery circuit in the scan driver 420 and a switch control signal for controlling the on / off time of the driving switch element. The sustain control signal CTRZ includes the energy in the sustain driver 430. A switch control signal for controlling the on / off time of the recovery circuit and the drive switch element is included.

The driving voltage generator 450 generates and supplies driving voltages necessary for the driving pulse controller 440 and each of the driving units 410, 420, and 430. That is, the driving voltage generator 450 generates the setup voltage Vsetup, the scan reference voltage Vsc, the scan voltage (-Vy), the sustain voltage Vs, the address voltage Va and the bias voltage Vzb. do. These driving voltages may be adjusted according to the composition of the discharge gas or the structure of the discharge cell. Here, the driving pulses and the wall charges distributed in the plasma display panel according to the plasma display apparatus according to the exemplary embodiment will be described with reference to FIGS. 5A and 5B.

5A is a view showing a driving waveform of the plasma display device according to an embodiment of the present invention.

As shown in FIG. 5A, a plasma display device according to an embodiment of the present invention includes a reset period for initializing all cells, an address period for selecting a cell to be discharged, a sustain period for maintaining discharge of a selected cell, and The driving is divided into an erasing period for erasing wall charges in the discharged cell.

In the reset period, a ramp-up waveform is simultaneously applied to all scan electrodes. This rising ramp waveform causes weak dark discharge within the full discharge cells. By this setup discharge, positive wall charges are accumulated on the address electrode and the sustain electrode, and negative wall charges are accumulated on the scan electrode.

In an embodiment of the present invention, the wall charges formed between the scan electrode and the sustain electrode are selectively erased in order to prevent afterimage erroneous discharge. For this purpose, after the rising ramp waveform is supplied to the scan electrode during the set-up period, the rising ramp waveform is lowered to the ground (GND) level lower than the peak voltage of the rising ramp waveform, and then the negative falling pulse is gradually applied. When a falling pulse is applied, a positive pulse is applied to the sustain electrode, so that a weak erase discharge occurs between the scan electrode and the sustain electrode.

By erasing discharge, the bright point problem can be more efficiently improved by selectively erasing the wall charges accumulated excessively in the cells that are not turned on in the region showing the monochrome pattern during driving.

At this time, the voltage of the falling pulse is applied to 10V or more and 50V or less based on the ground (GND) level. If the numerical value is less than 10 V, the erase discharge does not occur between the scan electrode and the sustain electrode. When the value exceeds 50 V, the erase discharge is excessively generated between the scan electrode and the sustain electrode, resulting in a dark afterimage. Here, since the falling pulse according to the embodiment of the present invention is a negative pulse, the minimum value of the falling pulse is -50 V or more-10 V or less.

The voltage magnitude of this falling pulse is controlled according to the voltage magnitude of the setup pulse applied in the setup period. Since the amount of wall charge accumulated depends on the voltage level of the setup pulse, the voltage level of the falling pulse to eliminate the wall charge is adjusted accordingly. A more detailed description thereof will be described later with reference to FIG. 6.

In addition, the fall pulse is preferably set to 10 mW or more and 30 mW or less in order to appropriately generate erase discharge.

The falling pulse according to an embodiment of the present invention can reduce the production cost in hardware configuration by using a voltage supplied from the same voltage source as the setdown pulse. By adjusting the switching time of the voltage supplied from the same voltage source, it is possible to implement the waveform of the falling pulse.

At this time, in the exemplary embodiment of the present invention, the voltage of the same voltage source as the setdown pulse (-Vy) is used, but the falling pulse is less than 30% of the voltage magnitude of the setdown pulse.

When the voltage magnitude of the falling pulse exceeds 30% of the voltage magnitude of the setdown pulse (approximately -200 V), the reset light increases due to the erase discharge between the scan electrode and the sustain electrode. In particular, a dark afterimage is generated by the reset light of cells that are not turned on in a region having a monochrome pattern, which is called a complementary afterimage. In one embodiment of the present invention, as described above, the size of the falling pulse is controlled to 30% or less of the voltage level of the setdown pulse in consideration of the complementary afterimage that may occur due to the falling pulse.

In addition, the positive pulse applied to the sustain electrode according to an embodiment of the present invention uses a voltage Vs having the same magnitude as that of the sustain pulse, thereby forming a voltage difference with the falling pulse to perform erase discharge. In addition, the production cost can be reduced even in the hardware configuration.

During the set-down period, after the falling pulse is supplied, a scan ramp and an address electrode in the cells have a ramp-down waveform falling from the ground (GND) level voltage to a specific voltage (-Vy) level whose magnitude is greater than the falling pulse. By causing an erasing discharge between them, the wall charges formed between the scan electrode and the address electrode are sufficiently erased. This set-down discharge causes uniform wall charges to remain uniformly in the cells so that the address discharge can be stably generated.

In the address period, the negative scan pulses are sequentially applied to the scan electrodes, and the positive address pulses are applied to the address electrodes in synchronization with the scan pulses. As the voltage difference between the scan pulse and the address pulse and the wall voltage generated in the reset period are added, address discharge is generated in the discharge cell to which the address pulse is applied. In the cells selected by the address discharge, wall charges are formed such that a discharge can occur when the sustain voltage Vs is applied. The sustain electrode is supplied with a positive bias voltage Vzb during the set down period and the address period so as to reduce the voltage difference with the scan electrode so as to prevent erroneous discharge from the scan electrode.

In the sustain period, a sustain pulse Su is applied to the scan electrode and the sustain electrodes alternately. In the cell selected by the address discharge, as the wall voltage and the sustain pulse in the cell are added, a sustain discharge, that is, a display discharge, occurs between the scan electrode and the sustain electrode every time the sustain pulse is applied.

After the sustain discharge is completed, in the erase period, a voltage of an erase ramp (Ramp-ers) waveform having a small pulse width and a low voltage level is supplied to the sustain electrode to erase the wall charge remaining in the cells of the full screen. The wall charges distributed in the discharge cells by the driving pulses according to the embodiment of the present invention will be described with reference to FIG. 6B.

5B is a view for explaining wall charges distributed in a discharge cell according to a driving waveform according to an embodiment of the present invention.

Referring to FIG. 5B, in the setup period of the reset period, the pulse of the positive rising ramp is supplied to the scan electrode Y, and the sustain electrode Z and the address electrode X are supplied to the scan electrode Y described above. More relatively low potential pulses are supplied. Accordingly, as illustrated in (a) of FIG. 5B, negative charges are positioned on the scan electrode Y, and positive charges are positioned on the sustain electrode Z and the address electrode X. FIG. In this case, charged particles diffused from the cells R and G in which the neighboring on state is maintained are transferred to the cell B maintaining the monochrome pattern.

Thereafter, in the falling pulse application period, the falling pulse is supplied to the scan electrode Y, and the positive pulse is supplied to the sustain electrode Z. Accordingly, as shown in (b) of FIG. 5B, selective erasure discharge occurs between the scan electrode Y and the sustain electrode Z in the cell B in which the wall charges are excessively fixed.

Subsequently, in the setdown period, a setdown pulse having an absolute magnitude greater than that of the falling pulse is supplied to the scan electrode Y, and the sustain electrode Z and the address electrode X have a predetermined bias voltage, preferably a ground level ( The voltage of GND) is supplied and maintained. Accordingly, as shown in (c) of FIG. 5B, the wall charges formed through the setup period are partially erased. Through such an erase process, the distribution of wall charges in each discharge cell is even.

Subsequently, in the address period, address discharge is generated as shown in FIG. 5B by the scan pulse supplied to the scan electrode Y and the address pulse supplied to the address electrode X. FIG.

Subsequently, in the sustain period, an alternating sustain pulse is applied at least once between the scan electrode Y and the sustain electrode Z to generate a sustain discharge as shown in Fig. 5B (e).

6 is a waveform diagram illustrating a relationship between a setup pulse and a falling pulse according to an embodiment of the present invention.

As shown in FIG. 6, in one embodiment of the present invention, a peak voltage value of a setup pulse applied to a scan electrode may be adjusted as necessary. It can be adjusted in units of frames in time and can be adjusted in units of subfields in detail. In addition, it is spatially adjustable for each scan electrode line unit. At this time, as the peak voltage value of the setup pulse increases, the amount of wall charges formed on each electrode also increases and becomes saturated at some degree or more. As such, in consideration of the wall charge amount increased as the peak voltage value increases, in one embodiment of the present invention, the voltage magnitude of the falling pulse is controlled according to the voltage magnitude of the setup pulse. As shown in (a) to (c), by increasing the absolute value of the voltage magnitude of the falling pulse as the voltage magnitude of the setup pulse increases, the wall charge between the scan electrode and the sustain electrode is appropriately erased.

7 is a view showing a modified waveform of the plasma display device according to an embodiment of the present invention.

As shown in FIG. 7, a falling pulse is applied to at least one subfield period during one frame. Including a falling pulse in the entire subfield for one frame is preferable for suppressing afterimage false discharge, but the other period is reduced due to time constraints. For example, when the sustain period representing the sustain discharge light, which is the actual display light, is reduced, the number of falling pulses can be overcome in the embodiment of the present invention in consideration of the fact that the contrast of the displayed screen is reduced. Can be applied every frame.

8 is a waveform diagram illustrating a waveform including a pre-reset pulse according to an embodiment of the present invention.

As shown in FIG. 8, the modified waveform according to the embodiment of the present invention includes a pre-reset pulse.

In the pre-reset period, a negatively decreasing negative pulse is supplied to the scan electrode, and a positive pulse of the sustain voltage Vs is supplied to the sustain electrode. In addition, 0 V of the ground (GND) level is applied to the address electrode.

In the discharge cells during the pre-reset period, dark discharge occurs between the scan electrode and the sustain electrode and between the sustain electrode and the address electrode, and wall charges are formed. Accordingly, all the discharge cells have the same wall charge distribution through the pre-reset period, thereby initializing every frame. By ensuring a stable wall charge state through this pre-reset period, the setup voltage level of the setup pulse can be lowered in the reset period of each subfield for one frame.

In the setup period of the reset period, pulses of the first positive ramp ramp-up waveform and the second positive ramp ramp-up waveform 2 are sequentially applied to the scan electrode, and 0 V is applied to the sustain electrode and the address electrode. Is applied. The voltage of the first positive ramp ramp-up 1 waveform rises from 0 V to the positive sustain voltage Vs, and the voltage of the second positive ramp ramp-up 2 waveform is the positive sustain voltage Vs. ) To a higher setup voltage (Vsetup 1). After the setup period, wall charges accumulate in all the discharge cells.

Here, in one embodiment of the present invention, the voltage magnitude of the setup pulse of the first subfield SF1 applied to the scan electrode is different from the voltage magnitude of the setup pulse of the remaining subfields SF2 to SFn. That is, the first subfield SF1 is controlled to have a high level of the setup voltage Vsetup 1, and the remaining subfields SF2 to SFn are controlled to have a lower level of the setup voltage Vsetup 2 than the first subfield.

After the set-up period, the scan electrode is supplied with a rising ramp waveform in the set-up period, and then falls to a voltage at a ground (GND) level lower than the peak voltage of the rising ramp waveform, and then a negative falling pulse is gradually applied. . When the falling pulse is applied, a positive pulse is applied to the sustain electrode Z, so that a weak erase discharge occurs between the scan electrode and the sustain electrode.

In the driving waveform including the pre-reset period according to an embodiment of the present invention, the voltage magnitude of the falling pulse of the first subfield is different from the voltage magnitude of the falling pulse of the remaining subfields. That is, in the first subfield SF1, since the wall charges accumulated in the discharge cells initialized by the pre-reset period are small, the erase discharge is weakly controlled. In the remaining subfields SF2 through SFn, the wall charges have already been reduced to some extent. Is controlled to control the erase discharge more strongly than the first subfield.

Preferably, the voltage magnitude of the falling pulse of the first subfield SF1 is applied to 10 V or more and 20 V or less based on the ground GND level, and the voltage magnitude of the falling pulse of the remaining subfields SF2 to SFn is 10. Apply at V or more and 50 V or less.

If the numerical value is less than 10 V, no erase discharge occurs between the scan electrode and the sustain electrode, and if 20 V of the first subfield SF1 and 50 V of the remaining subfields SF2 to Sfn are exceeded, the erase discharge is performed between the scan electrode and the sustain electrode. The discharge is excessively generated, resulting in dark afterimages.

In addition, the width of the falling pulse is set so that the width of the falling pulse of the first subfield SF1 is 10 mW or more and 20 mW or less, and the width of the falling pulses of the remaining subfields SF2 through SFn is set so as to secure an appropriate erase discharge period. It is preferable to keep it in 20 Pa or more and 30 Pa or less.

The set down period, the address period, and the sustain period of the reset period have been described fully with reference to FIG. 5A and will be omitted.

As described above, the bright point problem can be more efficiently improved by selectively erasing the wall charges accumulated excessively in the cells that are not turned on in the region showing the monochrome pattern during the driving. In addition, by limiting the voltage magnitude of the falling pulse, it is possible to prevent the problem that the complementary afterimage occurs.

As such, the technical configuration of the present invention described above can be understood by those skilled in the art that the present invention can be implemented in other specific forms without changing the technical spirit or essential features of the present invention.

Therefore, the exemplary embodiments described above are to be understood as illustrative and not restrictive in all aspects, and the scope of the present invention is indicated by the following claims rather than the detailed description, and the meaning and scope of the claims and All changes or modifications derived from the equivalent concept should be interpreted as being included in the scope of the present invention.

As described above, the present invention improves the plasma display device and its driving method, thereby having an effect of suppressing afterimage erroneous discharge.

In addition, the present invention has the effect of improving the bright point in the monochrome pattern to be implemented by improving the plasma display device and its driving method.

In addition, the present invention has the effect of preventing the complementary color image retention of the image to be implemented.

Claims (12)

A plasma display panel including a plurality of sustain electrodes including scan electrodes and sustain electrodes; A driving unit for driving the sustain electrode; And A driving pulse controller which controls the driving unit to apply a falling pulse to the scan electrode during a reset period, and then apply a set-down pulse, and apply a positive pulse to the sustain electrode while the falling pulse is applied. Plasma display device comprising a. The method of claim 1, And a voltage magnitude of the falling pulse is 10 V or more and 50 V or less. The method of claim 1, And a width of the falling pulse is 10 mW or more and 30 mW or less. The method of claim 1, And the voltage magnitude of the falling pulse is controlled according to the voltage magnitude of the setup pulse applied to the scan electrode during the reset period. The method of claim 1, The falling pulse is a plasma display device, characterized in that the negative pulse. The method of claim 1, And the falling pulse is applied to at least one subfield period. The method of claim 1, And said falling pulse is supplied from the same voltage source as said setdown pulse. The method of claim 1, And the maximum voltage of the falling pulse is 30% or less of the maximum voltage of the setdown pulse. The method of claim 1, And the positive polarity pulse uses the same voltage as the sustain pulse applied to the sustain electrode in the sustain period following the address period. The method of claim 1, A positive pulse is applied to the sustain electrode before the setup pulse applied to the scan electrode before the set down pulse is applied, and a negatively decreasing negative pulse is gradually applied to the scan electrode while the positive pulse is applied. And a plasma display device. The method of claim 1, And the maximum voltage level of the falling pulse in the first subfield is different from the maximum voltage level of the falling pulse in at least one of the remaining subfields. The method of claim 1, And the maximum voltage level of the setup pulse in the first subfield applied to the scan electrode is different from the maximum voltage level of the setup pulse in at least one subfield of the remaining subfields.

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