KR100728955B1 - Majority voter circuit - Google Patents

Abstract

The present invention relates to a majority voter circuit which receives consecutive n bits of data having a first or second logic level and whose output varies according to the number of bits of data having the same logic level among the n bits of data . The circuit may further include: a first sorting unit for receiving upper n / 2-bit data of the n-bit data inputs and rearranging the upper n / 2-bit data into data groups of first and second logic levels; A second sorting unit for receiving the lower n / 2-bit data of the n-bit data inputs and rearranging the lower n / 2-bit data into data groups of first and second logic levels; The data group of the first logic level or the second logic level transmitted from the first and second arranging units is received and rearranged into the data group of the first logic level and the second logic level in the upper n / 2 bits, To the lower n / 2 bits; And a determination unit that receives the lower n / 2-bit data of the third arrangement unit and generates an output signal that determines a majority of the first or second logic level of the n-bit data input.

Description

Majority voter circuit

1 is a circuit diagram showing a comparator according to the present invention;

2 is a truth table showing input / output of a comparator according to the present invention.

3 is a circuit diagram of a majority decision circuit according to the first embodiment of the present invention;

4 is a circuit diagram of a majority decision circuit according to a second embodiment of the present invention;

5 is a circuit diagram of a majority decision circuit according to a third embodiment of the present invention;

6 is a circuit diagram of a majority decision circuit according to a fourth embodiment of the present invention;

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a majority voter circuit, and more particularly, to a majority decision circuit in which a plurality of gates and end gates are used to reduce the area of a chip or the like to be applied, .

As is well known, the majority decision circuit outputs a high level value when a bit exceeding a majority of the input is a high level among the n bit inputs input to the majority decision circuit, and when a bit exceeding a majority of the inputs is at a low level , It outputs a low level value.

Conventional methods of implementing a majority decision circuit include an arithmetic-based structure that adds all binary input values using an adder and then goes to a high level when the value exceeds half the number of inputs arithmetic-based design, a decomposition-based design that uses a part of input as a control input of a mux and computes the remaining input values to obtain an output value .

However, in these schemes, the larger the number of bits of the input to be received, the more complicated the circuit becomes, and thus the price increases.

 Therefore, it is an object of the present invention to provide a majority decision circuit which is simple in configuration of a circuit and excellent in price.

According to an aspect of the present invention, there is provided a semiconductor memory device for receiving consecutive n bits of data having a first or second logic level and outputting the n bits of data according to the number of bits of data having the same logic level A first sorting unit for receiving the upper n / 2-bit data among the n-bit data inputs and rearranging the upper n / 2-bit data into data groups of first and second logic levels; A second sorting unit for receiving the lower n / 2-bit data of the n-bit data inputs and rearranging the lower n / 2-bit data into data groups of first and second logic levels; The data group of the first logic level or the second logic level transmitted from the first and second arranging units is received and rearranged into the data group of the first logic level and the second logic level in the upper n / 2 bits, To the lower n / 2 bits; And a determination unit that receives the lower n / 2-bit data of the third arrangement unit and generates an output signal that determines a majority of the first or second logic level of the n-bit data input.

In the above configuration, the determination unit may be configured such that all the data rearranged to the upper n / 2 bits of the third rearranging unit have the same level, and at least one of the lower n / And the output signal is enabled if it has the same level as the data.

In the above configuration, the determination unit may be configured such that all the data rearranged to the upper n / 2 bits of the third rearranging unit have the same level, and all of the lower n / And disables the output signal if it is not at the same level.

In the above configuration, the determination unit may disable the output signal when the data rearranged to the upper n / 2 bits of the third arrangement unit are not at the same level.

According to another aspect of the present invention, there is provided a semiconductor memory device for receiving consecutive n bits of data having a first logic level or a second logic level, There is provided a majority decision circuit in which the output is different: the circuit comprising: a first arrangement for receiving upper n / 2 bit data of the n bit data input and rearranging the upper n / 2 bit data into data groups of first and second logic levels; A second sorting unit for receiving the lower n / 2-bit data of the n-bit data inputs and rearranging the lower n / 2-bit data into data groups of first and second logic levels; A row judging unit for receiving a data group of a first logic level or a second logic level transmitted from the first and second arranging units and generating an output signal; Wherein when the output signal of the row determining unit is the first logic level, a majority of the n-bit data inputs are the second logic level, and when the output signal of the row determining unit is the second logic level, n bits And less than a majority of data inputs is at a second logic level.

According to another aspect of the present invention, there is provided a semiconductor memory device for receiving consecutive n bits of data having a first logic level or a second logic level, There is provided a majority decision circuit in which the output is different: the circuit comprising: a first arrangement for receiving upper n / 2 bit data of the n bit data input and rearranging the upper n / 2 bit data into data groups of first and second logic levels; A second sorting unit for receiving the lower n / 2-bit data of the n-bit data inputs and rearranging the lower n / 2-bit data into data groups of first and second logic levels; And a high determining unit receiving the data group of the first logic level or the second logic level transmitted from the first and second arranging units and generating an output signal; Wherein when the output signal of the high determination unit is at a first logic level, more than a majority of the n-bit data inputs are at a first logic level, and when the output signal of the row determining unit is a second logic level, And less than a majority of data inputs is at a first logic level.

According to another aspect of the present invention, there is provided a semiconductor memory device for receiving consecutive n bits of data having a first logic level or a second logic level and comparing the number of bits of data having the same logic level There is provided a majority decision circuit in which the output is varied: the circuit comprising: an arranging unit for receiving the n bit data input and dividing by two bits and rearranging the data into data of first and second logic levels, respectively; And an output unit receiving the n-bit data rearranged by the rearranging unit and outputting first and second output signals; Wherein when both the first output signal and the second output signal are at a first logic level, the n-bit data inputs are all at a first logic level, and both the first output signal and the second output signal are both And the second logic level, all of the n bit data inputs are at a second logic level.

(Example)

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a circuit diagram showing a comparator according to the present invention.

As shown, the comparator according to the present invention is comprised of an OR gate 110 and an AND gate 120 connected in parallel to two input signals.

In the case of inputting two bits of binary numbers, the OR gate 110 and the AND gate 120 commonly receive two bits of two binary numbers, and output the result.

2, the output signal of the OR gate 110 outputs a large number of 2 bits of binary data to be input, and the AND gate 120 outputs a small number of 2 bits of the inputted binary number . However, when each of the binary numbers constituting the 2 bits has the same value, the output signal of the comparator has the same output value as the input value.

3 is a circuit diagram showing a majority decision circuit using a plurality of comparators according to a first embodiment of the present invention.

Hereinafter, a description will be given of a case where binary numbers of 8 bits, that is, 10110101, are input for convenience.

As shown in the drawing, the majority decision circuit according to the first embodiment of the present invention includes a first alignment unit 310 having A to C stages 311, 312 and 313, a second alignment unit 310 having A 'to C' stages 321, 322 and 323, An alignment unit 320, a third alignment unit 330 having four comparators, and a determination unit 340 having three oates 341, 342, and 343.

The first arranging unit 310 includes A to C steps 311, 312 and 313 for receiving the upper 4 bits 1011 among the 8 bits 10110101.

In step A 311, 4 bits 1011 are rearranged to 4 bits 1011 through two comparators. To be more specific, the two comparators receive 2 bits 10 and 11 of each divided by 4 bits 1011 and output 10 and 11, respectively. Thus, 4 bits 1011 are relocated to 4 bits 1011.

Next, step B 312 is a step of rearranging 4 bits 1011 to 4 bits 1110 through two comparators. In detail, the two comparators receive the respective 2 bits 11 and 01 divided by 4 bits 1011 and output 11 and 10, respectively. Therefore, 4 bits 1011 are relocated to 4 bits 1110. [

Finally, step C 313 is a step of rearranging 4 bits 1110 to 4 bits 1110 through one comparator. In detail, the most significant bit 1 and the least significant bit 0 of the 4 bits 1110 are arranged as they are, and the 2 bits 11 of the middle bits are rearranged to 11 through one comparator. The reason for comparing only the middle two bits is that the most significant bit 1 and the least significant bit 0 have been rearranged through steps A and B. [ Therefore, in the C step 313, only the middle 2 bits are compared, and finally the 4 bits 1110 are rearranged to 4 bits 1110. [

The second arranging unit 320 includes A 'to C' steps 321, 322 and 323 for receiving the lower 4 bits 0101 of 8 bits 10110101.

First, the A 'step 321 is a step of rearranging the lower 4 bits 0101 to 4 bits 1010 through the two comparators. To be more specific, the two comparators receive the two bits 01 and 01 divided by 4 bits 0101 and output the two bits 10 and 10, respectively. Therefore, 4 bits 0101 are relocated to 4 bits 1010. [

Next, the B 'step 322 is a step of rearranging 4 bits 1010 to 4 bits 1010 through two comparators. In detail, the two comparators receive each of the 2 bits 11 and 00 divided by 4 bits 1010 and output 2 bits 11 and 00, respectively. Thus, 4 bits 1010 are relocated to 4 bits 1010.

Finally, the C 'step 323 is a step of rearranging 4 bits 1010 to 4 bits 1100 through one comparator. In detail, the most significant bit 1 and the least significant bit 0 of 4 bits 1010 are arranged as they are, and the 2 bits 01 in the middle are relocated to 10 bits through one comparator. The reason why only the middle two bits are compared is that the most significant bit 1 and the least significant bit 0 have been rearranged through the steps A 'and B'. Accordingly, in the C 'step 323, only the middle 2 bits are compared, and finally, the 4 bits 1010 are rearranged to 4 bits 1100.

The third sorting unit 330 includes 8 bits 11101100 rearranged through the first and second arranging units 310 and 320 and four comparators for dividing the received 8 bits 11101100 by 2 bits. In this configuration, the four comparators receive each of the 2 bits 10, 10, 11, and 01 divided by the 8 bits 11101100 and output 2 bits 10, 10, 11, Thus, finally, the 8-bit 11101100 is relocated to the 8-bit 11110100. Here, when the upper 4 bits out of the 8 bits output from the third sorting unit 330 are not all 1s, 0 exceeds the majority of the input. On the other hand, when the upper 4 bits out of the 8 bits outputted from the third arranging unit 330 are all 1, it is judged whether the majority of the input is 1 or not through the judging unit 340 which receives the lower 4 bits .

The determining unit 340 receives the lower 4 bits 0100 of the 8 bits 11110100 output to the third arranging unit 330 and judges whether or not the majority of the input is greater than or equal to 1 through the three oates 341 to 343 do. In detail, the gates 341 and 342 receive 01 and 00, which are obtained by dividing the input 4-bit 0100 by 2 bits, respectively, and output 1 and 0, respectively. The OR gate 343 receives the outputs 1 and 0 of the gates 341 and 342, and finally outputs 1. Here, when the output signal of the determining unit 340 is 1, it indicates that the number of 1s out of the 8-bit data input to the third arranging unit 330 is more than a half, while when it is 0, Or less.

FIGS. 4 and 5 are circuit diagrams of a majority decision circuit according to the second and third embodiments of the present invention. When the input / output channel is precharged to a high level or a low level, the data inversion scheme. Here, the data inversion structure is a structure in which a predetermined number of bits of data to be currently output from the memory device are compared with previously output data on a bit basis, and when the number of toggled bits is more than half, Output structure. For example, if the input / output channel (I / O channel) of the semiconductor device is precharged to a high level and the low level number of inputs exceeds a majority, the data on the input / output channel will change from high level to low level There is a lot of power consumption. Therefore, the data inversion structure is used to reduce power consumption by reducing the number of data that changes from a high level to a low level in an input / output channel.

First, referring to FIG. 4, a circuit for determining whether the number of zeros in the input exceeds a majority in a case where the input / output channel is precharged to a high level will be described.

Hereinafter, description will be made for the case where 8 bits, that is, 01000101, is input for convenience.

As shown, the majority decision circuit according to the second embodiment of the present invention includes a first alignment unit 410 having A to C stages 411, 412 and 413, a second alignment unit 410 having A 'to C' stages 421, 422 and 423, An alignment unit 420 and a row determination unit 430 having four oates 431, 432, 433 and 434 and three AND gates 435, 436 and 437. Here, the first and second alignment units 410 and 420 have the same configuration as the first and second alignment units 310 and 320 shown in FIG. 3, and will not be described here for the sake of convenience.

The row determining unit 430 receives the data output from the first and second arranging units 410 and 420 and outputs data of high level or low level through the four oates 431, 432, 433, and 434 and three end gates 435, 436, And outputs the data. In more detail, the first and second alignment units 410 and 420 receive 01000101 and output 10001100. The gates 431, 432, 433 and 434 receive the 01, 00, 01 and 01 divided by 10001100 and output 1, 0, 1 and 1. The AND gates 435 and 436 receive the 10 and 11 respectively 0, 1 are output. Further, the AND gate 437 receives 0, 1 and finally outputs 0. Therefore, when the input data is 01000101, the final output value of the row determining unit 430 is 0, so that it can be seen that the number of zeros of the input data exceeds the majority.

Therefore, when the majority decision circuit according to the second embodiment of the present invention is applied to the data inversion structure of the semiconductor device, the input data of the majority decision circuit according to the second embodiment exceeds 0, i.e., the majority of the number of low levels , The data inversion flag becomes high level, and the inverted input data is transferred to the input / output channel.

Next, referring to FIG. 5, a circuit for determining whether the number of 1's in the input exceeds a majority, when the input / output channel is precharged to a low level will be described.

Hereinafter, the case where 8 bits, that is, 10110101, is input for convenience will be described.

As shown, the majority decision circuit according to the third embodiment of the present invention includes a first alignment unit 510 having A to C stages 511, 512 and 513, a second alignment unit 510 having A 'to C' stages 521, 522 and 523, An alignment unit 520 and a high determination unit 530 having four AND gates 531, 532, 533 and 534 and three oates 535, 536 and 537. For reference, the first and second alignment units 510 and 520 shown in FIG. 4 have the same configuration as the first and second alignment units 310 and 320 shown in FIG. 3, and therefore will not be described herein for the sake of convenience.

The high determination unit 530 receives the data output from the first and second alignment units 510 and 520 and outputs 1 or 0 through the four AND gates 531, 532, 533 and 534 and the three oates 535, 536 and 537. In more detail, the first and second alignment units 510 and 520 receive 10110101 and output 11101100 to 11101100. The AND gates 531, 532, 533 and 534 receive the 01, 11, 10 and 01 divided by 11101100 and output 0, 1, 0 and 0. The OR gate 535 and 536 respectively receive 01 and 00, . Further, the OR gate 537 receives 1, 0 and finally outputs 1.

Therefore, when the majority decision circuit according to the third embodiment of the present invention is applied to the data inversion scheme of the semiconductor device, the input data of the majority decision circuit according to the third embodiment exceeds 1, that is, the majority of the number of high level , The data inversion flag becomes high level, and the input data is inverted and transmitted to the input / output channel.

FIG. 6 is a circuit diagram of a majority decision circuit according to the fourth embodiment of the present invention, which is applicable to a compress mode of a semiconductor device. Here, the compression mode refers to compressing a bit having the same value among the input bits into a single bit and outputting it.

As shown, the majority decision circuit according to the fourth embodiment of the present invention comprises an arrangement 610 composed of four comparators 611, 612, 613 and 614, three ogates 621, 623 and 625 and three end gates 622, 624 and 626 And an output unit 620.

The comparators 611, 612, 613, and 614 receive the 2-bit input data divided by 8 bits, respectively, and output the rearranged 8 bits.

The OR gate 621 receives the output of the OR gate of the comparator 611 and the output of the OR gate of the comparator 612 to output 1 or 0 and the OR gate 623 outputs the output of the OR gate of the comparator 611 And the output of the comparator 612 and outputs 1 or 0. The OR gate 625 receives the output of the OR gate 621 and outputs out1.

The AND gate 622 receives the AND gate output of the comparator 613 and the AND gate output of the comparator 614 and outputs 1 or 0 and the AND gate 624 outputs the AND gate output of the comparator 613 And the AND gate output of the comparator 614 and outputs 1 or 0. And, the AND gate 626 receives the output of the AND gate 624 and outputs out2.

If the output value out1 of the gate 625 is 0, that is, the low level, the values of the input data are all at the low level and the output out2 of the AND gate 622 is 1, It is high level.

Therefore, the majority decision circuit according to the fourth embodiment of the present invention can be used to test whether all of the input data is at the high level or the low level, in order to use the compression mode of the semiconductor device.

The majority decision circuit according to the present invention is simply composed of a plurality of AND gates and a gate. Therefore, the circuit is simple in design, and the cost is reduced. Furthermore, the majority decision circuit according to the present invention may be applied to a data inversion structure and a compression mode of a semiconductor device by applying a majority decision circuit.

According to the above-described structure of the present invention, the majority decision circuit according to the present invention has an effect of reducing the area of a chip or the like, which is constituted by a plurality of AND gates and an O gate, and is excellent in cost.

While the present invention has been particularly shown and described with reference to specific embodiments thereof, it is to be understood that the invention is not limited thereto and that various changes and modifications may be made without departing from the spirit or scope of the invention as set forth in the following claims Those skilled in the art will readily appreciate that such modifications and variations can be made without departing from the scope of the invention.

Claims (7)

There is provided a majority vote determination circuit for receiving consecutive n bits of data having a first or second logic level and varying the output according to the number of bits of data having the same logic level among the n bits of data, A first sorting unit for receiving upper n / 2-bit data of the n-bit data input and rearranging the upper n / 2-bit data into data groups of first and second logic levels; A second sorting unit for receiving the lower n / 2-bit data of the n-bit data inputs and rearranging the lower n / 2-bit data into data groups of first and second logic levels; The data group of the first logic level or the second logic level transmitted from the first and second arranging units is received and rearranged into the data group of the first logic level and the second logic level in the upper n / 2 bits, To the lower n / 2 bits; And And a determination unit for receiving the lower n / 2-bit data of the third arrangement unit and generating an output signal for determining a majority of the first or second logic level of the n-bit data input Circuit. delete delete delete A majority decision circuit which receives consecutive n bit data having a first logic level or a second logic level and whose output varies according to the number of bits of data having the same logic level among the n bit data, A first sorting unit for receiving upper n / 2-bit data of the n-bit data input and rearranging the upper n / 2-bit data into data groups of first and second logic levels; A second sorting unit for receiving the lower n / 2-bit data of the n-bit data inputs and rearranging the lower n / 2-bit data into data groups of first and second logic levels; And A row judging unit for receiving a data group of a first logic level or a second logic level transmitted from the first and second arranging units and generating an output signal; And, When the output signal of the row determining unit is at a first logic level, a majority of the n-bit data inputs are at a second logic level, and when the output signal of the row determining unit is at a second logic level, Is a second logic level. A majority decision circuit which receives consecutive n bit data having a first logic level or a second logic level and whose output varies according to the number of bits of data having the same logic level among the n bit data, A first sorting unit for receiving upper n / 2-bit data of the n-bit data input and rearranging the upper n / 2-bit data into data groups of first and second logic levels; A second sorting unit for receiving the lower n / 2-bit data of the n-bit data inputs and rearranging the lower n / 2-bit data into data groups of first and second logic levels; And A high determination unit receiving a data group of a first logic level or a second logic level transmitted from the first and second alignment units and generating an output signal; And, When the output signal of the high determination unit is at the first logic level, a majority of the n-bit data input is at the first logic level, and when the output signal of the row determining unit is at the second logic level, Is a first logic level. A majority decision circuit which receives consecutive n bit data having a first logic level or a second logic level and whose output varies according to the number of bits of data having the same logic level among the n bit data, An alignment unit for receiving the n-bit data input and dividing the input data by two bits, and rearranging the data into data of first and second logic levels, respectively; And An output unit receiving the n-bit data rearranged by the rearranging unit and outputting first and second output signals; And, Wherein when both the first output signal and the second output signal are at a first logic level, the n-bit data inputs are all at a first logic level, and wherein both the first output signal and the second output signal are at a second logic level , Wherein all of said n-bit data inputs are at a second logic level.

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