KR100724365B1 - Plasma display panel - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plasma display panel, wherein a conventional plasma display device is driven in such a manner as to maintain light emission by surface discharge after a counter discharge. Since this is carried out, the charges are rearranged before discharge so that the wall voltage can be formed above a certain level. However, in the conventional panel structure, when charge transfer becomes active such as high temperature, wall charge decreases due to movement and recombination of charges, and thus there is a fatal problem that discharge does not occur even when a driving voltage for discharge is applied. . In view of the above problems, the present invention is to form the top dielectric of the plasma display device in a different structure according to the region of the top electrode, or to form a dielectric having a different dielectric constant, thereby changing the capacitance of each electrode, so that the plasma It prevents erroneous discharge due to wall charge reduction by suppressing wall charge movement even in an active environment, and consequently, greatly increases the reliability of the panel.

Description

Plasma Display Panel {PLASMA DISPLAY PANEL}

1 is a cross-sectional view showing a typical plasma display panel device.

Figure 2 is a waveform diagram showing a conventional general panel driving method.

3 is a cross-sectional view of a device showing charge distribution immediately before an address discharge;

4 is a procedure cross-sectional view showing a change in charge distribution in an address discharge section at a high temperature.

5 is a cross-sectional view showing a panel structure according to an embodiment of the present invention.

6 is a sectional view showing a panel structure according to another embodiment of the present invention.

*** Explanation of symbols for main parts of drawing ***

1: lower substrate 2: barrier film

3: address electrode 4: lower dielectric

5: bulkhead 6: phosphor

10: lower plate structure 11: upper substrate

12: transparent (ITO) electrode 13: bus electrode

14: top dielectric 15: protective film

24: non-uniform top dielectric 25: low dielectric constant top dielectric

26: high dielectric constant plate dielectric

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plasma display panel, and more particularly, to a plasma display panel in which a structure or a material of a top dielectric is changed to maintain wall charge regardless of temperature by preventing wall charge reduction occurring at high temperature.

Plasma Display Panel (PDP) devices, which are spotlighted as next-generation display devices along with TFT liquid crystal display (LCD), organic EL, and FED, are He + Xe in discharge cells isolated by barrier ribs. Or 147 nm ultraviolet rays generated at the time of discharge of Ne + Xe gas excite the phosphors of R, G, and B and use the light emission phenomenon due to the energy difference when the phosphor returns from the excited state to the ground state. The PDP display device is expected to occupy the large display device market of 40 ˝ or more due to its simple structure, ease of manufacturing, high brightness and high light emitting efficiency, memory function, high nonlinearity, and wide viewing angle of 160 ° or more. A 102 "class product has already been developed.

1 is a cross-sectional view showing a typical AC PDP device, first of which a lower plate of the PDP device is deposited on the entire surface of the lower glass substrate 1 to prevent penetration of alkali ions contained in the substrate 1; An address electrode 3 of a discharge cell formed on a part of the blocking film 2; A lower plate dielectric 4 formed on the entire surface of the blocking film 2 including the address electrode 3; Barrier ribs 5 formed on the lower plate dielectric 4 to isolate discharge cells; It consists of a phosphor 6 formed on the lower plate dielectric 4 isolated by the partition wall (5).

The upper panel of the plasma display panel element includes a transparent electrode 12 formed on the upper glass substrate 11 and a bus electrode 13 for lowering the resistance of the transparent electrode 12; An upper plate dielectric 14 formed on an entire surface of the upper glass substrate 11 including the transparent electrode 12 and the bus electrode 13; It is formed on the upper surface of the upper dielectric 14 to form a protective film 15 to protect the upper dielectric 14 according to the plasma discharge, the upper plate formed in this way, the protective film 15 is the barrier rib 5 and the phosphor of the lower plate ( It is installed to face 6).

As described above, each electrode of the AC-type PDP device using three electrodes for driving has an address electrode 3 located on the lower plate and a pair of transparent electrodes 12 and bus electrode 13 located on the upper plate according to its function. It is divided into a scan electrode and a sustain (sustain) electrode is made, the scan electrode and the sustain electrode is formed of the same structure, and because the operation in the same function in the sustain section, both may be referred to as the sustain electrode. Therefore, each electrode is referred to as an X electrode and a scan electrode for outputting a scan pulse in an address section is referred to as a Y electrode, and a sustain electrode having the same structure as that of the scan electrode is used to distinguish the driving method. A common electrode may also be referred to as a Z electrode.

The driving method using the electrodes will be described using the basic driving waveform diagram of FIG. 2.

First, the driving cycle of the plasma display panel element is a repetition of a subframe SF composed of a reset period, an address period, and a sustain period. The wall charge of each cell is initialized during the reset period, and the cells to be discharged during the address period are reset. It selects and performs a counter discharge, and performs a continuous display discharge (surface discharge) with respect to the selected cell during the sustain period.

During the reset period, a ramp waveform is applied between the Y electrode and the Z electrode so that the wall charges of each electrode are initialized, and a predetermined positive charge is accumulated on the X electrode maintaining the ground potential.

When the reset is completed and enters the address section, the initial wall charge state (section A) for performing counter discharge is the same as the charge distribution shown in the cross-sectional view of the element shown in FIG. That is, in the address period, positive charges are applied to the Z electrode to accumulate negative charges, and a weak negative voltage is applied to the Y electrode, so that only a few negative charges remain, and positive charges are accumulated to the X electrode, which is the ground potential, through a reset process.

When the cell is selected at an address time point (following section A), a positive voltage is applied to the X electrode to push out the accumulated positive charges, and a negative voltage is applied to the Y electrode to push out the accumulated negative charges so that counter discharge is performed.

Subsequently, when the sustain period is reached, surface discharge is alternately performed between the Y electrode and the Z electrode to maintain the discharge generated by the opposite discharge, and the gray scale is expressed by adjusting the discharge degree during the sustain period.

In each of the driving periods, the actual start of driving of the PDP element is a counter discharge in an address section for determining a cell to emit light, and thus, a scan waveform and an address waveform of a predetermined length are provided at a high voltage for accurate counter discharge. This is because the wall charge initialization by the reset may not be complete according to the operating state of the panel. Particularly, since the X electrode always maintains the ground potential and operates only in the address section, the counter discharge is performed so that It is difficult to control the wall charges to accumulate on the X electrode.

In addition to the difficulty of controlling the wall charges accumulated in the X electrode holding the ground potential as described above, and the incomplete formation of the initial wall voltage due to incomplete reset, another main cause of reducing the wall charges is the space caused by the high temperature. Activation of charge transfer.

The activation of the idle charge transfer due to the high temperature causes a fatal problem in the condition of the opposite discharge where a high discharge voltage is required, and the amount of wall charge for the opposite discharge is reduced by the high temperature, thereby making it impossible to discharge. In general, in order to discharge, the address voltage plus the wall voltage must be larger than the discharge start voltage. In a high temperature state, when the wall charge initialized through the reset section enters the address section, the actual address voltage is applied. It will be reduced for the time until.

4 illustrates a process in which wall charges of each electrode initialized after reset are reduced within an address period.

As shown, when the initial wall charges are properly configured after the reset (Fig. 4a), when the movement of the space charges due to the high temperature is activated, the negative charges accumulated on the Y electrodes leave the Y electrodes and the positive charges or X between the electrodes are removed. The positive charges accumulated on the electrode are combined with each other, and the negative charges accumulated on the Z electrode are combined with the activated positive charges to reduce their size. This joining process is shown in Figure 4b.

As shown in FIG. 4B, positive charges are accumulated on the Y electrode to which a weak negative voltage is applied due to recombination and accumulation due to movement of activated charges at a high temperature, and negative charges accumulated on the Z electrode to which the positive voltage is applied are partially lost. In addition, the positive charges accumulated in the X electrode may be combined or moved with the negative charges, and thus hardly remain. Therefore, even if the addressing voltage is applied at the time when the opposite discharge is required, the wall voltage between the X-Y electrodes is insufficient, so that discharge does not occur.

As described above, the conventional plasma display device is driven in a manner that maintains light emission by surface discharge after the opposite discharge, the discharge is performed when the sum of the wall voltage and the driving voltage formed on the target electrode is a predetermined level or more, so that the wall The charges are rearranged before discharging so that the voltage can be formed above a certain level. However, in the conventional panel structure, when charge transfer becomes active such as high temperature, wall charge decreases due to movement and recombination of charges, and thus there is a fatal problem that discharge does not occur even when a driving voltage for discharge is applied. .

The present invention for solving the above-mentioned problems is to change the structure of the top dielectric of the plasma display device or to form a dielectric having a different dielectric constant differently according to the characteristics of the top electrode, thereby suppressing the mobility of the wall charges even at high temperatures It is an object of the present invention to provide a plasma display panel which prevents erroneous discharge due to a decrease in charge.

In order to achieve the above object, the present invention is provided with an X electrode positioned on the lower plate to apply an address voltage, a Y electrode positioned on the upper plate to face and discharge the X electrode, and a Z electrode surface discharged from the Y electrode. The plasma display panel includes a top dielectric layer formed to have a different structure or dielectric constant on the Y electrode and the Z electrode region so that the Y electrode and the Z electrode have different capacitances.

The upper dielectric layer has a structure in which a portion where the Y electrode is thick and a portion where the Z electrode is thin have a thin structure.

The upper dielectric layer is formed of a dielectric having a different dielectric constant according to the region where the Y electrode and the Z electrode are positioned, and the dielectric of the portion where the Y electrode is positioned has a lower dielectric constant than the dielectric of the portion where the Z electrode is located.

The present invention as described above will be described in detail through one embodiment as follows.

5 is a cross-sectional view illustrating a structure of a plasma display panel according to an exemplary embodiment of the present invention. As shown in FIG. 5, a transparent electrode 12 and a bus electrode 13 formed on the upper substrate 11 are formed on top of the Y and Z electrodes. This is the case where the upper dielectric layer 24 formed thereon is formed to have a different thickness depending on the position of the electrode.

Of the two electrodes, the Y electrode formed on the lower plate 10 and the Y electrode to be subjected to the opposite discharge are applied with a negative voltage until the address discharge voltage is provided when entering the address section through the reset section, but the negative charge is accumulated even at this time. Should be doing. That is, the negative charges accumulated by the negative voltage applied to the Y electrode should not be affected as much as possible, so the thickness of the dielectric is made thick and the Z electrode, which is positively applied to the positive voltage during the address period, accumulates and maintains the negative charges as much as possible. The thickness of the dielectric formed on the side of the Z electrode is made thin. At this time, the step of the thickest dielectric layer portion and the thinnest dielectric layer portion is preferably not more than 30㎛, the formation of the dielectric layer having such a step may use a conventional process already implemented by patterning, micromachining process and the like.

Since the capacitance of the Y electrode is reduced by the thick dielectric layer formed on the Y electrode, the force of attracting or pushing the charge becomes relatively weak, thereby preventing the accumulation of positive charge at a high temperature, and the thin dielectric layer formed on the Z electrode. As a result, the capacitance of the Z electrode is increased, so that the force of attracting the charge increases, so that a large amount of negative charge can be accumulated. As a result, the wall voltage between the X-Y electrodes is kept substantially constant even at high temperatures, thereby enabling stable counter discharge, thereby increasing reliability.

This technical driving principle can be implemented in other ways, and FIG. 6 shows a case in which a dielectric layer corresponding to each electrode region is formed of a dielectric having a different dielectric constant in order to differentiate the capacitances of the Y and Z electrodes. .

As described above, the dielectric material having a low permittivity 25 is applied to the Y electrode-side dielectric layer that should have low capacitance, and the dielectric material 26 having a high permittivity is applied to the Z electrode-side dielectric layer that should have high capacitance. .

In this case, it is preferable that the dielectric constant difference of each dielectric material 25 and 26 does not exceed 10. When the top dielectric layer is formed using the dielectric materials 25 and 26 having such different dielectric constants, the dielectric layer thickness does not change. do.

Of course, the two methods shown in FIGS. 5 and 6 may be used together, and the driving conditions between the Y electrode and the Z electrode in the case of generating initial wall charges and adjusting the difference between the thickness and the dielectric constant are capacitances. The degree of change by the difference and the degree of loss of wall charge at high temperature due to the difference in capacitance can be properly adjusted. When a condition that enables stable operation of the panel is found, the reliability of the panel according to the temperature change can be improved through a relatively simple structure change. It can be greatly increased.

As described above, in the plasma display panel of the present invention, the upper dielectric of the plasma display element is formed in a different structure according to the region of the upper electrode or is formed of a dielectric having a different dielectric constant so as to change the capacitance of each electrode, such as high temperature. In the environment in which the plasma is actively moved, wall charge movement is suppressed to prevent erroneous discharge due to wall charge reduction, and as a result, the reliability of the panel is greatly increased.

Claims (5)

A plasma display panel comprising an X electrode positioned on a lower plate to apply an address voltage, a Y electrode disposed on an upper plate to face and discharge the X electrode, and a Z electrode surface discharged from the Y electrode. The structure where the Y electrode and the Z electrode have different capacitances so that the Y electrode and the Z electrode have different capacitances, or the structure where the thickness of the portion where the Y electrode is located and the portion where the Z electrode is located is different, or where the Y electrode and the Z electrode are And a top dielectric layer formed to have a different dielectric constant of the located portion. The plasma display panel of claim 1, wherein the upper dielectric layer has a thick structure where a Y electrode is positioned and a thin portion where a Z electrode is positioned. The plasma display panel of claim 2, wherein a thickness difference of the upper dielectric layer is smaller than 30 µm. According to claim 1, wherein the top dielectric layer is composed of a dielectric having a different dielectric constant according to the region where the Y electrode and the Z electrode is located, the dielectric of the portion where the Y electrode is located has a lower dielectric constant than the dielectric of the portion where the Z electrode is located. Characterized in that the plasma display panel. The plasma display panel of claim 1, wherein a difference in dielectric constant of the upper dielectric layer is less than 10.

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