KR100724145B1 - Cmos reference circuit - Google Patents

Abstract

The present invention relates to a CMOS reference circuit that can improve the dependence of the power supply voltage in a bandgap reference circuit. According to the present invention, a CMOS reference circuit includes a reference voltage generator for generating a reference voltage using a current source proportional to an absolute temperature, an amplifier unit for negative feedback to a current source proportional to the absolute temperature, and the reference voltage And a constant current generator connected between the generator and the amplifier to apply a bias to the amplifier by outputting a power supply voltage at a constant current.

Description

CMOS Reference Circuits {CMOS REFERENCE CIRCUIT}

1 is a circuit diagram illustrating a conventional CMOS band-gap reference circuit.

2 is a circuit diagram illustrating a CMOS reference circuit according to an embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

100: reference voltage generator 200: constant current generator

300: amplifier

The present invention relates to a CMOS reference circuit, and more particularly to a CMOS reference circuit that can improve the dependence of the power supply voltage in the bandgap reference circuit.

In general, a band-gap reference circuit is a circuit that provides a reference voltage of Analog to Digital Conversion (ADC) and Digital Analog Conversion (DAC), and usually tends to be on-chip inside the ADC and DAC. In this case, the band-gap reference circuit is used in the case of a precision reference because the conditions required for the reference circuit should not be sensitive to temperature and process changes.                         

Hereinafter, a conventional CMOS reference circuit will be described with reference to the accompanying drawings.

1 is a circuit diagram illustrating a conventional CMOS band-gap reference circuit.

As shown in FIG. 1, the first, second, and third PMOS transistors P1, P2, and P3, the first and second NMOS transistors N1, N2, and the first and second resistors R1 are illustrated in FIG. 1. ) R2 and first and second PNP type bipolar transistors PNP1 and PNP2.

In more detail, one end of the first, second, and third PMOS transistors P1, P2, and P3 is mutually common to receive a power supply voltage VDD, and the first and second PMOS transistors ( The other end of P1) and P2 and one end of the first and second NMOS transistors N1 and N2 are connected in series. In this case, the gate of the first PMOS transistor P1 and the gate of the second PMOS transistor P2 are commonly connected, and the gates of the first and second PMOS transistors P1 and P2 that are commonly connected are the first. It is connected to one end of the NMOS transistor N1, and the gates of the commonly connected first and second PMOS transistors P1 and P2 are connected to the gates of the third PMOS transistor P3.

The other end of the first NMOS transistor N1 and one end of the first resistor R1 are connected, and the other end of the first resistor R1 and the other end of the second NMOS transistor N2 are first and second. It is connected in series to the emitter of the PNP type bipolar transistor PNP1 (PNP2). In this case, the gates of the first and second NMOS transistors N1 and N2 are commonly connected to one end of the second NMOS transistor N2.

The other end of the third PMOS transistor P3 is connected to one end of the second resistor R2, and the other end of the second resistor R2 is connected to the emitter of the third PNP type bipolar transistor PNP3. The base and the collector of the first, second, and third PNP type bipolar transistors PNP1, PNP2, and PNP3 are connected to the ground voltage VGG.

The reference voltage Vref is output from the other end of the third PMOS transistor P3 and one end of the second resistor R2.

Here, as a current source proportional to the temperature of the circuit configured as described above, the value of this current is given as follows.

(Where n indicates that the first PNP type transistor PNP1 is n of the second PNP type transistor PNP2)

In this case, V _BE2 is the voltage at the base-emitter stage of the second PNP type bipolar transistor PNP2, and V _BE1 is the voltage at the base-emitter stage of the first PNP type bipolar transistor PNP1.

As above, the current I _PTAT becomes proportional to the absolute temperature T.

However, in the conventional band-gap reference circuit configured as described above, there is a problem in that the current source of the first and second NMOS transistors is changed differently depending on the process change, irrespective of the power supply voltage.

The present invention has been made in order to solve the above problems, and the negative feedback is applied to the current source that is proportional to the absolute temperature (PTAT) increased with the power supply voltage, thereby reducing the dependence of the power supply voltage. The objective is to provide a CMOS reference circuit that can reduce the number of bipolar transistors.

The CMOS reference circuit of the present invention for achieving the above object comprises a reference voltage generator for generating a reference voltage using a current source proportional to the absolute temperature, an amplifier unit for negative feedback to the current source proportional to the absolute temperature; And a constant current generator connected between the reference voltage generator and the amplifier to output a power supply voltage at a constant current to apply a bias to the amplifier.

Hereinafter, a CMOS reference circuit of the present invention will be described in detail with reference to the accompanying drawings.

2 is a circuit diagram illustrating a band-gap reference according to an embodiment of the present invention.

As shown in Fig. 2, the first, second, third, fourth, fifth, and sixth PMOS transistors P1, P2, P3, P4, P5, P6, and the first and second A reference voltage generator 100 having a second resistor R1 (R2) and first and second PNP type bipolar transistors PNP1 and PNP2; and a seventh, eighth, and ninth PMOS transistors P7 ( P8) (P9), the constant current generator 200 including the first and second NMOS transistors N1 and N2, and the tenth, eleventh, twelfth and thirteenth PMOS transistors P10 and P11. And an amplifier unit 300 including (P12) (P13) and third, fourth, and fifth NMOS transistors N3, N4, and N5.                     

In detail, the reference voltage generator 100 receives one end of the first, second, and third PMOS transistors P1, P2, and P3 so as to receive a power supply voltage VDD. The other ends of the first, second and third PMOS transistors P1, P2 and P3 and one end of the fourth, fifth and sixth PMOS transistors P4, P5 and P6 are connected in series. . In this case, gates of the first, second, and third PMOS transistors P1, P2, and P3 are commonly connected to each other, and the fourth, fifth, and sixth PMOS transistors P4, P5, and P6 are connected to each other. Gates are also commonly connected to each other.

The other end of the fourth PMOS transistor P4 and one end of the first resistor R1 are connected by a first node Nd1, and the other end of the first resistor R1 and the fifth PMOS transistor P5. The other end of is connected in series to the emitters of the first and second PNP type bipolar transistors PNP1 and PNP2, respectively. At this time, the base and the collector of the first and second PNP type bipolar transistors PNP1 and PNP2 are connected to the ground voltage VGG.

The other end of the fifth PMOS transistor P5 is connected to one end of the second resistor R2 by the second node Nd2, and the other end of the sixth PMOS transistor P6 and the second resistor R2. The other end of is connected to output a reference voltage (Vref).

The constant current generator 200 receives one end of the seventh and ninth PMOS transistors P7 and P9 in common and receives the power supply voltage VDD, and the other end and the eighth end of the seventh PMOS transistor P7. One end of the PMOS transistor P8 is connected in series, and the other end of the eighth PMOS transistor P8 and one end of the first NMOS transistor N1 are connected in series. In this case, the gate of the first NMOS transistor N1 is connected to the other end of the eighth PMOS transistor P8 and one end of the first NMOS transistor N1.                     

The other end of the ninth PMOS transistor P9 and one end of the second NMOS transistor N2 are connected in series, and a gate of the ninth PMOS transistor P9 is connected to the second NMOS transistor N2.

The gate of the seventh PMOS transistor P7 is commonly connected to the gate of the third PMOS transistor P3, and the gates of the eighth and ninth PMOS transistors P8 and P9 are the sixth PMOS transistor. Commonly connected to the gate of P6, the gates of the first and second NMOS transistors N1 and N2 are commonly connected to each other. In this case, the other ends of the first and second NMOS transistors N1 and N2 are connected to a ground power source.

The amplifier 300 receives one end of the tenth and eleventh PMOS transistors P10 and P11 in common with the power supply voltage VDD, and the other end of the tenth PMOS transistor P10 and the twelfth PMOS transistor. One end of P12 is connected in series, and the other end of the twelfth PMOS transistor P12 and one end of the third NMOS transistor N3 are connected in series by the third node Nd3.

The other end of the eleventh PMOS transistor P11 and one end of the thirteenth PMOS transistor P13 are connected in series, and the other end of the thirteenth PMOS transistor P13 and one end of the fourth NMOS transistor N4 are fourth nodes. It is connected in series by (Nd4).

The other end of the third and fourth NMOS transistors N3 and N4 is commonly connected to one end of the fifth NMOS transistor N5, and the other end of the fifth NMOS transistor N5 is connected to the ground voltage VGG. do.

Here, the gates of the tenth and eleventh PMOS transistors P10 and P11 are commonly connected to each other and connected to a fourth node Nd4, and the gates of the twelfth and thirteenth PMOS transistors P12 and P13 are connected to each other. It is connected in common to the gate of the ninth PMOS transistor P9. The gate of the seventh PMOS transistor P7 is connected to the third node Nd3, and the gate of the fifth NMOS transistor N5 is commonly connected to the gate of the second NMOS transistor N2.

On the other hand, after a plus voltage is input to the gate of the third NMOS transistor N3 and a minus voltage is input to the gate of the fourth NMOS transistor N4, the first node Nd1 is input. The negative voltage is connected to the plus voltage, and the positive voltage is connected to the second node Nd2.

The amplifier unit 300 receives the current of the constant current generator 200 to the fifth NMOS transistor N5. In addition, the positive input of the amplifier 300 is connected to the emitter terminal of the second PNP type bipolar transistor PNP2 of the PTAT current source to output the voltage V2 of the second node Nd2, and the amplifier 300 A negative input of outputs the voltage V1 of the first node Nd1 via the emitter and the first resistor R1 of the first PNP type bipolar transistor PNP1 of the PTAT current source.

Accordingly, the amplifier unit 300 serves to equalize the output voltage V1 of the first node Nd1 and the output voltage V2 of the second node Nd2 of the reference voltage generator 100. That is, the amplifier unit 300 applies negative feedback to the reference voltage generator 100.

As described above, according to the CMOS reference circuit of the present invention, if the negative feedback is applied to the current source PTAT which is proportional to the absolute temperature using the amplifier unit, the dependency of the power supply voltage can be reduced, so it is irrelevant to the power supply voltage. One ideal current source can be made.

And the number of bipolar transistors can be reduced.

Claims (6)

In CMOS reference circuits, A reference voltage generator for generating a reference voltage using a current source proportional to an absolute temperature; An amplifier unit for negative feedback to a current source proportional to the absolute temperature; And a constant current generator connected between the reference voltage generator and the amplifier to output a power supply voltage at a constant current to bias the amplifier. The method of claim 1, wherein the reference voltage generator, First to third PMOS transistors having a current mirror structure for receiving the power supply voltage; Fourth to sixth PMOS transistors each connected in series with the first to third PMOS transistors and having a current mirror structure; A first resistor and a first PNP type bipolar transistor connected in series between a first node connected to one side of the fourth PMOS transistor and a ground voltage; A second PNP type bipolar transistor connected between a second node connected to one side of the fifth PMOS transistor and a ground voltage; And a second resistor connected between the second node and a third node for outputting a reference voltage. The third and sixth PMOS transistors are connected in series between a power supply voltage and the third node, and a negative feedback voltage from the amplifier unit is applied to the first node and the second node, respectively. Reference circuit. The method of claim 2, And the gates of the first, second, and third PMOS transistors are commonly connected to each other, and the gates of the fourth, fifth, and sixth PMOS transistors are also commonly connected to each other. The method according to claim 1 or 2, wherein the constant current generating unit, A seventh and eighth PMOS transistor and a first NMOS transistor connected in series between the power supply voltage and a ground voltage; A ninth PMOS transistor and a second NMOS transistor connected in series between the power supply voltage and the ground voltage; And the first NMOS transistor has a current mirror structure with the second NMOS transistor. The method of claim 4, wherein And the amplifier unit comprises a current mirror differential amplifier. The method of claim 1, A minus voltage is applied to the first node, And a positive voltage is applied to the second node.

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