KR100704218B1 - Data transfer unit - Google Patents

Abstract

SUMMARY OF THE INVENTION An object of the present invention is to provide a data transfer apparatus that normally operates as a single buffer and can operate in a double buffer manner as needed to realize high-speed data transfer. To this end, the data transmission apparatus of the present invention includes a first channel unit for performing a first data transmission using a first buffer as a relay in a first operation mode, and first data using a second buffer as a relay in a first operation mode. And a second channel unit for performing a second data transfer different from the transfer, and sequentially selecting a plurality of buffers including at least a first buffer and a second buffer in a second operation mode, and reading the data read from the transfer source. By sequentially transferring the selected buffers to the transfer destination, the readout data from the transfer source and the data write to the transfer destination are executed in parallel.

Description

DATA TRANSFER UNIT {DATA TRANSFER UNIT}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention generally relates to data transfer apparatus, and more particularly, to a data transfer apparatus for performing DMA transfer of data in a dual bus system.

In computer systems, direct memory access (DMA) transfer, which directly executes data transfer between two devices without going through the CPU, is an indispensable technique for achieving high system performance.

A computer system generally consists of a plurality of devices and a bus connecting them. A device connected to the bus can be divided into a device called a master that outputs a read or write request and a device called a slave that receives a request output by the master. The DMAC (DMA Controller) and CPU that control the direct memory access (DMA) transfer are the master devices on the side that output the request.

DMAC performs data transfer directly between slave devices without going through the CPU. In the bus system, each slave device is specified by using an address, and a position (for example, each address in the memory device) in each slave device is specified. 1 is an address map illustrating the allocation of slave devices in an address space.

DMAC outputs a Read request to the slave device and reads information from a specific location within the slave device specified by the address. DMAC then issues a Write request and sends the read information to a separate slave device. In this way, the DMAC outputs read and write requests, thereby realizing data transfer between slave devices.

2 is a diagram illustrating a double buffer data transfer operation in a dual bus system.

The dual bus system of FIG. 2 includes a DMAC 10, a bus 11, a bus 12, a RAM 13, a ROM 14, a video display 15, and a Universal Asynchronous Receiver Transmitter (UART) 16. do. DMAC 10 is the master device, and RAM 13, ROM 14, video display 15 and UART 16 are slave devices. The RAM 13 and the ROM 14 are connected to the DMAC 10 via the bus 11, and the video display 15 and the UART 16 are connected to the DMAC 10 via the bus 12.

 The DMAC 10 includes two buffers (Buffer1) 21 and a buffer (Buffer2) 22. For example, the DMA data transfer operation from the RAM 13 to the video display 15 will be described below. 3 is a timing diagram showing an operation of transferring DMA data from the RAM 13 to the video display 15.

The DMAC 10 first sends a read request to the RAM 13, and stores the data received from the RAM 13 in the buffer 21 as a result of the read request. This Read operation is represented as RAM → buffer1 in FIG. When this Read operation is completed, the DMAC 10 writes the information stored in the buffer 21 to the video display 15. This Write operation is represented as buffer1? Video in FIG.

Since the configuration of FIG. 2 is a double buffer system, another buffer 22 can be used simultaneously with the buffer 21. In other words, in parallel with the recording from the buffer 21 to the video display 15, the next data is read from the RAM 13 and stored in the buffer 22 (RAM → buffer2). The data stored in the buffer 22 is recorded in the video display 15 in parallel with reading data from the RAM 13 and storing it in the buffer 21 (buffer 2? Video).

As described above, in the double buffer system data transfer in the dual bus system, by using two buses and two buffers, the transfer speed between slave devices can be doubled as compared to the case of the single buffer using one buffer. Can be.

In the double buffer system described above, twice as much information is required to be stored as compared with the single buffer system, which consumes a large amount of chip area. Also, among the slave devices generally present in the system, there are not many devices requiring the transmission performance that is likely to be realized for the first time by the double buffer method. Accordingly, the double buffer system is limited in that it can enjoy the merit of high speed of data transfer, compared with the disadvantage of requiring a large chip area.

In view of the above, it is an object of the present invention to provide a data transfer apparatus that normally operates as a single buffer and operates as a double buffer scheme as necessary, thereby enabling high-speed data transfer.

Patent Document 1: Japanese Patent Application Laid-open No. Hei 1-229353

Patent Document 2: Japanese Patent Laid-Open No. 64-78351

A data transmission apparatus according to the present invention includes a first channel unit for performing a first data transfer using a first buffer as a relay in a first operation mode, and the first buffer using a second buffer as a relay in the first operation mode. A second channel unit for performing a second data transfer different from the data transfer, and sequentially selecting a plurality of buffers including at least the first buffer and the second buffer in a second mode of operation, and reading from the transfer source The data is transferred to a transfer destination using the sequentially selected buffer as a relay, so that data reading from the transfer source and data writing to the transfer destination are performed in parallel.

In the data transfer apparatus, when high speed data transfer is not required, each channel operates as a separate channel in the first operation mode to realize each data transfer. When high speed data transfer is necessary, the data read operation is executed in parallel with the data read operation and the data write operation in the second operation mode. Therefore, when high speed data transfer is not required, efficient data transfer is realized as a plurality of channels of a single buffer system, and when high speed data transfer is required, a single channel of a double buffer system is realized and high speed data transfer is achieved. Run As a result, while reducing the disadvantages of the double buffer method, it is possible to enjoy the merit of the high speed of data transfer of the double buffer method.

1 is an address map illustrating the allocation of slave devices in an address space.

2 is a diagram illustrating a double buffer data transfer operation in a dual bus system.

3 is a timing diagram illustrating an operation of transferring DMA data from a RAM to a video display.

4 is a diagram for explaining a DMA controller (data transfer apparatus) according to the present invention.

Fig. 5 is a timing diagram showing a double buffer data transfer operation from RAM to video display.

FIG. 6 is a diagram for explaining an operation in which a first channel executes DMA data transfer from a RAM to a UART, and a second channel executes DMA data transfer from a RAM to a video display.

FIG. 7 is a timing diagram showing a data transfer operation by the two channels shown in FIG.

FIG. 8 is a diagram showing an embodiment of a configuration in which two channels operate as one channel to realize a double buffer data transfer.

9 is a timing diagram illustrating a data transfer operation of FIG. 8.

FIG. 10 is a diagram showing another embodiment of a configuration in which two channels operate as one channel to realize double buffer data transfer.

11 is a timing diagram illustrating a data transfer operation of FIG. 8.

12 is a diagram for explaining another embodiment of the high speed data transfer according to the present invention.

Fig. 13 is a timing diagram showing a double buffer data transfer operation from RAM to video display.

EMBODIMENT OF THE INVENTION Below, the Example of this invention is described in detail using an accompanying drawing.

4 is a diagram for explaining a DMA controller (data transfer apparatus) according to the present invention.

The DMA controller (DMAC) 30 according to the present invention is used in a dual bus system as shown in FIG. The bus system of FIG. 4 includes a DMAC 30, a bus 11, a bus 12, a RAM 13, a ROM 14, a video display l5, and a UART 16. The RAM 13 and the ROM 14 are connected to the DMAC 30 via the bus 11, and the video display 15 and the UART 16 are connected to the DMAC 30 via the bus 12.

  In the DMAC 30, a plurality of channels (channel units) 31-1 to 31-N are mounted, and one buffer is provided for each channel. For example, a buffer 32-1 is provided in the channel 31-1, and a buffer 32-2 is provided in the channel 31-2. In each channel of the DMAC, two registers S and D are provided for setting an address. The address indicating the position in the slave device whose register S is the transfer source is stored, and the address indicating the position in the slave device whose register D is the transfer destination.

In the example of FIG. 4, both of the channel 31-1 and the channel 31-2 perform DMA data transfer from the RAM 13 to the video display 15. As a result, the channels 31-1 and 31-2 virtually operate as one channel, and perform double buffer data transfer using the two buffers 32-1 and 32-2.

FIG. 5 is a timing diagram showing a double buffer data transfer operation from the RAM 13 to the video display 15. As shown in FIG.

First, the channel 31-1 of the DMAC 30 sends a read request to the RAM 13, and stores the data received from the RAM 13 as a result of the read request in the buffer 32-1. This Read operation is represented as RAM → buffer1 in FIG. When the Read transfer is completed, an odd read completion signal is sent from the channel 31-1 to the channel 31-2, and the channel 31-2 is instructed to start data transfer (arrow 1 and in Fig. 5). Arrow 3). At the same time, channel 31-1 starts the operation of recording the information stored in buffer 32-1 to video display 15 (arrow 2 in FIG. 5). This Write operation is represented as buffer1? Video in FIG.

The channel 31-2 detects the assertion of the odd read completion signal, and sends a read request to the RAM 13. As a result, the next data is read from the RAM 13 and stored in the buffer 32-2 (RAM → buffer2). This operation is performed in parallel with the operation (buffer? Video) in which the channel 31-1 writes the information stored in the buffer 32-1 to the video display 15. When the transfer from the RAM 13 to the buffer 32-2 is completed, the channel 31-2 issues a good read completion signal and instructs the channel 31-1 to start data transfer (Fig. 5). Arrows 4 and 7). The channel 31-1 starts the read operation by outputting the next Read request to the RAM 13 at the completion of the write (arrow 6) and the assertion of the even read completion signal (arrow 7).

In parallel with the channel 31-1 reading data from the RAM 13 and storing it in the buffer 32-1 (RAM → Buffer1), the channel 31-2 is the data stored in the buffer 32-2. Are recorded on the video display 15 (buffer 2? Video).

In this way, the two channels alternately use their own buffers, virtually acting as one channel to perform double buffer data transfer. As a result, high transmission performance can be realized if necessary.

In addition, when a round robin or rotation priority is used for priority control for determining which channel to transmit to the bus, the data transmission using two channels as one channel is performed by another channel. You can get twice as much priority as transmission. Therefore, there is an advantage that the data transfer can be reliably doubled in the case of data transfer with respect to the slave device which must secure a high transfer rate.

In the DMAC 30 shown in Fig. 4, two channels are virtually operated as one channel as necessary to execute a double buffer type data transfer. When high speed data transfer is not required, each channel executes each data transfer operation as a separate channel.

6 shows that channel 31-1 executes DMA data transfer from RAM 13 to UART l6, and channel 31-2 executes DMA data transfer from RAM 13 to video display 15. FIG. It is a figure for demonstrating the operation | movement.

FIG. 7 is a timing diagram illustrating a data transmission operation by two channels shown in FIG. 6.

First, the channel 31-1 of the DMAC 30 outputs a read request to the RAM 13. As a result of the Read request, the obtained information is stored in the buffer 32-1 of the channel 31-1 (RAM → CHl). Thereafter, the channel 31-1 outputs a write request to the UART 16, and writes the contents of the buffer 32-1 to the UART 16 (CH1 to UART).

In parallel with the channel 31-1 performing a write operation to the UART 16, the channel 31-2 outputs a Read request to the RAM 13, and stores the read information in the buffer 32-2. (RAM → CH2). The channel 31-2 then writes the contents of the buffer 32-2 to the video display 15 (CH2? Video).

In this way, when high-speed data transfer is not necessary, each channel operates as a separate channel to realize each data transfer. If high-speed data transfer is required, as described above, the two channels operate virtually as one channel, thereby performing double buffer data transfer. Therefore, when high speed data transfer is not required, efficient data transfer is realized as a plurality of channels of a single buffer system, and when high speed data transfer is required, a single channel of a double buffer system is realized and high speed data transfer is achieved. Run In this way, while reducing the disadvantages of the double buffer method, it is possible to enjoy the merit of the high speed of data transfer of the double buffer method.

FIG. 8 is a diagram showing an embodiment of a configuration in which two channels operate as one channel to realize double buffer data transfer.

In FIG. 8, a plurality of channels 31-1 to 31-N are mounted in the DMAC 30, and one buffer is provided for each channel. In each channel, a transfer source register 41, a transfer destination register 42, an address increment module 43, and an address increment module 44 are provided. The transfer source register 41 stores the address of the transfer source of the data transfer executed by the channel, and the transfer destination 42 stores the address of the transfer destination of the data transfer executed by the channel. The address increment module 43 updates the contents of the transfer source register 41 by +2. The address increment module 44 also updates the content of the transfer destination 42 by +2.

The DMAC transfers data while incrementing the transfer source address and transfer destination register. Normally, the address is incremented (+1) by the number of transfer data sizes read or written in one buffer transfer operation. In contrast, in the embodiment of Fig. 8, two channels each increment an address (+2) by twice the transfer size.

In the configuration of this embodiment, the double buffer operation can be realized by only slightly modifying the address increment module without substantially changing the configuration of the controller controlling the buffer. In addition, the address increment module is also capable of executing +1 address increments and switching between +1 increments and +2 increments in order to support single buffer data transfer. .

9 is a timing diagram illustrating a data transfer operation of FIG. 8.

The contents of the transfer source register 41 of the channel 31-1 are represented as Src1, and the contents of the transfer destination register 42 of the channel 31-1 are represented as Dest1. The contents of the transfer source register 41 of the channel 31-2 are represented as Src2, and the contents of the transfer destination register 42 of the channel 31-2 are represented as Dest2.

In FIG. 9, the flow of data with respect to the read and write operations is the same as in FIG. The following describes the read and write operations in association with address generation. First, the channel 31-1 performs a read operation on the address 0 of Src1 (RAM → Buffer1). In response to the completion of this Read operation (arrow 1), Src1 is updated with the addition result 2 by adding 2 to the value of Src1. Similarly, the channel 31-2 performs a read operation on the address 1 of Src2 (RAM → Buffer2), and in response to its completion (arrow 2), adds 2 to the value of Src2 and adds the result (3). Update Src2 with

In parallel with the read operation of the channel 31-2, the channel 31-1 performs a write operation on the address 1000 of Dest1 (Buffer → Video). In response to the completion of the Write operation of the channel 31-1 (arrow 3), Dest1 is updated with the addition result 1002 by adding 2 to the value of Dest1. Similarly, in response to the completion of the write operation (Buffer2? Video) of the channel 31-2 (arrow 4), 2 is added to the value of Dest2 to update Dest2 with the addition result 1003.

FIG. 10 is a diagram showing another embodiment of the configuration in which two channels operate as one channel to realize double buffer data transfer. In Fig. 10, the same components as in Fig. 8 are referred to by the same numerals, and the description thereof is omitted.

In the embodiment of Fig. 10, only the channel 31-1 is configured to output an address. Therefore, the address increment module 43 +1 updates the contents of the transfer source register 41, and the address increment module 44 updates the contents of the transfer destination 42 by +1. That is, the address is incremented (+1) by the number of transfer data sizes read or written in one buffer transfer operation.

In this way, the channel 31-1 and the channel 31-2 are buffered 32-1 while addressing using only the transfer source register 41 and the transfer destination register 42 of the channel 31-1. And buffer 32-2 are used to realize double buffer data transfer. In this embodiment, it is necessary to configure the DMAC 30 so that the channel 31-1 can control both buffers, but it is not necessary to provide a +2 increment configuration in the address increment module.

11 is a timing diagram illustrating a data transfer operation of FIG. 8.

First, the channel 31-1 performs a read operation on the address 0 of Src1 (RAM → Buffer1). In response to the completion of this Read operation (arrow 1), Src1 is updated with the addition result 1 by adding 1 to the value of Src1. Next, the channel 31-2 performs a read operation on the address 1 of Src1 (RAM → Buffer2). In response to the completion (arrow 2), the channel 31-1 adds 1 to the value of Src1 and updates Src1 with the addition result (2). This update may be performed in response to the even read completion signal from the channel 31-2 to the channel 31-1.

In parallel with the read operation of the channel 31-2, the channel 31-1 performs a write operation on the address 1000 of Dest1 (Buffer → Video). In response to the completion of the Write operation of the channel 31-1 (arrow 3), 1 is added to the value of Dest1 to update Dest1 with the addition result 1001. Next, when the write operation (Buffer2? Video) of the channel 31-2 is completed, in response to this, the even-write completion signal is supplied from the channel 31-2 to the channel 31-1. In response to the assertion of this even-recording completion signal (arrow 4), the channel 31-1 adds 1 to the value of Dest1 and updates Dest1 with the addition result 1002.

12 is a diagram for explaining another embodiment of the high speed data transfer according to the present invention.

The DMA controller DMAC 50 according to the present invention is used in a dual bus system as shown in FIG. The bus system of FIG. 12 includes a DMAC 50, a bus 11, a bus 12, a RAM 13, a video display 15, a UART 16, and a CPU 60. The RAM 13 is connected to the DMAC 50 via the bus 11, and the video display 15 and the UART 16 are connected to the DMAC 50 via the bus 12.

In the DMAC 50, a plurality of channels 51-1 to 51-N are mounted, and one buffer number queue is provided for each channel. For example, a buffer number queue 52-1 is provided in the channel 51-1, and a buffer number queue 52-2 is provided in the channel 51-2. Besides the channels, buffers 53-1 to 53-N are provided. Further, valid flags 54-1 to 54-N are provided to indicate whether or not the corresponding buffers 53-1 to 53-N are available.

FIG. 13 is a timing diagram showing a high speed data transfer operation from the RAM 13 to the video display 15. FIG.

First, the channel 51-1 checks the valid flags 54-1 to 54-N, finds an empty buffer, and stores the buffer number Buffer1 in the buffer number queue 52-1. The data read from the RAM 13 is also stored in the buffer (the buffer of the last number in the queue) (RAM → Buffer1). Subsequently, similarly, the channel 51-1 checks the valid flags 54-1 to 54-N, finds an empty buffer, and stores the buffer number Buffer2 in the buffer number queue 52-1. do. In addition, after reading from the RAM 13, the data is stored in the corresponding buffer (the buffer at the end of the queue) (RAM → Buffer2).

When a recording request arrives from the video display 15, the channel 51-1 writes to the video display 15. At this time, data is sent from the buffer indicated by the number (the head number of the queue) output from the buffer number queue 52-1 to the video display 15 (Buffer1 to Video). As shown in Fig. 13, the channel 51-1 can execute data reading from the RAM 13 and data writing to the video display 15 in parallel.

In the example of FIG. 13, the channel 51-1 uses Buffer1, Buffer2, and Buffer3 in order as a buffer, uses Buffer1 again, and then reuses Buffer1 after using Buffer2. In the data transmission in the present embodiment, since a valid flag is checked and a buffer that can be used at any time is specified, the buffer to be used varies depending on the situation.

In addition, each channel may independently acquire a buffer and perform respective data transfer operations.

In the above embodiment, a plurality of buffers are comprehensively managed, and each channel obtains and uses the buffers as necessary. In this method, the buffer control is complicated compared with the method of Fig. 8 or 10, but if two buffers are available, the same effect as that of the double buffer type data transfer can be obtained.

It is also possible to use two or more buffers if available. Therefore, even if transmission from the transmission source to the DMAC 50 is interrupted by the access of another master or the like during data transmission, data stored in the plurality of buffers can be continuously sent to the transmission destination. That is, as shown in FIG. 13, for example, when the CPU 60 accesses the RAM 13 (RAM → CPU) is executed a plurality of times, and the transfer from the RAM 13 to the DMAC 50 is delayed several times. In addition, the possibility of delaying data transmission to the video display 15 can be reduced.

The configuration of this embodiment has a problem in that read transmission of a separate channel cannot be performed if a channel secures all buffers. In general, the operation from the transmission request to the data reception is often limited within a predetermined time, and in order to solve the problem, it is a simple solution to control one buffer for each channel. In this case, the operation is essentially the same as that of FIGS. 4 and 6.

As mentioned above, although this invention was demonstrated based on the Example, this invention is not limited to the said Example, A various deformation | transformation is possible within the range of a claim.

Claims (10)

A first channel unit executing a first data transfer using the first buffer as a repeater in a first operation mode, A second channel unit configured to execute a second data transmission different from the first data transmission by using a second buffer as a relay in the first operation mode, By sequentially selecting a plurality of buffers including at least the first buffer and the second buffer in a second mode of operation, and transferring data read from one source to one destination using the sequentially selected buffer as a relay, Configured to execute reading of data from the one transfer source and writing of data to the one transfer destination in parallel, The first operation mode in which the first channel unit and the second channel unit respectively perform data transmission operations as separate channels, and at least the first channel unit and the second channel unit are integrated to virtually one And said second mode of operation for operating as a channel to execute one data transfer is switchable. The method of claim 1, wherein in the second operation mode, the first buffer and the second buffer are alternately selected, and data read from the transfer source is transferred to the transfer destination using the alternately selected buffer as a relay. Simultaneously performing a data read operation from the transfer source to the first buffer and a data write operation from the second buffer to the transfer destination, and at the same time, read data from the transfer source to the second buffer; And a data write operation from the first buffer to the transfer destination in parallel. The data transmission apparatus of claim 2, wherein the first channel and the second channel are jointly operated in the second operation mode to transmit data as a single channel. The data transmission apparatus according to claim 3, wherein in the second operation mode, the first channel and the second channel notify the counterpart of completion of the read operation when the data read operation from the transfer source is completed. The method of claim 4, wherein each of the first channel unit and the second channel unit, A transfer source register for storing an address indicating an access position of the transfer source; A transfer destination register for storing an address indicating an access position of the transfer destination; A first address increment module for incrementing an address stored in said transfer source register; A second address increment module for incrementing an address stored in the transfer register; In the second mode of operation, the first address increment module increments the address to access every other access location of the transmission source, and the second address increment module determines an access location of the destination. Incrementing the address to access every other, and alternately designating an access location between the source and destination registers of the first channel unit and the source and destination registers of the second channel unit. Characterized in that the data transmission device. The method of claim 4, wherein each of the first channel unit and the second channel unit, A transfer source register for storing an address indicating an access position of the transfer source; A transfer destination register for storing an address indicating an access position of the transfer destination; A first address increment module for incrementing an address stored in said transfer source register; A second address increment module for incrementing an address stored in the transfer register; In the second mode of operation, the first address increment module of the first channel increments an address to sequentially access the access positions of the transmission source one by one, and the second address increment of the first channel The retention module increments the address so as to access the access positions of the transfer destination one by one, and transmits data by designating an access position by the transfer source register and the transfer destination register of the first channel unit. Data transmission device. 7. The data transmission apparatus as claimed in claim 6, wherein the second channel unit notifies the first channel unit of the completion of the recording operation when the data recording operation to the transfer destination is completed. The method of claim 1, wherein the first channel unit includes a first queue for sequentially storing information for specifying a buffer, and the second channel unit includes a second queue for sequentially storing information for specifying a buffer. In the second operation mode, the first channel unit sequentially selects available buffers from the plurality of buffers, sequentially stores information specifying the selected buffers in the first queue, and sequentially stores the first queue. And reading data from the transfer source into the buffer designated by the last information of the data and writing the data from the buffer designated by the information at the head of the queue to the transfer destination in parallel. A first channel unit, A second channel unit, The first channel unit, The first buffer, A first transfer source register indicating an access position of the transfer source, A first transfer destination register indicating an access location of a transfer destination, and configured to transfer data from a transfer source represented by said first transfer register to a transfer destination represented by said first transfer register, using said first buffer as a relay; , The second channel unit, The second buffer, A second transfer source register indicating a transfer location of the transfer source, A second transfer destination register indicating an access location of a transfer destination, configured to transfer data from a transfer source represented by said second transfer register to a transfer destination represented by said second transfer register, using said second buffer as a relay, By performing the cooperative operation of the first channel unit and the second channel unit, data read operation from one transfer source to the first buffer and data write operation to one transfer destination from the second buffer are performed in parallel. At the same time, the data read operation from the one transfer source to the second buffer and the data write operation from the first buffer to the one transfer destination are performed in parallel, A first operation mode in which the first channel unit and the second channel unit respectively perform data transmission operations as separate channels, and at least the first channel unit and the second channel unit are integrated to virtually one channel And said second mode of operation for operating as one data transfer is switchable. Multiple buffers, A first channel unit including a first queue for sequentially storing information specifying a buffer; A second channel unit including a second queue for sequentially storing information specifying a buffer, The first channel unit sequentially selects an available buffer from among the plurality of buffers, sequentially stores information specifying the selected buffer in the first queue, and stores the information specifying the selected buffer in a buffer designated by the last information of the queue. Reading out data from the transfer source and writing data from the buffer designated by the head information of the queue to the transfer destination in parallel, wherein the first channel unit and the second channel unit respectively transmit data as separate channels. And a first operation mode for executing the operation and at least the first channel unit and the second channel unit are integrated to operate as a single channel to perform one data transmission. Data transmission device.

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