JPH05250306A - Dma controller - Google Patents

Abstract

PURPOSE:To obtain multi-channel constitution with a small circuit scale by enabling one arithmetic means to perform the address addition or subtraction of all channels and also count words of transfer data. CONSTITUTION:Address registers 23-25 which are provided corresponding to the channels CH0-CH2 are stored with addresses of a memory at a data transfer source or destination and a CPU sets the respective address registers 23-25. Further, registers 26-28 for the number of transfer data words which are provided corresponding to the channels CH0-CH2 are stored with the number of words of the transfer data, and the CPU sets those registers 26-28 as well. Then one computing element 33 performs the addition or subtraction of the addresses and counts the number of the words of the transfer data. Thus, the registers 23-28 are provided for the respective channels CH0-CH2 instead of providing a counter, and the computing element 33 performs the address addition and counts the words of the transfer data as to all the channels.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a facsimile machine, etc.
In a data processing system that processes a large amount of data centering on a CPU (central processing unit),
A data transfer path independent of the data transfer path between the peripheral circuit section and the memory via the PU is provided between the peripheral circuit section and the memory, and the data is directly transferred between the peripheral circuit section and the memory. Data transfer control device used to control this, so-called DMA (direct memory acces).
s) Concerning the controller.

[0002]

2. Description of the Related Art Conventionally, as a data processing system configured by providing a DMA controller in addition to a CPU, for example, there is a facsimile apparatus, and FIG.

In the figure, 1 is a CPU, 2 is a memory, and 3 is a DM.
A controller, 4 is a scanner unit for reading an image,
Reference numeral 5 is an image processing unit that processes an image read by the scanner unit 4, 6 is a printer unit that prints an image, 7 is a compression / decompression unit that compresses data to be transmitted and decompresses received data, and 8 is data. It is a communication control unit that controls the transmission and reception of.

In such a facsimile apparatus, in order to efficiently process data, the DMA controller 3 is used without the CPU 1 to directly connect between the memory 2 and the peripheral circuit section such as the scanner section 4. Data may be transferred.

Here, the DMA controller 3 is conventionally
It was constructed so that a part thereof is shown in FIG. In the figure,
9, 10, 11 are channels CH0, CH1, C respectively
This is a transfer request signal input terminal provided corresponding to H2.

In this example, the channel CH0 is used in the scanner section 4, and the transfer request signal input terminal 9 is used.
A transfer request signal RQ0 from the scanner unit 4 is input to the. The channel CH1 is used by the image processing unit 5, and the transfer request signal RQ1 from the image processing unit 5 is input to the transfer request signal input terminal 10. The channel CH2 is used in the printer unit 6, and the transfer request signal R from the printer unit 6 is input to the transfer request signal input terminal 11.
Q2 is input.

A selector 12 selects a transfer request signal to be taken in based on a preset priority when a plurality of transfer request signals are simultaneously input.

Further, reference numerals 13, 14, and 15 are counters for addresses provided corresponding to the channels CH0, CH1, and CH2, respectively.
3, 14, and 15 are set by the CPU 1 and operate so as to add or subtract the address for each transfer of the address.

Reference numerals 16, 17, and 18 are counters for counting the number of words (byte number) of transfer data provided corresponding to the channels CH0, CH1, and CH2, respectively. , 17, 1
8 is set by the CPU 1.

A selector 19 selects a counter for transferring an address to the memory 2. The selector 19 is controlled so as to select a counter for an address of a channel to which a transfer request signal is input. It

[0011]

As described above, the conventional D
In the MA controller, two counters are provided for each channel, that is, an address counter and a transfer data word number counter. Therefore, if the number of channels is increased, the circuit scale becomes large and the price is reduced. There was a problem that it would be expensive.

SUMMARY OF THE INVENTION In view of the above points, an object of the present invention is to provide a DMA controller which can realize a multi-channel system with a circuit scale smaller than that of the conventional one and can reduce the cost.

[0013]

A DMA controller according to the present invention is provided with a register for storing an address of a transfer destination or a transfer source of transfer data and a register for storing the number of words of the transfer data for each channel. ,
One arithmetic unit shared by all channels is provided, and the arithmetic unit is configured to add or subtract addresses for all channels and count the number of words of transfer data.

[0014]

In the present invention, a register for storing the transfer destination or transfer source address of transfer data and a register for storing the number of words of transfer data are provided for each channel. Also, the number of words in the transfer data is counted by one computing means.

Here, the circuit scale of the register can be made significantly smaller than that of the counter. Therefore, according to the invention, 2 for each channel.
The circuit scale can be reduced as compared with the conventional DMA controller having the individual counters.

[0016]

1 is a circuit diagram showing a part of an embodiment of the present invention, and FIG. 2 is a time chart for explaining the operation of the embodiment of the present invention. In FIG. 1, 20, 21, 22
Are transfer request signal input terminals provided corresponding to the channels CH0, CH1, and CH2, respectively.

Here, for example, when this embodiment is used in the facsimile apparatus shown in FIG. 3, channel CH0 is used.
Is used in the scanner unit 4, and the transfer request signal RQ from the scanner unit 4 is connected to the transfer request signal input terminal 20.
0 is input.

The channel CH1 is used, for example, in the image processing section 5, and the transfer request signal RQ1 from the image processing section 5 is input to the transfer request signal input terminal 21. The channel CH2 is used, for example, in the printer unit 6, and the transfer request signal RQ2 from the printer unit 6 is input to the transfer request signal input terminal 22.

Reference numerals 23, 24 and 25 are address registers provided respectively for the channels CH0, CH1 and CH2, and the register 2 for these addresses is provided.
Addresses in the memory that are the transfer destination or the transfer source of the data are stored in 3, 24, and 25. The CPU sets the registers 23, 24 and 25 for these addresses.

Reference numerals 26, 27 and 28 denote transfer data word number registers provided corresponding to the channels CH0, CH1 and CH2, respectively. The transfer data word number registers 26, 27 and 28 are transferred to these registers. The number of words of data is stored. The CPU sets the registers 26, 27 and 28 for the number of transfer data words.

Further, 29 is a selector for selecting the address register 23 and the transfer data word number register 26, 30 is a selector for selecting the address register 24 and the transfer data word number register 27, 31 Is an address register 25 and a transfer data word number register 2
8 is a selector for selecting 8

Further, 32 is each channel CH0, CH1,
Selector 29 provided for CH2 ...
Is a selector for selecting 30, 31, ..., This selector 32 selects the selector of the channel to which the transfer request signal is input, and when a plurality of transfer request signals are input at the same time, It is configured to make the selection based on the set priority.

Further, 33 is an arithmetic unit for adding addresses and subtracting the number of words of transfer data, 34 is an address register for storing an address output from the arithmetic unit 33, and 3 is an address register.
Reference numeral 5 is a transfer data word number register that stores the number of words of transfer data output from the arithmetic unit 33.

Further, 36 is a clock input terminal to which a system clock CK1 as shown in FIG. 2A is inputted from the outside, 37 is a D flip-flop, and this D flip-flop 37 is a frequency divider by two. And a clock C at the positive-phase output terminal Q and the negative-phase output terminal Q, respectively.
The clocks CK2 and CK2 bars as shown in FIGS. 2B and 2C, which are obtained by dividing K1 by two, are output.

Of the clocks CK2 and CK2, the clock CK2 is, for example, the selectors 29-3.
1, the arithmetic unit 33, and the address register 34, and the clock CK2 bar is supplied to, for example, the transfer data word number register 35.

Here, the address register 23 is brought into a load state when the clock CK2 is at the L level when the transfer request signal RQ0 is input. Also,
The address register 24 is brought into a load state when the clock CK2 is at the L level when the transfer request signal RQ1 is input. Further, the address register 25 is brought into a load state when the transfer request signal RQ2 is input and the clock CK2 is at the L level.

Further, the register 26 for the number of transfer data words
Is loaded when the transfer request signal RQ0 is input and the clock CK2 bar is at the L level. In addition, the register 27 for the number of transfer data words is provided with a clock CK when the transfer request signal RQ1 is input.
When the 2 bar is at L level, it is in a loaded state. Also,
The transfer data word number register 28 is provided with a transfer request signal RQ.
When 2 is input, the clock CK2 bar is L
If it is a level, it is loaded.

Further, in the arithmetic unit 33, the clock CK2 is H level.
In the case of the level, the operation of "+1" is performed as shown in FIG. 2 (E), and in the case of the L level, the operation of "-1" is performed.

That is, as will be described later, when the clock CK2 is at the H level, the addresses stored in the address registers 23, 24 or 25 are added, and when the clock CK2 is at the L level, the number of transfer data words is used. The register 26, 27 or 28 is configured to subtract the number of words of the transfer data.

Further, the selectors 29, 30 and 31 respectively select the address registers 23, 24 and 25 when the clock CK2 is at the H level, and respectively select the transfer data word number when the clock CK2 is at the L level. Of the registers 26, 27, 28 are selected.

The address register 34 is shown in FIG.
As shown in (G), when the clock CK2 is at the H level, the output of the arithmetic unit 33 is stored, and when the clock CK2 is at the L level, the stored contents are output. Note that FIG. 2H shows the register 3 for this address.
4 shows the output state of the stored contents of No. 4.

Further, the register 35 for the number of transfer data words
As shown in FIG. 2 (I), the clock CK2 bar is at H level.
In the case of the level, the output of the arithmetic unit 33 is stored and the clock C
When the K2 bar is at the L level, the stored contents are output. Note that FIG. 2 (J) shows the output state of the stored contents of the register 35 for the number of transfer data words.

Therefore, for example, as shown in FIG. 2D, when the H-level transfer request signal RQ0 is input from the scanner section 4 of the channel CH0, the selector 32 selects the selector 29 of the channel CH0. Also, at this time,
The selector 29 selects the address register 23 at the H level of the clock CK2.

As a result, the address previously stored in the address register 23 by the CPU 1 is the selector 2
Transferred to the memory 2 via 9, 32,
It is transferred to the computing unit 33, and in this computing unit 33,
As shown in (E), "+1" is calculated, and
The result is output as shown in (F) and stored in the address register 34 as shown in FIG. 2 (G).

Next, when the clock CK2 becomes L level, the address register 23 is loaded, and the contents stored in the address register 34 are stored in the address register 23. At this time, the clock CK
Since 2 bar becomes H level, the selector 29 selects the register 26 for the number of transfer data words.

As a result, the number of words of transfer data previously stored in the register 26 for the number of words of transfer data is transferred to the arithmetic unit 33 via the selectors 29 and 32 by the CPU 1.
In the computing unit 33, as shown in FIG.
1 "is performed, the result is output as shown in FIG. 2 (F), and is stored in the transfer data word number register 35 as shown in FIG. 2 (I).

Next, when the clock CK2 bar becomes L level, the transfer data word number register 26 is loaded, and the contents stored in the transfer data word number register 35 are stored in the transfer data word number register 26. .. Further, at this time, the clock CK2 becomes the H level, so the selector 29 selects the address register 23.

Thereafter, the same operation is repeated until the number of words of the transfer data stored in the register 26 for the number of transfer data words becomes "0". In addition, the transfer request signal R
The same operation is performed when Q0, RQ1 and RQ2 are input.

As described above, in this embodiment, as shown in FIG.
Instead of providing the counters 13 to 18 as shown in FIG. 2, instead of providing the registers 23 to 28 for each channel, the arithmetic unit 33 is supposed to add addresses for all channels and count the number of words of transfer data. ..

Here, the registers 23 to 28 can be constructed with a circuit size significantly smaller than that of the counters 13 to 18. Therefore, according to this embodiment,
The circuit scale can be made smaller than that of the conventional DMA controller shown in FIG. 4 in which two counters are provided for each channel.

Further, according to this embodiment, the system clock CK1 and the system clock CK1 are D
A clock CK2 that is divided by the flip-flop 37,
CK2 bar and transfer request signals RQ0, RQ1, RQ2.
.. and are used to control internal circuits, so circuits for generating complex timing signals,
No complicated control circuit is required.

[0042]

According to the present invention, a register for storing an address of a transfer destination or a transfer source of transfer data and a register for storing the number of words of transfer data are provided for each channel, and addresses for all channels are provided. Since the addition or subtraction and the number of words of the transfer data are counted by one arithmetic means, the circuit scale can be made smaller than that of the conventional DMA controller having two counters for each channel. Therefore, the number of channels can be increased with a circuit scale smaller than the conventional one, and the cost can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing a part of an embodiment of the present invention.

FIG. 2 is a time chart for explaining the operation of the embodiment of the present invention.

FIG. 3 is a block diagram showing a part of a facsimile device.

FIG. 4 is a block diagram showing a part of a conventional DMA controller.

[Explanation of symbols]

 23-25 Address register 26-28 Transfer data word number register 29-32 Selector 34, 35 register

Claims (3)

[Claims] 1. A register for storing an address of a transfer destination or a transfer source of transfer data and a register for storing the number of words of the transfer data are provided for each channel, and one operation is shared by all the channels. A DMA controller characterized in that means is provided, and the arithmetic means is configured to add or subtract addresses for all channels and count the number of words of transfer data. 2. The arithmetic means is provided with one arithmetic unit and two registers for storing the output of the arithmetic unit, and one and the other of these two registers are used for address and the number of transfer data words, respectively. The DMA controller of claim 1, wherein the DMA controller is configured to be used for. 3. A system clock supplied from the outside, a clock obtained by internally dividing the system clock supplied from the outside, and a transfer request signal supplied from the peripheral circuit section. 3. The control circuit according to claim 1, wherein the internal circuit is controlled.
The described DMA controller.